INPUT CAPTURE WITH ST62 16-BIT AUTO-RELOAD TIMER

Transcription

1 APPLICATION NOTE INPUT CAPTURE WITH ST62 -BIT AUTO-RELOAD TIMER by -bit Micro Appliction Tem 1 INTRODUCTION This note presents how to use the ST62 -bit Auto-Relod Timer (ARTimer) to mesure durtions or frequencies of n input signl. An exmple shows how to cpture n input signl to mke n output signl with the sme frequency s input signl but with duty cycle equl to 50%. 1.1 BIT AUTO-RELOAD TIMER DESCRIPTION This timer is -bit downcounter timer with prescler (see Figure 1.). It includes uto-relod PWM, cpture nd compre cpbility with two input(cp1,cp2) nd two output pins(ovf,pwm). It is controlled by the following registers ( bit): Sttus control registers (SCR1, SCR2, SCR3, SCR4) Cpture register high (CPH) nd low (CPL). For the totl -bit the register is CP. Msk register high (MASKH) nd low (MASKL). For the totl -bit the register is MASK. Decrementl counter register (TC with -bit) Compre register high (CMPH) nd low (CMPL). For the totl -bit the register is CMP. Relod/Cpture register high (RLCPH) nd low (RLCPL). For the totl -bit the register is RLCP. AN1050/109 1/9 1

2 The prescler rtio cn be progrmmed to choose the timer input frequency f int (see Tble 1 ). Figure 1. -bit Auto-Relod Timer Block Digrm -BIT MCU DATA BUS SCR1 SCR2 SCR3 SCR4 BUS INTERFACE -BIT DATA BUS CMP MASK RLCP CP PSC rtio f int Compre Compre to 0 TC f osc PWM OVF INT CONTROL LOGIC CP1 CP2 2/9

3 1.2 CAPTURE MODE This cn be used to mesure time durtion or frequencies (see Figure 2.).This mode is used to mesure the time elpsed between two edges of one or two externl signl. Ech edge cou be rising or flling depend on initilistion. With the -bit TC downcounter nd with f osc to Mhz, signl of 4ms durtion cn be mesured with resolution of 1/3276. Exmple: Let's mesure the time elpsed between two rising edges on CP2: The -bit CP vlue contins the time between the two CP2 rising edges nd will be divided by two to be loded in the -bit CMP register. The cpture mode uses the CP2 triggered restrt mode with CP2 event detection (RDSEL2=1, RDSEL1=0 of SCR2 register). It s men tht ech CP2 edge sets off the cpture of the TC vlue in the CP register nd then relods TC register with the RLCP vlue. The CP2 interrupt is enbled (CP2IEN=1 of SCR3 register) nd CMP interrupt is enbled (CMPIEN=1 of SCR3 register) to mnge the output bit PA2. In the CP2 interrupt sub-progrm the output bit PA2 is set to 1. In the CMP interrupt sub-progrm the output bit PA2 is set to 0. The min progrm clcultes the division by 2 of the cptured -bit vlue nd sves it in NewCMPh nd NewCMPl. The prescler rtio must be progrmmed ccording to the expected durtion to mesure. In this exmple it is progrmmed to: prescler rtio =, clock source = f osc = Mhz. The period to mesure must be in the rnge of 250µs to 133ms. The shring of -bit dt between the min progrm nd the interrupt sub-progrm obliges to disble the interruption for ech hndling of this dt in the min progrm. This cuses jitters of up to 30µs. The dely between the input signl ctive edge nd the output signl is of 36µs. The RLCP register is lod with FFFFh to void subtrction to clculte the dely between the CP2 edge nd the compre vlue reched by the TC vlue. Tble 1. Prescler Progrmming Rtio PSC2 PSC1 PRESCALER Rtio 0 0 Clock Disbled /9

4 Figure 2. TC, CP nd CMP vlue evolution synchronized with the input CP2. CP2 CP vlue CMP vlue= previous CP vlue divide by 2 relod t TC register 0 t MASK&TC=MASK&CMP cpture PA2 bit ouput t 4/9

5 Progrm exmple **************ST6230 Auto-Relod -bit Cpture mode ****************** object: Give n output TTL squre siqnl t the sme frequency of the no symmetricl TTL input signl input : TTL signl in the rnge of 7.5Hz to 4000Hz on CP2 output: TTL signl with the sme frequency of CP2 but with duty cycle of 50%. The signl hs dely of 36µs nd jitters of 30µs with clock frequency of Mhz. uthor: Jen-Luc CREBOUW.vers "st6230".romsize dt registers ***.input "623x.sm" dt RAM *** templ.def 04h ; low byte of the divider by two temph.def 05h ; high byte of the divider by two NewCMPl.def 06h ; low byte of the result divider NewCMPh.def 07h ; high byte of the result divider dt.def 0h ; dt copy of the A port sve_cpl.def 09h ; sve the CP hight sve_cph.def 0h ; sve the CP low ************************ INITIALIZATION *********************************.org 00h reset ART Initilistion *** i SCR1,0F0h ; prescl by to hve f int =.5 Mhz ; Relod mode ; Runres ; No interrupt with overflow ; Reset mode for OVFMD i SCR2,02h ; CP1 input interrupt disble ; CP2 triggered restrt mode with CP2 event ; detection i SCR3,0D0h ; CP2 polrity with rising edge 5/9

6 ; CP2 interrupt enble ; Compre interrupt enble ; Compre to zero interrupt disble i SCR4,0h ; Overflow output disble ;PWM output disble i RLCPH,0FFh ; RLCP register to FFFFh i RLCPL,0FFh ; i CMPH,0FFh ; CMP register to FF00h i CMPL,000h ; i MASKH,0FFh ; MASK = 0FFFFh i MASKL,0FFh PortA initilistion for output bit 2 nd CP2 input i ddr,04h i or,04h clr dt, ; dt = 0 GENERAL INTERRUPT *** i ior,10h ;Enbles ll interrupts. **************************Min progrm******************************** ********divide the CP vlue by two to lod CMP register with ********** PULSE: red the previous cpture out of interrupt to void sve_cpl nd sve_cph from different CP vlue i ior,00h ; disbles ll interrupts.,sve_cpl templ,,sve_cph i ior,10h ; Enbles ll interrupts. temph, divide by two temp (-bit) clr,templ templ, clr,temph 6/9

7 temph, jrnc no_1,templ ddi,00h templ, no_1:,temph ddi,00h temph,,templ store the next CMP vlue out of interrupt i ior,00h ; disbles ll interrupts. NewCMPl,,temph NewCMPh, i ior,10h ; Enbles ll interrupts. jp PULSE ***********************End of Min progrm**************************** ***********************UART IT mngement***************************** it_urt: x, ; sve if compre interrupt jrs 5,SCR3,it_cp2,dt ; output port PA2 = 0 dr, set 2,dt ; dt bit 2 = 1 res 3,SCR3 ; reset CMPFLG,x ; restore it_cp2: else CP2 interrupt,dt ; output port PA2 = 1 dr, res 2,dt ; dt bit 2 = 0 res 5,SCR3 ; reset CP2FLG 7/9

8 res 5,SCR2 ; reset CP2ERR,CPH ; red CP register nd sve the -bit vlue sve_cph, ; in sve_cph nd sve_cpl,cpl sve_cpl,,newcmph CMPH, ; store NewCMPh nd NewCMPl in CMP to hve,newcmpl ; CMP = previous CP / 2 CMPL,,x ; restore ********************End of UART IT mngement************************* ***************** Restrt nd interrupt Vectors ************************.org 0ff0h ; FF0h jp it_urt ; FF2h ; FF4h ; FF6h.org 0ffch nmi nop res jp reset /9

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