ECE 274 Digital Logic. Digital Design. Datapath Components Registers. Datapath Components Register with Parallel Load

Transcription

1 ECE 274 igitl Logic Multifunction Registers igitl esign igitl esign Chpter 4: Slides to ccompny the textbook igitl esign, First Edition, by Frnk Vhid, John Wiley nd Sons Publishers, Copyright 27 Frnk Vhid Instructors of courses requiring Vhid's igitl esign textbook (published by John Wiley nd Sons) hve permission to modify nd use these slides for customry course-relted ctivities, subject to keeping this copyright notice in plce nd unmodified. These slides my be posted s unnimted pdf versions on publicly-ccessible course websites.. PowerPoint source (or pdf with nimtions) my not be posted to publicly-ccessible websites, but my be posted for students on internl protected sites or distributed directly to students by other electronic mens. Instructors my mke printouts of the slides vilble to students for resonble photocopying chrge, without incurring roylties. Any other use requires explicit permission. Instructors my obtin PowerPoint source or obtin specil use permissions from Wiley see for informtion. Registers 4.2 Register with Prllel Lod Cn store dt, very common in dtpths Bsic register of Ch 3: Loded every cycle Useful for implementing FSM -- stores encoded stte For other uses, my wnt to lod only on certin cycles b clk Combintionl logic s s Stte register n n x Add 2x mux to front of ech flip-flop Register s lod input selects mux input to pss Either existing flip-flop vlue, or new vlue to lod lod I 2 I I 4-bit register clk 3 2 Bsic register lods on every clock cycle How extend to only lod on certin cycles? 3 4

2 Shift Registers Shift Registers Move ech bit one position right Shift in to leftmost bit before shift right fter shift right Wht is the result fter shifting four times to the right?. Shift Register Connect register s flip-flop s outputs to next flip-flop s input This design wou lwys shift on every clock cycle How cn we control it? Shift Register To llow register to either shift or retin, use 2x muxes : mens retin, shift : vlue to shift in My be, or Note: Cn esily design shift register tht shifts left insted Rotte Register Rotte right Like shift right, but leftmost bit comes from rightmost bit before shift right fter shift right 7 2

3 Register Exmple: Above-Mirror isply Shift Register Exmple: Above-Mirror isply Insted of connecting cr s computer to disply using 32 wires, cn we use fewer wires? To reduce wires: Cr s computer cn write vlue t time, lods into one of four registers with disply C d lod r eg 2 4 d lod r eg A i i d2 lod r eg2 I lod d3 e lod r eg3 T M Loded on clock edge i i i2 -bit 4 d i3 s s x y Erlier exmple: +2+ = wires from cr s computer to bove-mirror disply s four registers Better thn 32 wires, but still lot -- wnt fewer for smller wire bundles Use shift registers Wires: +2+=4 Computer sends one vlue t time, one bit per clock cycle Note: this line is bit, rther thn bits like before x y c d r eg T s s 2 4 i 4 d r eg A i i i d d2 r eg2 I e d3 shi f t r eg3 M i2 i3 9 Multifunction Registers Multifunction Registers Mny registers hve multiple functions Lod, shift, cler (lod ll s) And retin present vlue, of course Esily designed using muxes Just connect ech mux input to chieve desired function s s Functions: (unused - let's lod s) s s 2 3

4 Multifunction Registers with Seprte Control Register Tble Truth tble for combintionl circuit hs priority over hs priority hs priority hs priority s s Note Mintin vlue? c ombin tionl ci r cuit s s I 2 I I I 2 I I _in _in s = * * + ** + ** s = * * + 3 Register opertions typiclly shown using compct version of tble mens sme opertion whether vlue is or One expnds to two rows Two s expnd to four rows Put highest priority control input on left to mke reduced tble simple s s No t e Mintin vlue Ope r tion M i n tin v lue Shi f t le f t 4 Register esign Process Cn design register with desired opertions using simple four-step process 5 Register esign Exmple esired register opertions Synchronous cler, synchronous set, lod, shift left (with this priority) Step : etermine mux size 5 opertions: bove, plus mintin present vlue (don t forget this one!) --> Use x mux Step 2: Crete mux opertion tble Step 3: Connect mux inputs Step 4: Mp control lines = *set s = *set * * + s = *set * + set s s s s s s Synchronous cler Synchronous set n In Set to ll s Cler to ll s from n- 6 4

5 Register esign Exmple I 2 I I set combintionl circuit s s I 2 I I _in 3 2 _in 3 2 Step 4: Mp control lines = *set s = *set * * + s = *set * + set s s Set to ll s Cler to ll s 7 5