CPE 200L LABORATORY 2: DIGITAL LOGIC CIRCUITS BREADBOARD IMPLEMENTATION UNIVERSITY OF NEVADA, LAS VEGAS GOALS:
|
|
- Kimberly Riley
- 6 years ago
- Views:
Transcription
1 CPE 200L LABORATORY 2: DIGITAL LOGIC CIRCUITS BREADBOARD IMPLEMENTATION DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: In this l, the sic logic circuits will e uilt on the redord. Wiring circuits from the schemtic, using pproprite ICs, using the redords nd trouleshooting in generl re the min gols of this l. BACKGROUND: IMPLEMENTING FUNCTIONS ON THE BREADBOARD Min rules / steps to get circuit working exmple for function F = + : 1. Split function into seprte modules. For function F there will e module nd module '' 2. Implement nd test modules seprtely 3. Connect modules nd test 4. It is possile, tht the chip is fulty. To mke sure the chip is working, connect +5V to VCC, 0V to GND, nd connect one gte nd test its opertion. Other test method is to use the IC tester. You ll find them in the ECE Ls: DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 1
2 Figure 1. Digitl IC Tester ville in ECE Ls Implementtion of F = + function. Implementing module: Implement AND gte, nd verify its opertion y connecting the LED in series with 100Ω resistor y y Plce chip, nd power it y connecting +5V to VCC, nd 0V to GND Connect inputs nd outputs: to pin 1, to pin 2, y to pin 3 Figure 2. Setup of AND gte with LED Connect LED to the output y: plce LED s shown ove longer led to y, shorter to the resistor. Resistor connects shorter LED led to the ground (0V). At this point, the module is tested nd working. Next step: implementing the '' module. You need to invert the nd signls first, using NOT gtes. ' ' ' ' '' Plce chip, nd power it y connecting +5V to VCC, nd 0V to GND Connect inputs nd outputs: to pin 1, ' to pin 2, to pin 3, ' to pin 4 Use ' nd ' s inputs to AND gte. Connect '' to LED nd test. Figure 3. Setup of NOT nd AND gte DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 2
3 Now, hving the nd '' modules tested, you connect them using OR gte. ' ' F '' Plce chip, nd power it y connecting +5V to VCC, nd 0V to GND. Connect '' nd, the output of OR gte is F Figure 4. Connecting modules Rememer to hve just single one wire for signl, nd just single one wire for signl. 7-SEGMENT DISPLAY To represent the digitl signls either LEDs or 7-segment displys cn e used. LEDs re suitle to represent single-it inry signls, while 7-segments re used to represent multi-it numers. Binry coded deciml (BCD) numers re often displyed on seven segment disply using BCD to seven segment decoder such s 7447, which we use in this l. Figure 7 illustrtes BCD to seven segment disply circuit. Figure 5. 7-segment disply DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 3
4 There re two configurtions of 7-segment displys: common node nd common cthode. In this l we use common node type, wht cn e illustrted s follows: Figure 6. Common node configurtion Figure 10 shows complete schemtics for 7-segment nd 7447 driver configurtion tkes BCD numer s the input nd converts to 7-signl formt, s shown in truth tle further. Do not forget out the 2.4 kω resistor, to limit the current. Figure 7. Schemtics for 7-seg with 7447 configurtion DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 4
5 FULL ADDER Full dder hs three inputs nd two outputs. The first two inputs re A nd B (oth re 1-it numers) nd the third input is n input crry designted s Cin. Full dder cn dd two its together, tking crry from the next lower order of mgnitude, nd sending crry to the next higher order of mgnitude. Figure 8. Full Adder setup Tle 1. Truth tle for Full Adder A B CIN S COUT MULTIPLEXERS AND DEMULTIPLEXERS A multiplexer (or mux) is device tht selects one of severl nlog or digitl input signls nd forwrds the selected input into single line. A multiplexer of 2n inputs hs n select lines, which re used to select which input line to send to the output. Multiplexers re minly used to increse the mount of dt tht cn e sent over the network within certin mount of time nd ndwidth. A multiplexer is lso clled dt selector. Demultiplexer works the opposite wy: it tkes one dt input nd hs multiple outputs. The ctive output is selected using selector inputs. An electronic multiplexer mkes it possile for severl signls to shre one device or resource, for exmple one A/D converter or one communiction line, insted of hving one device per input signl. An electronic multiplexer cn e considered s multiple- input, single-output switch. The schemtic symol for multiplexer is n isosceles trpezoid with the longer prllel DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 5
6 side contining the input pins nd the short prllel side contining the output pin. The schemtic in Figure 9 shows 2-to-1 multiplexer with the s wire controlling the desired input to the output. It cn e expressed s truth tle s shown in Tle 1: ) input ctive (s=0) ) input ctive (s=1) Figure 9. Input selection for 2-to-1 multiplexer Tle 2. Truth tle of 2-to-1 multiplexer S A B Z to-1 multiplexer hs 4 dt inputs nd two selector inputs. According to the vlues of selector inputs, one of four dt inputs is ctive nd signls from this input re pssed to the output of multiplexer. Figure 10 shows the exmple configurtion of 4-to-1 multiplexer. DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 6
7 Figure to-1 multiplexer ARITHMETIC-LOGIC UNIT (ALU) Arithmetic logic unit is the most importnt element of microprocessor which performs oth mth nd logic functions. An ALU lods dt from input registers, n externl Control Unit then tells the ALU wht opertion to perform on tht dt, nd then the ALU stores its result into n output register. ALU tkes mny opernds s input dt, then depending on the opertion which is currently progrmmed in opertion selector, it performs this opertion on input opernd nd produces the result. The result is presented on the ALU s output. Figure 11. Block schemtic of ALU ) logic opertion ) rithmetic opertion Figure 12. Logic nd rithmetic opertion in ALU In this l, we will e working on ALU which performs three functions: logicl AND: y = logicl OR: y = + logicl XOR: y = rithmetic ddition: y = + DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 7
8 Figure 13. Smple implementtion of 1-it ALU with AND, OR, ADD functions. LAB DELIVERIES: PRELAB: 1. Bredords: 1. Red the tutoril on how to use redord. The written tutoril cn e found on our wesite t: it ALU: 1. Design 1-it ALU with AND, OR, XOR, ADD functions. Simulte gte level schemtic in Qurtus. 3. Prel deliveries Include in the prel document: 1. Your design of 1-it ALU 2. Simultion wveforms of 1-it ALU DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 8
9 LAB EXPERIMENTS To find the chip implementing the desired function, or to look for the dtsheet regrding the specific chip, go to 1. Experiment 1: Simple circuit 1. Implement the following circuit on the redord, using the 74xx chips. Function: y = + c Figure 14. Schemtic for experiment 1 Use the tutoril from the introduction section of this document s guide for the implementtion. 2. Experiment 2: Full Adder 1. Crete full dder schemtic s shown of Figure 8 2. Crete mcro of Full dder to use for hierrchicl design. 3. Perform simultion nd verify tht it mtches FA truth tle shown on Tle Experiment 3: Implementing dder using IC 1. Use the 7483 IC (4-it full inry dder) to implement the 2-it ddition Figure chip DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 9
10 2. Test the opertion for 6 smple comintions of your choice: 3 of them not including crry, 3 of them including crry. 4. Experiment 4: 1-it ALU 1. Build 1-it ALU with AND, OR, XOR, FA functions. 2. For the Full Adder, you cn use the sme circuit s in experiment 1, or the IC chip 3. Design the 1-it ALU sed on the Figure 13. POSTLAB REPORT: Include the following elements in the report document: Section Element 1 Theory of opertion Include rief description of every element nd phenomenon tht ppers during the experiments. 2 Prel report Results of the experiments Experiment Experiment Results 1. Truth tle. Picture of the circuit on the redord 3 2. Truth tle. Picture of the circuit on the redord 3. Truth tle. Picture of the circuit on the redord 4. Truth tle. Picture of the circuit on the redord Answer the questions Question no. Question 4 1 Wht is the difference etween Hlf Adder nd Full Adder? Descrie oth. 2 Briefly chrcterize the IC7483 chip. 3 Wht re sic cpilities of Digitl IC Testers? 5 Conclusions Write down your conclusions, things lerned, prolems encountered during the l nd how they were solved, etc. References: 1. Introduction to redords: 2. Dtsheets of 7400 series chips: 3. Dtsheet of it inry dder: DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 10
CPSC 121: Models of Computation Lab #2: Building Circuits
CSC 121: Models of Computti L #2: Building Circuits Ojectives In this l, ou will get more eperience with phsicl logic circuits using The Mgic Bo. You will lso get our first eposure to Logisim, tool for
More informationCPE 200L LABORATORY 3: SEQUENTIAL LOGIC CIRCUITS UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND: SR FLIP-FLOP/LATCH
CPE 200L LABORATORY 3: SEUENTIAL LOGIC CIRCUITS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: Learn to use Function Generator and Oscilloscope on the breadboard.
More informationECE 274 Digital Logic. Digital Design. Datapath Components Registers. Datapath Components Register with Parallel Load
ECE 274 igitl Logic Multifunction Registers igitl esign 4. 4.2 igitl esign Chpter 4: Slides to ccompny the textbook igitl esign, First Edition, by Frnk Vhid, John Wiley nd Sons Publishers, 27. http://www.ddvhid.com
More informationNORTHWESTERN UNIVERSITY TECHNOLOGICAL INSTITUTE
NORTHWESTERN UNIVERSITY TECHNOLOGICL INSTITUTE ECE 270 Experiment #8 DIGITL CIRCUITS Prelab 1. Draw the truth table for the S-R Flip-Flop as shown in the textbook. Draw the truth table for Figure 7. 2.
More informationChapter 1: Introduction
Chpter : Introduction Slides to ccompny the textbook, First Edition, by, John Wiley nd Sons Publishers, 7. http://www.ddvhid.com Copyright 7 Instructors of courses requiring Vhid's textbook (published
More informationECE Lab 5. MSI Circuits - Four-Bit Adder/Subtractor with Decimal Output
ECE 201 - Lab 5 MSI Circuits - Four-Bit Adder/Subtractor with Decimal Output PURPOSE To familiarize students with Medium Scale Integration (MSI) technology, specifically adders. The student should also
More informationDev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET
Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET LABORATORY MANUAL EXPERIMENT NO. 1 ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE :
More informationPHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops
PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops Objective Construct a two-bit binary decoder. Study multiplexers (MUX) and demultiplexers (DEMUX). Construct an RS flip-flop from discrete gates.
More informationLab #6: Combinational Circuits Design
Lab #6: Combinational Circuits Design PURPOSE: The purpose of this laboratory assignment is to investigate the design of combinational circuits using SSI circuits. The combinational circuits being implemented
More informationApplications to Transistors
CS/EE1012 INTRODUCTION TO COMPUTER ENGINEERING SPRING 2013 LAYERED COMPUTER DESIGN 1. Introduction CS/EE1012 will study complete computer system, from pplictions to hrdwre. The study will e in systemtic,
More informationHomework 1. Homework 1: Measure T CK-Q delay
Homework Find the followin for 3nm, 9nm, 65nm nd 45nm, 32nm, 22nm MO technoloies Effective chnnel lenth Equivlent nd physicl oxide thickness upply volte (Vdd) rw the lyout for the followin Flip-Flop (use
More informationExperiment (6) 2- to 4 Decoder. Figure 8.1 Block Diagram of 2-to-4 Decoder 0 X X
8. Objectives : Experiment (6) Decoders / Encoders To study the basic operation and design of both decoder and encoder circuits. To describe the concept of active low and active-high logic signals. To
More informationChapter 8 Functions of Combinational Logic
ETEC 23 Programmable Logic Devices Chapter 8 Functions of Combinational Logic Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Basic Adders
More informationDIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITL TECHNICS Dr. álint Pődör Óbuda University, Microelectronics and Technology Institute 10. LECTURE (LOGIC CIRCUITS, PRT 2): MOS DIGITL CIRCUITS II 2016/2017 10. LECTURE: MOS DIGITL CIRCUITS II 1.
More informationLecture 3: Circuits & Layout
Lecture 3: Circuits & Lyout Slides courtesy of eming Chen Slides sed on the initil set from vid Hrris CMOS VLSI esign Outline CMOS Gte esign Pss Trnsistors CMOS Ltches & Flip-Flops Stndrd Cell Lyouts Stick
More informationThe Official IDENTITY SYSTEM. A Manual Concerning Graphic Standards and Proper Implementation. As developed and established by the
The Officil ISKCON IDENTITY SYSTEM A Mnul Concerning Grphic Stndrds nd Proper Implementtion As developed nd estlished y the COMMUNICATIONS DEPARTMENT of the INTERNATIONAL SOCIETY FOR KRISHNA CONSCIOUSNESS
More informationChapter 4: Table of Contents. Decoders
0/26/20 OF 7 Chapter 4: Table of Contents Decoders Table of Contents Modular Combinational Logic - Decoders... 2 The generic decoder... 2 The 7439 decoder... 3 The decoder specification sheet... 4 decoder
More informationECE 274 Digital Logic. Digital Design. Sequential Logic Design Controller Design: Laser Timer Example
ECE 274 Digitl Logic Sequentil Logic Design Sequentil Logic Design Process Digitl Design 3.4 3.5 Digitl Design Chpter 3: Sequentil Logic Design -- Controllers Slides to ccompny the tetook Digitl Design,
More informationGRABLINKTM. FullTM. - DualBaseTM. - BaseTM. GRABLINK Full TM. GRABLINK DualBase TM. GRABLINK Base TM
GRLINKTM FullTM - DulseTM - setm Full-Fetured se, Medium nd Full Cmer Link Frme Grbbers GRLINK Full TM GRLINK Dulse TM GRLINK se TM www.euresys.com info@euresys.com Copyright 011 Euresys s.. elgium. Euresys
More informationSequencer devices. Philips Semiconductors Programmable Logic Devices
hilips emiconductors rogrmmle Logic Devices equencer devices INTODUTION Ten yers go, in their serch for strightforwrd solution to complex sequentil prolems, hilips emiconductors originted rogrmmle Logic
More informationgate symbols will appear in schematic Dierent of a circuit. Standard gate symbols have been diagram Figures 5-3 and 5-4 show standard shapes introduce
chapter is concerned with examples of basic This circuits including decoders, combinational xor gate and parity circuits, multiplexers, comparators, adders. Those basic building circuits frequently and
More informationFUNCTIONS OF COMBINATIONAL LOGIC
FUNCTIONS OF COMBINATIONAL LOGIC Agenda Adders Comparators Decoders Encoders Multiplexers Demultiplexers Adders Basic Adders Adders are important in computers other types of digital systems in which numerical
More informationECE 2274 Pre-Lab for Experiment Timer Chip
ECE 2274 Pre-Lab for Experiment 6 555 Timer Chip Introduction to the 555 Timer The 555 IC is a popular chip for acting as multivibrators. Go to the web to obtain a data sheet to be turn-in with the pre-lab.
More informationWE SERIES DIRECTIONAL CONTROL VALVES
WE SERIES DIRECTIONL CONTROL VLVES ISO4401 Size 03 ulletin 80340- DESIGNTION PGE Fetures nd Generl Description 3 Specifictions 4 Operting Limits 5 Tle of Contents Performnce Dt 6 Stndrd Models 7-8 Dimensions
More informationLAERSKOOL RANDHART ENGLISH GRADE 5 DEMARCATION FOR EXAM PAPER 2
LAERSKOOL RANDHART ENGLISH GRADE 5 DEMARCATION FOR EXAM PAPER 2 Dte: 15 Octoer 2018 Time: 2 hours Totl: 25 mrks SECTION C: ESSAY (15 MARKS) Write n essy out one of the given topics. Your essy should e
More informationEXPERIMENT 8 Medium Scale Integration (MSI) Logic Circuits
ELEC 00 Laboratory Manual Experiment 8 PRELAB Page of EXPERIMT 8 Medium Scale Integration (MSI) Logic Circuits Introduction In this lab you will learn to work with some simple MSI (medium scale integration)
More informationSeSSION 9. This session is adapted from the work of Dr.Gary O Reilly, UCD. Session 9 Thinking Straight Page 1
G N I K N I THmily TrHeeT FSTRAIG SeSSION 9 This session is dpted from the work of Dr.Gry O Reilly, UCD Session 9 Thinking Stright Pge 1 Lerning Objectives ful thinking tht To look t how we cn spot unhelp
More informationDIGITAL ELECTRONICS: LOGIC AND CLOCKS
DIGITL ELECTRONICS: LOGIC ND CLOCKS L 6 INTRO: INTRODUCTION TO DISCRETE DIGITL LOGIC, MEMORY, ND CLOCKS GOLS In this experiment, we will learn about the most basic elements of digital electronics, from
More informationEXPERIMENT #6 DIGITAL BASICS
EXPERIMENT #6 DIGITL SICS Digital electronics is based on the binary number system. Instead of having signals which can vary continuously as in analog circuits, digital signals are characterized by only
More informationCombinational Logic Design
Lab #2 Combinational Logic Design Objective: To introduce the design of some fundamental combinational logic building blocks. Preparation: Read the following experiment and complete the circuits where
More informationIS1500 (not part of IS1200) Logic Design Lab (LD-Lab)
Introduction IS1500 (not part of IS1200) Logic Design Lab (LD-Lab) 2017-10-26 The purpose of this lab is to give a hands-on experience of using gates and digital building blocks. These build blocks are
More informationMODULAR DIGITAL ELECTRONICS TRAINING SYSTEM
MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM MDETS UCTECH's Modular Digital Electronics Training System is a modular course covering the fundamentals, concepts, theory and applications of digital electronics.
More informationCorporate Logo Guidelines
Corporte Logo Guidelines The llpy logo Inspirtion The logo is inspired by llpy s commitment to the world of secure nd complete pyment services. The solid circle surrounding the nme represents bullet proof
More informationDEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Lab Manual for Computer Organization Lab
More informationEngineering College. Electrical Engineering Department. Digital Electronics Lab
Engineering College Electrical Engineering Department Digital Electronics Lab Prepared by: Dr. Samer Mayaleh Eng. Nuha Odeh 2009/2010-1 - CONTENTS Experiment Name Page 1- Measurement of Basic Logic Gates
More informationEngineer To Engineer Note
Engineer To Engineer Note EE-203 Technicl Notes on using Anlog Devices' DSP components nd development tools Contct our technicl support by phone: (800) ANALOG-D or e-mil: dsp.support@nlog.com Or visit
More informationLOGOMANUAL. guidelines how to use Singing Rock logotype. Version 1.5 English. Lukáš Matěja
LOGOMANUAL guidelines how to use Singing Rock logotype In cse of ny questions, contct our grphic designer Lukáš Mtěj +420 775 282 064 luks.mtej@singingrock.cz Version 1.5 English PRIMARY LOGOTYPE Primry
More informationDigital Circuits ECS 371
Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 0 Office Hours: BKD 360-7 Monday 9:00-0:30, :30-3:30 Tuesday 0:30-:30 Announcement HW4 posted on the course web site Chapter 5:
More informationOutline. Circuits & Layout. CMOS VLSI Design
CMO VLI esign Circuits & Lyout Outline Brief History CMO Gte esign Pss Trnsistors CMO Ltches & Flip-Flops tndrd Cell Lyouts tick igrms lide 2 Brief History 958: First integrted circuit Flip-flop using
More informationContents Circuits... 1
Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...
More informationDRAFT. Vocal Music AOS 2 WB 3. Purcell: Music for a While. Section A: Musical contexts. How is this mood achieved through the following?
Purcell: Music for While Section A: Musicl contexts Like the Bch Brndenurg Concerto No. 5 in Workook 1, this song y Henry Purcell ws composed during the Broque er. To understnd the music it is helpful
More informationDigital Logic. ECE 206, Fall 2001: Lab 1. Learning Objectives. The Logic Simulator
Learning Objectives ECE 206, : Lab 1 Digital Logic This lab will give you practice in building and analyzing digital logic circuits. You will use a logic simulator to implement circuits and see how they
More informationLOGICAL FOUNDATION OF MUSIC
LOGICAL FOUNDATION OF MUSIC philosophicl pproch Im Anfng wr die Tt Goethe, Fust CARMINE EMANUELE CELLA cecily@liero.it www.cryptosound.org NATURE OF MUSICAL KNOWLEDGE Musicl knowledge cn e thought s complex
More informationLaboratory Objectives and outcomes for Digital Design Lab
Class: SE Department of Information Technology Subject Logic Design Sem : III Course Objectives and outcomes for LD Course Objectives: Students will try to : COB1 Understand concept of various components.
More informationEE 210. LOGIC DESIGN LAB.
College of Engineering Electrical Engineering Department EE 210. LOGIC DESIGN LAB. (1 st semester 1426-27) Dr. Messaoud Boukezzata Office: EE 11 Phone: 063 8000 50 Ext 3152 1 College of Engineering Electrical
More informationYour Summer Holiday Resource Pack: English
Messge Activity to Prents: Sheet The summer holidys re here! To help keep your child entertined, we ve put together Summer Holidy Resource Pck. It s een produced to reduce summer holidy lerning loss nd
More informationLab #11: Register Files
Lab #11: Register Files Zack Mattis Lab: 3/21/17 Report: 3/26/17 Partner: Brendan Schuster Purpose In this lab, 4x4 register was designed and fully implemented onto a protoboard that emulates the local
More informationChapter 3: Sequential Logic Design -- Controllers
Chpter 3: Sequentil Logic Design -- Controllers Slides to ccompny the textbook, First Edition, by, John Wiley nd Sons Publishers, 27. http://www.ddvhid.com Copyright 27 Instructors of courses requiring
More informationOutline. Annual Sales. A Brief History. Transistor Types. Invention of the Transistor. Lecture 1: Circuits & Layout. Introduction to CMOS VLSI Design
Introduction to MO VLI esin Lecture : ircuits & Lyout vid Hrris Outline rief History MO Gte esin Pss Trnsistors MO Ltches & Flip-Flops tndrd ell Lyouts tick irms Hrvey Mudd ollee prin lide rief History
More informationEXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true.
EXPERIMENT: 1 DATE: VERIFICATION OF BASIC LOGIC GATES AIM: To verify the truth tables of Basic Logic Gates NOT, OR, AND, NAND, NOR, Ex-OR and Ex-NOR. APPARATUS: mention the required IC numbers, Connecting
More informationPhysics 323. Experiment # 10 - Digital Circuits
Physics 323 Experiment # 10 - Digital Circuits Purpose This is a brief introduction to digital (logic) circuits using both combinational and sequential logic. The basic building blocks will be the Transistor
More informationELEC 204 Digital System Design LABORATORY MANUAL
Elec 24: Digital System Design Laboratory ELEC 24 Digital System Design LABORATORY MANUAL : 4-bit hexadecimal Decoder & 4-bit Increment by N Circuit College of Engineering Koç University Important Note:
More informationDIGITAL ELECTRONICS LAB MANUAL FOR 2/4 B.Tech (ECE) COURSE CODE: EC-252
DIGITAL ELECTRONICS LAB MANUAL FOR /4 B.Tech (ECE) COURSE CODE: EC-5 PREPARED BY P.SURENDRA KUMAR M.TECH, Lecturer D.SWETHA M.TECH, Lecturer T Srinivasa Rao M.TECH, Lecturer Ch.Madhavi, Lab Assistant 009-00
More informationME 515 Mechatronics. Introduction to Digital Electronics
ME 55 Mechatronics /5/26 ME 55 Mechatronics Digital Electronics Asanga Ratnaweera Department of Faculty of Engineering University of Peradeniya Tel: 8239 (3627) Email: asangar@pdn.ac.lk Introduction to
More informationwalking. Rhythm is one P-.bythm is as Rhythm is built into our pitch, possibly even more so. heartbeats, or as fundamental to mu-
Ir melody- is sung without its rhythm, it immeditely loses much of its essence. P-.bythm is s fundmentl to mu- sic s pitch, possibly even more so. Rhythm is built into our bodies s hertbets, or s the motion
More informationChapter 5. Synchronous Sequential Logic. Outlines
Chpter 5 Synchronous Sequentil Logic Outlines Sequentil Circuits Ltches Flip-Flops Anlysis of Clocke Sequentil Circuits Stte Reuction n Assignment Design Proceure 2 5. Sequentil Circuits Sequentil circuits
More informationLaboratory 8. Digital Circuits - Counter and LED Display
Laboratory 8 Digital Circuits - Counter and Display Required Components: 2 1k resistors 1 10M resistor 3 0.1 F capacitor 1 555 timer 1 7490 decade counter 1 7447 BCD to decoder 1 MAN 6910 or LTD-482EC
More informationLab #12: 4-Bit Arithmetic Logic Unit (ALU)
Lab #12: 4-Bit Arithmetic Logic Unit (ALU) ECE/COE 0501 Date of Experiment: 4/3/2017 Report Written: 4/5/2017 Submission Date: 4/10/2017 Nicholas Haver nicholas.haver@pitt.edu 1 H a v e r PURPOSE The purpose
More informationLAB #6 State Machine, Decoder, Buffer/Driver and Seven Segment Display
LAB #6 State Machine, Decoder, Buffer/Driver and Seven Segment Display LAB OBJECTIVES 1. Design a more complex state machine 2. Design a larger combination logic solution on a PLD 3. Integrate two designs
More informationMassachusetts Institute of Technology Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Project Resources Project resources are allocated on a per
More informationMapping Arbitrary Logic Functions into Synchronous Embedded Memories For Area Reduction on FPGAs
Mpping Aritrry Logic Functions into Synchronous Emedded Memories For Are Reduction on FPGAs Gordon R. Chiu, Deshnnd P. Singh, Vlvn Mnohrrjh, nd Stephen D. Brown Toronto Technology Center, Alter Corportion
More informationAdvanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20
Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.
More informationApplication Support. Product Information. Omron STI. Support Engineers are available at our USA headquarters from
Omron STI Appliction Support Thnk you for your interest in Omron STI products. Plese contct Omron STI with your ppliction questions. Support Engineers re vilble t our U hedqurters from 4:00.m. until 5:00
More informationSoft Error Derating Computation in Sequential Circuits
Soft Error Derting Computtion in Sequentil Circuits Hossein Asdi Northestern University, ECE Dept. Boston, MA 02115 gsdi@ece.neu.edu Mehdi B. Thoori Northestern University, ECE Dept. Boston, MA 02115 mthoori@ece.neu.edu
More informationMinnesota State College Southeast
ELEC 2211: Digital Electronics II A. COURSE DESCRIPTION Credits: 4 Lecture Hours/Week: 2 Lab Hours/Week: 4 OJT Hours/Week: *.* Prerequisites: None Corequisites: None MnTC Goals: None Minnesota State College
More informationA New Concept of Providing Telemetry Data in Real Time
The Spce Congress Proceedings 1967 (4th) Spce Congress Proceedings Apr 3rd, 12: AM A New Concept of Providing Telemetry Dt in Rel Time John M. Bllock Pn Americn World Airwys, GMRD, Ptrick Air Force Bse,
More informationTRAINING KITS ON DIGITAL ELECTRONIC EXPERIMENTS. Verify Truth table for TTL IC s AND, NOT, & NAND GATES
TRAINING KITS ON DIGITAL ELECTRONIC EXPERIMENTS CEE 2800 Basic Logic Gates using TTL IC's (7 in 1) To verify the truth table For TTL AND, OR. NOT, NAND,NOR, EX-OR, & EX-NOR Gates. Instrument comprises
More informationChapter 9 MSI Logic Circuits
Chapter 9 MSI Logic Circuits Chapter 9 Objectives Selected areas covered in this chapter: Analyzing/using decoders & encoders in circuits. Advantages and disadvantages of LEDs and LCDs. Observation/analysis
More informationHalf-Adders. Ch.5 Summary. Chapter 5. Thomas L. Floyd
Digital Fundamentals: A Systems Approach Functions of Combinational Logic Chapter 5 Half-Adders Basic rules of binary addition are performed by a half adder, which accepts two binary inputs (A and B) and
More informationLab #10 Hexadecimal-to-Seven-Segment Decoder, 4-bit Adder-Subtractor and Shift Register. Fall 2017
University of Texas at El Paso Electrical and Computer Engineering Department EE 2169 Laboratory for Digital Systems Design I Lab #10 Hexadecimal-to-Seven-Segment Decoder, 4-bit Adder-Subtractor and Shift
More informationDay care centres (ages 3 to 5) Kindergarten (ages 4 to 5) taken part in a fire drill in her building and started to beep.
You nd your fmily Here re eight key fire cn tke prt in sfety tips tht you should know Dy cre centres (ges 3 to 5) Kindergrten (ges 4 to 5) flsh Sty wy from hot things tht cn burn! Tell grown-up if you
More informationJawaharlal Nehru Engineering College
Jawaharlal Nehru Engineering College Laboratory Manual DIGITAL LOGIC DESIGN For Second Year Students Manual made by Dr. V. A. More Author JNEC, Aurangabad MGM S Jawaharlal Nehru Engineering College N-6,
More informationPHYS 3322 Modern Laboratory Methods I Digital Devices
PHYS 3322 Modern Laboratory Methods I Digital Devices Purpose This experiment will introduce you to the basic operating principles of digital electronic devices. Background These circuits are called digital
More informationSequential logic circuits
Computer Mathematics Week 10 Sequential logic circuits College of Information Science and Engineering Ritsumeikan University last week combinational digital circuits signals and busses logic gates and,
More information92.507/1. EYR 203, 207: novaflex universal controller. Sauter Systems
92.507/1 EYR 203, 207: novflex universl controller novflex, universl controller of the EY3600 fmily, is used in HVAC control systems. The EYR 203 hs totl of 18 inputs nd 10 outputs, while the EYR 207 hs
More informationGeneral: Catalog Description: Grading Policy: Course Code: COE 203 Title: Digital Logic Laboratory Co-requisite(s): COE 202 (Digital Logic Design)
King Fahd University of Petroleum & Minerals College of Computer Sciences and Engineering Department of Computer Engineering LAB Manual: COE 203: Digital Logic Laboratory (0-3-1) COE 203 Syllabus COE 203
More informationDALHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 220. Experiment 4 - Latches and Flip-Flops
DLHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 0 Experiment - Latches and Flip-Flops Objectives:. To implement an RS latch memory element. To implement a JK
More informationLCD Data Projector VPL-S500U/S500E/S500M
LCD Dt Projector VPL-S500U/S500E/S500M Sony presents to you... In tody s world it is esy to crete n impctful nd colorful presenttion full of chrts grphics video clips nd nimtions. To deliver these effective
More informationAIM: To study and verify the truth table of logic gates
EXPERIMENT: 1- LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various Logic gates and their output. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main
More informationTAP 413-1: Deflecting electron beams in a magnetic field
TAP 413-1: Deflecting electron bems in mgnetic field Circulr control Mgnetic fields re often used to steer bems of chrged prticles, in situtions from teleision tube to lrge-scle prticle ccelertor. The
More informationEEE130 Digital Electronics I Lecture #1_2. Dr. Shahrel A. Suandi
EEE130 Digital Electronics I Lecture #1_2 Dr. Shahrel A. Suandi 1-4 Overview of Basic Logic Functions Digital systems are generally built from combinations of NOT, AND and OR logic elements The combinations
More informationCSE 352 Laboratory Assignment 3
CSE 352 Laboratory Assignment 3 Introduction to Registers The objective of this lab is to introduce you to edge-trigged D-type flip-flops as well as linear feedback shift registers. Chapter 3 of the Harris&Harris
More informationLED BASED SNAKE GAME
LED BASED SNAKE GAME Group 14 1 NAME ROLL NO MAJOR Muhammad Shoaib Hassan 14100005 Electrical Engineering Syed Muhammad Ali 14100167 Electrical Engineering Muhammad Ali Gulzar 14100017 Computer Science
More informationTIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic
COURSE TITLE : DIGITAL INSTRUMENTS PRINCIPLE COURSE CODE : 3075 COURSE CATEGORY : B PERIODS/WEEK : 4 PERIODS/SEMESTER : 72 CREDITS : 4 TIME SCHEDULE MODULE TOPICS PERIODS 1 Number system & Boolean algebra
More informationNorth Shore Community College
North Shore Community College Course Number: IEL217 Section: MAL Course Name: Digital Electronics 1 Semester: Credit: 4 Hours: Three hours of Lecture, Two hours Laboratory per week Thursdays 8:00am (See
More informationR13 SET - 1 '' ''' '' ' '''' Code No: RT21053
SET - 1 1. a) What are the characteristics of 2 s complement numbers? b) State the purpose of reducing the switching functions to minimal form. c) Define half adder. d) What are the basic operations in
More informationVISUAL IDENTITY GUIDE
VISUAL IDENTITY GUIDE contents Bsic Section Visul Identity System Bsic Prt Appliction Section Visul Identity System Appliction Prt 1.1 Logo System Design 1.1.1 Stndrd Color Grphics of The Logo 1.1.2 Stndrd
More informationCPE 310L EMBEDDED SYSTEM DESIGN (CPE)
CPE 310L EMBEDDED SYSTEM DESIGN (CPE) LABORATORY 8 ANALOG DIGITAL CONVERTER DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOAL The goal of this lab is to understand
More informationDIGITAL CIRCUIT PROJECTS
DIGITAL CIRCUIT PROJECTS Understanding Digital Circuits through Implementation Second Edition ABSTRACT This text explains some of the most basic digital circuits by implementing them on a breadboard. The
More informationLABORATORY # 1 LAB MANUAL. Digital Signals
Department of Electrical Engineering University of California Riverside Laboratory #1 EE 120 A LABORATORY # 1 LAB MANUAL Digital Signals 2 Objectives Lab 1 contains 3 (three) parts and the objectives are
More informationCatch or Die! Julia A. and Andrew C. ECE 150 Cooper Union Spring 2010
Catch or Die! Julia A. and Andrew C. ECE 150 Cooper Union Spring 2010 Andrew C. and Julia A. DLD Final Project Spring 2010 Abstract For our final project, we created a game on a grid of 72 LED s (9 rows
More informationContents. English. English. Your remote control 2
English Contents Your remote control 2 Instlltion Preprtion 3 Connect your computer 4 Switch on 5 Select your enu lnguge 5 Serch for nd Store chnnels Automtic instlltion 7 nul instlltion 8 Reshuffle the
More informationExperiment # 4 Counters and Logic Analyzer
EE20L - Introduction to Digital Circuits Experiment # 4. Synopsis: Experiment # 4 Counters and Logic Analyzer In this lab we will build an up-counter and a down-counter using 74LS76A - Flip Flops. The
More informationAnswers to Exercise 3.3 (p. 76)
Answers to Exercise 3.3 (p. 76) First of ll, check to see tht you hve weighted your dtset with the vrible WTCORRCT (see Figure 2.5 on p. 52 for how to do this). Once this hs been done, you then need to
More informationEncoders and Decoders: Details and Design Issues
Encoders and Decoders: Details and Design Issues Edward L. Bosworth, Ph.D. TSYS School of Computer Science Columbus State University Columbus, GA 31907 bosworth_edward@colstate.edu Slide 1 of 25 slides
More informationIntroduction. APPLICATION NOTE 712 DS80C400 Ethernet Drivers. Jun 06, 2003
Mxim > Design Support > Technicl Documents > Appliction Notes > Microcontrollers > APP 712 Keywords: DS80C400, ethernet drivers, ethernet controller, TCP/IP router, source code, MII, MAC, PHY, ethernet
More informationDALHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 2200
DALHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 2200 Tutorial 1. Xilinx Integrated Software Environment (ISE) Tools Objectives: 1. Familiarize yourself with
More informationstyle type="text/css".wpb_animate_when_almost_visible { opacity: 1; }/style
style type="text/css".wpb_nimte_when_lmost_visible { opcity: 1; }/style Jul 11, 5 thousnd dollrs week life 2011 5 thousnd dollrs week life. 5 thousnd dollrs week life The $5000 A Week For Life Winner Selection
More informationChapter 2. Digital Circuits
Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217
More informationREPEAT EXAMINATIONS 2004 SOLUTIONS
REPET EXMINTIONS 24 SOLUTIONS MODULE: EE Digital Electronics COURSE:.Eng. in Electronic Engineering (year ).Eng. in Info and Communications Engineering (year ).Eng. in Mechatronic Engineering (year 2).Eng.
More information