Where Are We Now? e.g., ADD $S0 $S1 $S2?? Computed by digital circuit. CSCI 402: Computer Architectures. Some basics of Logic Design (Appendix B)

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1 Where Are We Now? Chapter 1: computer systems overview and computer performance Chapter 2: ISA (machine-spoken language), different formats, and various instructions Chapter 3: We will learn how those instructions can be supported by hardware. e.g., ADD $S0 $S1 $S2?? Computed by digital circuit 1 CSCI 402: Computer Architectures Some basics of Logic Design (Appendix B) Fengguang Song Department of Computer & Information Science IUPUI 1

2 Different Levels in Digital Design Subjects Building Blocks Theory Combinational Logic Design Sequential Logic Design Standard Modules Design System Design AND, OR, NOT, XOR AND, OR, NOT, FF Operators, Interconnects, Memory Data Paths, Control Paths Boolean Algebra Finite State Machine Arithmetics, Universal Logic Methodologies 4 Logic Gates Computers are digital computers: only have two voltage levels Consists of many digital circuits Rather than refer to High/Low voltage levels, we talk about signals that are logically 1 or 0 (asserted or de-asserted) Digital circuits are built from logic gates Gates are the simplest circuits Take as input multiple Boolean variables and produce one output. Gates are used to build more complex logic blocks 5 2

3 Classification of Logic Blocks Combinational logic blocks: Any number of inputs Its output depends only on current values of inputs E.g., a function with 4 inputs and 1 output y=(x 1 +x 2 *x 3 ))+((x 3 *x 4 )*x 1 ) Sequential logic blocks: Outputs depend on current values of inputs, plus some internal states. Any logic block can be realized only using AND, OR, NOT gates. nand and nor gates are universal. E.g., any logic system can be converted into nand 6 How to Combine Gates Together A combinatorial logic block can be constructed using a combination of Inverters (i.e., NOT), OR, and AND gates. Multiple gates may share the same input. Output of one gate may be input to another gate. e.g., Look at how to construct a circuit that produces output: xy +xy. Boolean algebra 7 3

4 More Examples: Combinations of Gates Examples: Construct circuits that produce these outputs (a) (x + y)x (b) x(y+z) (c) (x+y+z)(x y z) Boolean algebra 8 Basic Laws of Boolean Algebra 9 4

Truth Tables Boolean Algebra describes a logic function The other way to describe logic functions is to use Truth Table issue: the table sizes grow exponentially (2 n ) E.g., Consider a logic function with three inputs: A, B, and C, what is the truth table?

5 Truth Tables Boolean Algebra describes a logic function The other way to describe logic functions is to use Truth Table issue: the table sizes grow exponentially (2 n ) E.g., Consider a logic function with three inputs: A, B, and C, what is the truth table? Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true 10 Example Boolean algebra: D = A + B + C F = A*B*C E=(A*B*C) + (A*C*B) + (B*C*A) 11 5

In the following slides, we will look at 2 logic building blocks that we will use often (Ch3, ) Decoder x n-1 x 2 x 1 x 0 à a number e.g., 11101100 2 à output:?

.., Out 2 n -1 A full decoder works as follows: Only one output has value 1, while all other outputs have value 0.

6 In the following slides, we will look at 2 logic building blocks that we will use often (Ch3, ) Decoder x n-1 x 2 x 1 x 0 à a number e.g., à output:? Multiplexer (aka selector) 12 Decoders A full decoder has n input and 2 n outputs. Let inputs be labeled In 0, In 1, In 2,..., In n-1 Let outputs be labeled Out 0, Out 1,..., Out 2 n -1 A full decoder works as follows: Only one output has value 1, while all other outputs have value 0. The only output set to 1 is the one, whose label is equal to the binary value on input lines. That is, if input is k, then Out k will be = 1. A decoder with n inputs may have fewer than 2 n outputs. Sometime they are called partial decoders. 13 6

7 Example of a 3-Input Full Decoder the input signal is 3 bits wide 14 Multiplexers (or Selectors) A basic multiplexer has only one output line z. There are 2 types of input lines: data lines and select lines. There are N data lines, labeled d 0, d 1, d 2,... d N-1. There are m select lines, labeled s 0, s 1,..., s m-1 m is such that any data line d x can be referenced by a decimal value using m bits. Thus, N <= 2 m. A multiplexer works as follows: Output z has the value of the data line, whose label is equal to the value on select lines. 15 7

8 The Simplest Multiplexer The simplest multiplexer has 2 data lines and 1 select line C = (A*S) + (B*S) 16 An Array of Logic Elements Still 0 or 1 Computers often need to apply operations to an entire word (i.e. 32 bits) E.g., two buses, which one should be written into a register? 17 8

9 Programming Logic Array (PLA) A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic blocks. A sum-of-product can be implemented with a two-level logic 1 st level: all product 2 nd level: all sum abc + def + + xyz 23 Any logic function can be represented by a sum-of-product. Sum-of-Products Definition: Literal is a boolean variable or its complement. Minterm is a product y 1 y 2 y n, where y i = x i or y i = x i. The minterm y 1, y 2,, y n has value 1 if and only if each y i is 1. This occurs if and only if x i = 1 when y i = x i, and x i = 0 when y i = x i The sum of minterms is called the sum-ofproducts expansion (or disjunctive normal form). 24 9

How to Obtain Sum-of-Products uestion: Find the sum-of-products expansion for the function F(x,y,z) = (x + y) z Solution: we may use two methods, (1) using truth table, or (2) using Boolean Algebra.

10 How to Obtain Sum-of-Products uestion: Find the sum-of-products expansion for the function F(x,y,z) = (x + y) z Solution: we may use two methods, (1) using truth table, or (2) using Boolean Algebra. (M1) Form the sum of the minterms corresponding to each row of the table that has the value 1. Including a tem for each row of the table for which F(x,y,z) = 1 gives us F(x, y, z) = xyz + x y z + x y z 25 Sum-of-Products Expansion (Cont.) (M2) We can also use Boolean Algebra laws to find the sum-ofproducts form: F(x,y,z) = (x + y) z = x z + y z distributive law = x1 z + 1y z identity law = x(y + y ) z + (x +x )y z unit property = xy z + x y z + xy z + x y z distributive law = xyz +x y z + x y z idempotent law 26 10

11 Programming Logic Array (PLA) Minterm Minterm 27 Section B.7 Clock A clock is simply a running signal (has a fixed clock cycle time) Clock rate = 1 / Clock Cycle One clock cycle has two portions: when signal is high, and when signal is low Clocks are used in sequential logic blocks to decide when should a memory element (which contains state) be updated We will introduce edge-triggered clocking (see next slide) 28 11

12 Edge-Triggered Clocking Content of a state element only changes on active clock edge Either the rising edge or the falling edge will be the active edge (either one is OK) State element is a memory element (e.g., Register) Idea: Clock edge works like a sampling signal How: This signal will cause the input of a state element to be sampled or read; after sampling, the input is stored in the state element 29 Section B.8 Memory Elements Memory elements Memory elements can store state (or data) Its output depends both on the inputs and on the value stored inside All logic blocks that contain a memory element are sequential logic blocks Different types: Latches Flip-Flop 32 12

13 Latches and Flip-Flops Latches and flip-flops are simplest memory elements Both can store data Their output is equal to the stored state Both can be clocked Differences Latch is not always clocked Flip-flop is always clocked Flip-flop is often built from latch In a flip-flop, the state is changed only on clock edge 33 SR Latch SR latch is unclocked S-R latch (set-reset), built from 2 NOR gates SR Latch Symbol R S S=0, R=0 =>, = previous values (can ) S: 0->1 => = 1, = 0 R: 0->1 => = 0, =

14 SR Latch Analysis S = 1, R = 0: then = 1 and = 0 R 0 N1 SET S = 0, R = 1: then = 0 and = 1 S 1 N2 R 1 N1 RESET S 0 N2 S = 0, R = 0: then = prev SR Latch Analysis prev = 0 prev = 1 R 0 N1 0 R 0 N1 1 S 0 N2 S 0 N2 S = 1, R = 1: then = 0 and = 0 (Invalid) R 1 N1 S 1 N2 14

15 Clocked D-Latch D-latch is a clocked latch Two inputs: Data and Clock Output: and R S 1) When C is asserted, latch is open. <- D 2) When C is deasserted, latch is closed, is the old value How it works? open closed open closed D Flip-Flop D flip-flop uses a falling-edge triggered clock 1 st latch is Master, 2 nd latch is Slave When C is asserted, Master is open, Master outputs D When C falls, Master is closed, but Slave is open, ß D D 38 15

16 Result: D Flip-Flop can store 1 bit, driven by a falling clock edge Clocked D Flip-Flop Clocked D-Latch R Unclocked SR Latch S 39 Register Files We can use 32 D flip-flops to build a register (to store a 32-bit word) Register File is a set of registers Can be read/written given a register number To read One input: Register# To write Three inputs: Register#, data, clock 16

17 Design of 32-bit Register D flip-flop as a building block Thus, 32-bit register has: 33 inputs and 32 outputs There are two operations on a register: read and Write Read operation: register content is always available on Dout0-Dout31 Write operation: provide desired values on Din0- Din31 generate falling edge on the write line Recall critical period T cr around Essentially made from a number of NOR gates. falling edge. 5- Basics of Digital Logic Design -48 CSC3501 S07 41 Register File with 2 Read Ports 5 bits Read port is implemented with a Multiplexor 42 17

COMP2611: Computer Organization. Introduction to Digital Logic

1 COMP2611: Computer Organization Sequential Logic Time 2 Till now, we have essentially ignored the issue of time. We assume digital circuits: Perform their computations instantaneously Stateless: once