Outline Synchronous Systems Introduction Field Programmable Gate Arrays (FPGAs) Introduction Review of combinational logic

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1 EECS150 - igital esign Lecture 2 - Synchronous igital Systems and FPGAs January 24, 2013 John Wawrzynek Electrical Engineering and Computer Sciences University of California, Berkeley Spring 2013 EECS150 lec02-ss-fpgas Page 1 Outline Synchronous Systems Introduction Field Programmable Gate Arrays (FPGAs) Introduction Review of combinational logic Spring 2013 EECS150 - Lec02-SS-FPGAs Page 2

Integrated Circuit Example PowerPC microprocessor microphotograph Superscalar (3 instructions/cycle) execution units (2 integer and 1 double precision IEEE floating point) 32 KByte Instruction and

motherboard) Memory interface Power (Vdd, GN) Clock input Spring 2012 EECS150 lec01-intro Page 3 Clock Signal Τ represents the time of one clock cycle.

2 Integrated Circuit Example PowerPC microprocessor microphotograph Superscalar (3 instructions/cycle) execution units (2 integer and 1 double precision IEEE floating point) 32 KByte Instruction and ata L1 caches ual Memory Management Units (MMU) External L2 Cache interface with integrated controller and cache tags. Comprises only transistors and wires. Connections to outside world (ex. motherboard) Memory interface Power (Vdd, GN) Clock input Spring 2012 EECS150 lec01-intro Page 3 Clock Signal Τ represents the time of one clock cycle. A source of regularly occurring pulses used to measure the passage of time. Waveform diagram shows evolution of signal value (in voltage) over time. Usually comes from an off-chip crystal-controlled oscillator. One main clock per chip/system. istributed throughout the chip/system. Heartbeat of the system. Controls the rate of computation by directly controlling all data transfers. Spring 2012 EECS150 lec01-intro Page 4

3 ata Signals Random adder circuit at a random point in time: The facts: 1. Low-voltage represents binary 0 and high-voltage, binary Circuits are designed and built to be restoring and deviations from ideal voltages are ignored. Outputs close to ideal. 3. In synchronous systems, all changes follow clock edges. Observations: 1. Most of the time, signals are in either low- or high-voltage position. 2. When the signals are at the highor low-voltage positions, they are not all the way to the voltage extremes (or they are past). 3. Changes in the signals correspond to changes in clock signal (but don t change every cycle). Spring 2012 EECS150 lec01-intro Page 5 Bus Signals Signal wires grouped together often called a bus. X 0 is called the least significant bit (LSB) X 3 is called the most significant bit (MSB) Capital X represents the entire bus. Here, hexadecimal digits are used to represent the values of all four wires. The waveform for the bus depicts it as being simultaneiously high and low. (The hex digits give the bit values). The waveform just shows the timing. Spring 2012 EECS150 lec01-intro Page

4 Circuit elay igital circuits cannot produce outputs instantaneously. In general, the delay through a circuit is called the propagation delay. It measures the time from when inputs arrive until the outputs change. The delay amount is a function of many things. Some out of the control of the circuit designer: Processing technology, the particular input values. And others under her control: Circuit structure, physical layout parameters. Spring 2012 EECS150 lec01-intro Page 7 Combinational Logic Blocks Example four-input function: True-table representation of function. Output is explicitly specified for each input combination. In general, CL blocks have more than one output signal, in which case, the truth-table will have multiple output columns. a b c d y F(0,0,0,0) F(0,0,0,1) F(0,0,1,0) F(0,0,1,1) F(0,1,0,0) F(0,1,0,1) F(0,1,1,0) F(0,1,1,1) F(1,0,0,0) F(1,0,0,1) F(1,0,1,0) F(1,0,1,1) F(1,1,0,0) F(1,1,0,1) F(1,1,1,0) F(1,1,1,1) Spring 2012 EECS150 lec01-intro Page 8

5 2-bit adder. Takes two 2-bit integers and produces 3-bit result. Think about true table for 32-bit adder. It s possible to write out, but it might take a while! Example CL Block a1 a0 b1 b0 c2 c1 c Theorem: Any combinational logic function can be implemented as a networks of logic gates. Spring 2012 EECS150 lec01-intro Page 9 Logic Gates AN ab c ab c OR NOT a b NAN ab c NOR ab c XOR ab c Logic gates are often the primitive elements out of which combinational logic circuits are constructed. In some technologies, there is a one-to-one correspondence between logic gate representations and actual circuits. Other times, we use them just as another abstraction layer (FPGAs have no real logic gates). How about these gates with more than 2 inputs? o we need all these types? Spring 2012 EECS150 lec01-intro Page 10

Example Logic Circuit a b c y 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1

circuits have been built out of many different technologies.

6 Example Logic Circuit a b c y How do we know that these two representations are equivalent? Spring 2012 EECS150 lec01-intro Page 11 Logic Gate Implementation Logic circuits have been built out of many different technologies. If we have a basic logic gate (AN or OR) and inversion we can build a complete logic family. TL CMOS Gate Hydraulic Mechanical LEGO logic gates. A clockwise rotation represents a binary one while a counterclockwise rotation represents a binary zero. Spring 2012 EECS150 lec01-intro Page 12

7 Restoration A necessary property of any suitable technology for logic circuits is "Restoration". Circuits need: to ignore noise and other non-idealities at the their inputs, and generate "cleaned-up" signals at their output. Otherwise, each stage would propagates input noise to their output and eventually noise and other non-idealities would accumulate and signal content would be lost. Spring 2012 EECS150 lec01-intro Page 13 Inverter Example of Restoration Example (look at 1-input gate, to keep it simple): Idealize Inverter Actual Inverter VIN VOUT Inverter acts like a non-linear amplifier The non-linearity is critical to restoration Other logic gates act similarly with respect to input/output relationship. Spring 2012 EECS150 lec01-intro Page 14

Project platform: Xilinx ML505-110 Spring 2013 EECS150 - Lec02-SS-FPGAs Page 15 FPGA: Xilinx Virtex-5

8 Project platform: Xilinx ML Spring 2013 EECS150 - Lec02-SS-FPGAs Page 15 FPGA: Xilinx Virtex-5 XC5VLX110T Virtex-5 die photo Spring 2013 EECS150 - Lec02-SS-FPGAs Page 1 A die is an unpackaged part Serial ()

Ball Grid Array (BGA) Flip-Chip Package From die to PC board.

Solder Bump Silicon ie Solder Ball Organic Build-Up Substrate Spring 2013 EECS150 -

blocks and flip-flops with a means for the user to configure (program): 1.

9 Ball Grid Array (BGA) Flip-Chip Package From die to PC board... Copper Heatspreader Thermal Interface Material Underfill Epoxy Adhesive Epoxy* Flip Chip Solder Bump Silicon ie Solder Ball Organic Build-Up Substrate Spring 2013 EECS150 - Lec02-SS-FPGAs Page 17 Serial () FPGA Overview Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure (program): 1. the interconnection between the logic blocks, 2. the function of each block. Simplified version of FPGA internal architecture: Spring 2013 EECS150 - Lec02-SS-FPGAs Page 18

10 Why are FPGAs Interesting? Technical viewpoint: For hardware/system-designers, like ASICs only better! Tape-out new design every few minutes/hours. oes the reconfigurability or reprogrammability offer other advantages over fixed logic? ynamic reconfiguration? In-field reprogramming? Self-modifying hardware, evolvable hardware? Spring 2013 EECS150 lec02-ss-fpgas Page 19 Why are FPGAs Interesting? Staggering logic capacity growth (10000x): Year Introduced evice Logic Cells logic gate equivalents 1985 XC XC7V2000T 1,954,50 15,3,480 FPGAs have tracked Moore s Law better than any other programmable device. Spring 2013 EECS150 lec02-ss-fpgas Page 20

Why are FPGAs Interesting? Logic capacity now only part of the story: on-chip RAM, high-speed I/Os, hard function blocks,.

Mapping is more difficult. Introduces uncertainty in efficiency of solution.

implemented in FPGA than in custom chips.

Gear in river Assistance with FPGA Platforms Hardware Trumps Software in Medical evice esign Taming Power raw in Consumer MPUs Plugging into High-Volume Consumer

11 Why are FPGAs Interesting? Logic capacity now only part of the story: on-chip RAM, high-speed I/Os, hard function blocks,... Modern FPGAs are reconfigurable systems Xilinx Virtex-5 LX110T 10GBps Serdes Ethernet MACs PCI express Phy But, the heterogeneity erodes the purity argument. Mapping is more difficult. Introduces uncertainty in efficiency of solution Kb SRAM Blocks Spring 2013 EECS150 lec02-ss-fpgas Page 21 FPGAs are in widespread use FPGAs Power Net-Centric Battlefield on Many Fronts Far more designs are implemented in FPGA than in custom chips. INSIE Make MicroBlaze Processing Roar With Hardware Acceleration FPGAs Help CERN Track Particles Approaching Speed of Light Xcell Automotive Innovators Hit Hit High Top Gear in river Assistance with FPGA Platforms Hardware Trumps Software in Medical evice esign Taming Power raw in Consumer MPUs Plugging into High-Volume Consumer Products INSIE Algorithm evelopers Power New A System on Xilinx Automotive FPGA Platform Engineer Turns Blown HIGH VOLUME Engine into Hot Startup Spartan-3E: A New Era How to Beat Your Son Multimedia for Automotive at Guitar Hero Using Xilinx FPGA SP Algorithms Tips and Tricks for ESIGN TOOLS Using FPGA Editor New ISE 7.1i Software and SystemVerilog Control Your esigns SERIAL I/O Spring 2012 CS Lec02-logic-FPGA Page 22 Extend Your Reach SUBS

12 User Programmability Latch-based (Xilinx, Altera, ) + reconfigurable volatile relatively large. Latches are used to: 1. control a switch to make or break cross-point connections in the interconnect 2. define the function of the logic blocks 3. set user options: within the logic blocks in the input/output blocks global reset/clock Configuration bit stream is loaded under user control Spring 2012 CS Lec02-logic-FPGA Page 23 Background (review) for upcoming A MUX or multiplexor is a combinational logic circuit that chooses between 2 N inputs under the control of N control signals. A latch is a 1-bit memory (similar to a flip-flop). Spring 2013 EECS150 - Lec02-SS-FPGAs Page 24

13 Idealized FPGA Logic Block 4-input look up table () implements combinational logic functions Register optionally stores output of Spring 2012 CS Lec02-logic-FPGA Page Implementation n-bit is implemented as a 2 n x 1 memory: inputs choose one of 2 n memory locations. memory locations (latches) are normally loaded with values from user s configuration bit stream. Inputs to mux control are the CLB inputs. Result is a general purpose logic gate. n- can implement any function of n inputs! Spring 2012 CS Lec02-logic-FPGA Page 2

as general logic gate An n-lut as a direct implementation of a function truth-table. Each latch location holds the value of the function corresponding to one input combination.

14 as general logic gate An n-lut as a direct implementation of a function truth-table. Each latch location holds the value of the function corresponding to one input combination. Example: 4-lut Example: 2-lut Implements any function of 2 inputs. How many of these are there? How many functions of n inputs? Spring 2012 CS Lec02-logic-FPGA Page 27 FPGA Generic esign Flow esign Entry: Create your design files using: schematic editor or HL (hardware description languages: Verilog, VHL) esign Implementation: Logic synthesis (in case of using HL entry) followed by, Partition, place, and route to create configuration bit-stream file esign verification: Optionally use simulator to check function, Load design onto FPGA device (cable connects PC to development board), optional logic scope on FPGA check operation at full speed in real environment. Spring 2012 CS Lec02-logic-FPGA Page 28

15 Example Partition, Placement, and Route Idealized FPGA structure: Example Circuit: collection of gates and flip-flops Circuit combinational logic must be covered by 4-input 1-output s. Flip-flops from circuit must map to FPGA flip-flops. (Best to preserve closeness to CL to minimize wiring.) Best placement in general attempts to minimize wiring. Vdd, GN, clock, and global resets are all prewired. Spring 2012 CS Lec02-logic-FPGA Page 29 Example Partition, Placement, and Route OUT IN Example Circuit: collection of gates and flip-flops A A B B Two partitions. Each has single output, no more than 4 inputs, and no more than 1 flip-flop. In this case, inverter goes in both partitions. Note: the partition can be arbitrarily large as long as it has not more than 4 inputs and 1 output, and no more than 1 flip-flop. Spring 2012 CS Lec02-logic-FPGA Page 30

16 Xilinx FPGAs (interconnect detail) Spring 2012 CS Lec02-logic-FPGA Page 31 Colors represent different types of resources: Logic Block RAM SP (ALUs) Clocking I/O Serial I/O + PCI A routing fabric runs throughout the chip to wire everything together. Spring 2013 EECS150 - Lec02-SS-FPGAs Page 32 Serial ()

17 Configurable Logic Blocks (CLBs) Slices define regular connections to the switching fabric, and to slices in CLBs above and below it on the die. CLB COUT COUT Slice(1) Switch Matrix Slice(0) CIN CIN UG190_5_01_12205 The LX110T has 17,280 slices. Spring 2013 EECS150 - Lec02-SS-FPGAs Page 33 X-Y naming convention for slices X0, X2,... are lower CLB slices. X1, X3,... are upper CLB slices. Y0, Y1,... are CLB column positions. COUT COUT COUT COUT CLB Slice X1Y1 CLB Slice X3Y1 Slice X0Y1 Slice X2Y1 CIN CIN CIN CIN CLB COUT Slice X1Y0 COUT CLB COUT Slice X3Y0 COUT Slice X0Y0 Slice X2Y0 Lower-left corner of the die. UG190_5_02_12205 Spring 2013 EECS150 - Lec02-SS-FPGAs Page 34

18 Atoms: 5-input Look Up Tables (s) A2 A3 A4 A5 A 5 A[:2] (1) (0) (1). (0). A[:2] Computes any 5- input logic function. Timing is independent of function (0) (1) Latches set during configuration. 35 Spring 2013 EECS150 - Lec02-SS-FPGAs Page A1 A2 A3 A4 A5 A Virtex-5 -s: Composition of 5-s May be used A2 A3 A4 A5 A A2 A3 A4 A5 A as one -input ( out) or as two 5-input S ( and 5) Figure 3: Block iagram of a Virtex-5 -Input WP245_03_05100 The LX110T has 9,120 -s - delay is 0.9 ns Combinational logic (post configuration) Spring 2013 EECS150 - Lec02-SS-FPGAs Page 3

19 ([:1]) (C[:1]) (B[:1]) A[:1] A[:1] A[:1] The simplest view of a slice SLICE (Optional) (Optional) () () (C) (C) (B) (B) Four -s Four Flip-Flops Switching fabric may see combinational and registered outputs. (A[:1]) (CLK) A[:1] (Optional) (Optional) (A) (A) An actual Virtex-5 slice adds many small features to this simplified diagram. We show them one by one... Spring 2013 EECS150 - Lec02-SS-FPGAs Page 37 SLICE Two 7-s per slice... ([:1]) A[:1] F7BMUX (C[:1]) (CX) A[:1] (CMUX) (C) (Optional) Extra multiplexers(f7amux, F7BMUX) (CLK) (B[:1]) A[:1] F7AMUX Extra inputs (AX and CX) (AMUX) (A[:1]) A[:1] (A) (Optional) (AX) Spring 2013 EECS150 - Lec02-SS-FPGAs Page 38

20 Or one 8-s per slice... SLICE ([:1]) A[:1] F7BMUX (C[:1]) A[:1] F8MUX Third multiplexer(f8mux) (CX) (BMUX) (B[:1]) A[:1] F7AMUX (Optional) (B) Third input (BX) (A[:1]) (AX) (BX) (CLK) A[:1] Configuring the n of an n-... Spring 2013 EECS150 - Lec02-SS-FPGAs UG Page 39 Extra muxes to chose option... Inputs X O5 FE/LAT CE MUX From eight 5-s... to one 8-. CLK SR REV C Inputs CX O5 F7BMUX F8MUX FE/LAT CE C CMUX C Combinational or registered outs. CLK B Inputs BX O5 SR REV FE/LAT CE CLK SR REV B BMUX B Flip-flops unused by s can be used standalone. A Inputs AX CE CLK SR REV (X) F7AMUX A AMUX O5 FE/LAT A CE CLK SR REV Spring 2013 EECS150 - Lec02-SS-FPGAs Page 40 UG190_5_25_05050

21 From O5 From X S3 COUT (To Next Slice) I3 MUXCY Virtex 5 Vertical Logic Carry Chain Block (CARRY4) CO3 O3 MUX/* MUX We can map ripple-carry addition onto carry-chain block. (Optional) From C S2 MUXCY CO2 CMUX/C* O5 From C CX I2 O2 CMUX C (Optional) From B S1 MUXCY CO1 BMUX/B* O5 From B BX I1 O1 BMUX B From A O5 From A AX S0 I0 CYINIT 0 1 MUXCY CIN CO0 O0 (Optional) AMUX/A* AMUX A (Optional) * Can be used if unregistered/registered outputs are free. Spring 2013 CIN (From Previous Slice) EECS150 - Lec02-SS-FPGAs Page 41 UG190_5_24_05050 The carry-chain block also useful for speeding up other adder structures and counters. Putting it all together... a SLICEL X A A5 A4 A3 A2 A1 ROM O5 COUT X CE CK Reset Type Sync Async FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV MUX The previous slides explain all SLICEL features. CMUX C C5 C4 C3 C2 C1 CX B B5 B4 B3 B2 B1 BX A A5 A4 A3 A2 A1 AX SR CE CLK A A5 A4 A3 A2 A1 A A5 A4 A3 A2 A1 A A5 A4 A3 A2 A1 ROM ROM ROM O5 O5 O5 0/1 C CX B BX A AX CE CK CE CK CE CK Spring 2013 EECS150 - Lec02-SS-FPGAs Page FF LATCH INIT1 INIT0 SRHIGH SRLOW SR FF LATCH INIT1 INIT0 SRHIGH SRLOW SR FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV REV REV C C BMUX B B AMUX A A About 50% of the 17,280 slices in an LX110T are SLICELs. The other slices are SLICEMs, and have extra features. 42 CIN UG190_5_04_0320

22 A2 A3 A4 A5 A 5 A[:2] Recall: 5- architecture... (1) (0) (1). (0) (0) (1). A[:2] 32 Latches. Configured to 1 or 0. Some parts of a logic design need many state elements. SLICEMs replace normal 5-s with circuits that can act like 5-s, but can alternatively use the 32 latches as RAM, ROM, shift registers. Spring 2013 EECS150 - Lec02-SS-FPGAs Page 43 Virtex-5 SP48E Slice Efficient implementation of multiply, add, bit-wise logical. LX110T has 4 in a single column. Spring 2013 EECS150 - Lec02-SS-FPGAs Page 44

23 Spring 2013 EECS150 - Lec02-SS-FPGAs Page 45 To be continued... Throughout the semester, we will look at different Virtex-5 features in-depth. Switch fabric Block RAM SP48 (ALUs) Clocking I/O Serial I/O + PCI Spring 2013 EECS150 - Lec02-SS-FPGAs Page 4 Serial ()

Why FPGAs? FPGA Overview. Why FPGAs?

Why FPGAs? FPGA Overview. Why FPGAs? Transistor-level Logic Circuits Positive Level-sensitive EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) January 28, 2003 John Wawrzynek Transistor Level clk clk clk Positive