PROGRAMMABLE ASIC LOGIC CELLS

Transcription

1 ASICs...THE COURSE ( WEEK) PROGRAABLE ASIC LOGIC CELLS 5 Key concepts: basic logic cell multiplexer-based cell look-up table (LUT) programmable array logic (PAL) influence of programming technology timing worst-case design 5. Actel ACT 5.. ACT Logic odule Logic odule Logic odule Logic odule Actel ACT (a) A A SA B B SB S S S 2 S 2 S S3 O 3 A A SA B B SB S S O 2 S3 '' C '' A '' B 2 =(A B) +(B' C)+ (b) (c) (d) The Actel ACT architecture (a) Organization of the basic logic cells (b) The ACT Logic odule (L, the Actel basic logic cell). The ACT family uses just one type of L. ACT 2 and ACT 3 PGA families both use two different types of L (c) An example L implementation using pass transistors (without any buffering) (d) An example logic macro. Connect logic signals to some or all of the L inputs, the remaining inputs to V or GN

2 2 SECTION 5 PROGRAABLE ASIC LOGIC CELLS ASICS... THE COURSE 5..2 Shannon s Expansion Theorem We can use the Shannon expansion theorem to expand =A (A='') + A' (A='') Example: =A' B + A B C' + A' B' C = A (B C') + A' (B + B' C) (A='')=B C' is the cofactor of with respect to (wrt) A or A If we expand wrt B, =A' B + A B C' + A' B' C = B (A' + A C') + B' (A' C) Eventually we reach the unique canonical form, which uses only minterms (A minterm is a product term that contains all the variables of such as A B' C) Another example: =(A B) + (B' C) + Expand wrt B: =B (A + ) + B' (C + ) =B 2 + B' = 2: UX, with B selecting between two inputs: (A='') and (A='') also describes the output of the ACT L Now we need to split up and 2 Expand 2 wrt A, and wrt C: 2=A + =(A ) + (A' ); =C + =(C ) + (C' ) A, B, C connect to the select lines and '' and are the inputs of the UXes in the ACT L Connections: A=, A='', B=, B='', SA=C, SB=A, S='', and S=B

3 ASICs... THE COURSE 5. Actel ACT ultiplexer Logic as unction Generators The 6 logic functions of 2 variables: 2 of the 6 functions are not very interesting (='', and ='') There are functions that we can implement using just one 2: UX 6 functions are useful: INV, BU, AN, OR, AN-, NOR- A B 4 ways to arrange one '' A B 6 ways to arrange two ''s A B 4 functions of 2 variables (and ='', ='' makes 6) 4 ways to arrange one '' Boolean functions using a 2: UX unction, = Canonical form interms interm code unction number A A SA '' '' '' none 2 NOR-(A, B) (A+B') A' B 2 B A 3 NOT(A) A' A' B' + A' B, 3 A 4 AN-(A, B) A B' A B' 2 4 A B 5 NOT(B) B' A' B' + A B', 2 5 B 6 BU(B) B A' B + A B, 3 6 B 7 AN(A, B) A B A B 3 8 B A 8 BU(A) A A B' + A B 2, 3 9 A 9 OR(A, B) A+B A' B + A B' + A B, 2, 3 3 B A '' '' A' B' + A' B + A B' + A B,, 2, 3 5 Example of using the WHEEL functions to implement =NAN(A, B)=(A B)'. irst express as the output of a 2: UX: we do this by expanding wrt A (or wrt B; since is symmetric) =A (B') + A' ('') 2. Assign WHEEL to implement INV(B), and WHEEL2 to implement '' 3. Set the select input to the UX connecting WHEEL and WHEEL2, S+S=A. We can do this using S=A, S=''

4 4 SECTION 5 PROGRAABLE ASIC LOGIC CELLS ASICS... THE COURSE A A SA AN- NOR- BU OR AN INV AN- NOR- 2 3 WHEEL WHEEL2 A two-input UX S S can implement S S these functions, selected by A, A, and SA. WHEEL The ACT Logic odule can implement these functions. S3 A, B C, 2 3 S3 (a) (b) The ACT Logic odule as a Boolean function generator (a) A 2: UX viewed as a function wheel (b) The ACT Logic odule is two function wheels, an OR gate, and a 2: UX A 2: UX is a function wheel that can generate BU, INV, AN-, AN-, OR, AN WHEEL(A, B) =UX(A, A, SA) UX(A, A, SA)=A SA' + A SA The inputs (A, A, SA) ={A, B, '', ''} Each of the inputs (A, A, and SA) may be A, B, '', or '' The ACT L is built from two function wheels, a 2: UX, and a two-input OR gate ACT L =UX [WHEEL, WHEEL2, OR(S, S)] 5..4 ACT 2 and ACT 3 Logic odules ACT requires 2 Ls per flip-flop: with unknown interconnect capacitance ACT 2 and ACT 3 use two types of Ls, one includes a flip-flop ACT 2 C-odule is similar to the ACT L but can implement five-input logic functions combinatorial module implements combinational logic (blame I for the misuse of terms) ACT 2 S-odule (sequential module) contains a C-odule and a sequential element

5 ASICs... THE COURSE 5. Actel ACT Timing odel and Critical Path Keywords and concepts: timing model deals only with internal logic estimates delays before place-and-route step nondeterministic architecture find slowest register register delay or critical path Example of timing calculations (a rather complex examination of internal module timing): The setup and hold times, measured inside (not outside) the S-odule, are t' SU and t' H (a prime denotes parameters that are measured inside the S-odule) The clock Q propagation delay is t' CO The parameters t' SU, t' H, and t' CO are measured using the internal clock signal CLKi The propagation delay of the combinational logic inside the S-odule is t' P The delay of the combinational logic that drives the flip-flop clock signal is t' CLK rom outside the S-odule, with reference to the outside clock signal CLK: t SU =t' SU + (t' P t' CLK ), t H =t' H + (t' P t' CLK ), t CO =t' CO + t' CLK We do not know the internal parameters t' SU, t' H, and t' CO, but assume reasonable values: t' SU =.4ns, t' H =.ns, t' CO =.4ns. t' P (combinational logic inside the S-odule) is equal to the C-odule delay, so t' P =3ns for the ACT 3 We do not know t' CLK ; assume a value of t' CLK =2.6ns (the exact value does not matter) Thus the external S-odule parameters are: t SU =.8ns, t H =.5ns, t CO =3.ns These are the same as the ACT 3 S-odule parameters (I chose t' CLK so they would be) Of the 3.ns combinational logic delay:.4ns increases the setup time and 2.6ns increases the clock output delay, t CO Actel says that the combinational logic delay is buried in the flip-flop setup time. But this is borrowed money you have to pay it back Speed Grading Speed grading (or speed binning) uses a binning circuit easure t P =(t PLH + t PHL )/2 and use the fact that properties match across a chip Actel speed grades are based on 'Std' speed grade

6 6 SECTION 5 PROGRAABLE ASIC LOGIC CELLS ASICS... THE COURSE C-odule S-odule (ACT 2) S-odule (ACT 3) A B S Y OUT SE Y Q A B S SE Y Q A B S A B S A CLR CLK S A B CLR CLK S (a) (b) (c) SE (sequential element) SE C2 C Z S master latch Z S slave latch Q CLK CLR C2 C CLR Q Q CLR combinational logic for clock and clear flip-flop macro Q CLK C (d) (e) Actel ACT 2 and ACT 3 Logic odules (a) The C-odule for combinational logic (b) The ACT 2 S-odule (c) The ACT 3 S-odule (d) The equivalent circuit (without buffering) of the SE (sequential element) (e) The SE configured as a positive-edge triggered flip-flop '' speed grade is approximately 5 percent faster than 'Std' '2' speed grade is approximately 25 percent faster than 'Std' '3' speed grade is approximately 35 percent faster than 'Std'.

7 ASICs... THE COURSE 5. Actel ACT 7 (a) t P t SU t CO combinational logic delay setup time 3.ns.8ns 3.ns clock to output delay t SU setup time.8ns t CO clock to output delay 3.ns (t H ) internal signal C-odule (hold time) (.5ns) S-odule S-odule internal signal I CL CL Q Q O clock pad C clock buffer S CLK CLK2 S2 CLK internal clock = variable routing delay S t' P CL S-odule t' SU t' CO (t' H ) i CLKi Qi Q timing parameters typical figures S 3ns CL S-odule.4 ns.4ns (. ns) i CLKi Qi Q t' CLK View CLK from inside looking out. View from outside looking in. (b) t SU t CO (t H ) CLK Q t SU = t' SU + t' P t' CLK t H = t' H + t' P t' CLK t CO = t' CO + t' CLK Q CLK 2.6ns (c).8ns 3. ns (.5ns) CLK Q Q t SU = ( ) =.8ns t H = ( ˇ) =.5ns t CO = ( ) = 3.ns Timing views from inside and outside the Actel ACT S-module (a) Timing parameters for a 'Std' speed grade ACT 3 (b) lip-flop timing (c) An example of flip-flop timing based on ACT 3 parameters

8 8 SECTION 5 PROGRAABLE ASIC LOGIC CELLS ASICS... THE COURSE 5..7 Worst-Case Timing Keywords and concepts: Using synchronous design you worry about how slow your circuit may be not how fast ambient temperature, T A package case temperature, T C (military) temperature of the chip, the junction temperature, T J nominal operating conditions: V =5.V, and T J =25 C worst-case commercial conditions: V =4.75V, and T J =+7 C always design using worst-case timing derating factors critical path delay between registers process corner (slow slow fast fast slow fast fast slow) Commercial. V =5V ± 5%, T A (ambient)= to +7 C Industrial. V =5V ± %, T A (ambient)= 4 to +85 C ilitary: V =5V ± %, T C (case)= 55 to +25 C ilitary: Standard IL-ST- 883C Class B ilitary extended: unmanned spacecraft ACT 3 timing parameters anout amily elay ACT 3-3 (data book) t P ACT3-2 (calculated) t P / ACT3- (calculated) t P / ACT3-Std (calculated) t P / ACT 3 derating factors Temperature T J (junction)/ C V /V Actel Logic odule Analysis Actel uses a fine-grain architecture which allows you to use almost all of the PGA Synthesis can map logic efficiently to a fine-grain architecture

9 ASICs... THE COURSE 5.2 Xilinx LCA 9 Physical symmetry simplifies place-and-route (swapping equivalent pins on opposite sides of the L to ease routing) atched to small antifuse programming technology Ls balance efficiency of implementation and efficiency of utilization A simple L reduces performance, but allows fast and robust place-and-route 5.2 Xilinx LCA Keywords and concepts: Xilinx LCA (a trademark, logic cell array) configurable logic block coarse-grain architecture 5.2. XC3 CLB A 32-bit look-up table (LUT) CLB propagation delay is fixed (the LUT access time) and independent of the logic function 7 inputs to the XC3 CLB: 5 CLB inputs (A E), and 2 flip-flop outputs (QX and QY) 2 outputs from the LUT ( and G). Since a 32-bit LUT requires only five variables to form a unique address (32=2 5 ), there are several ways to use the LUT: Use 5 of the 7 possible inputs (A E, QX, QY) with the entire 32-bit LUT (the CLB outputs ( and G) are then identical) Split the 32-bit LUT in half to implement 2 functions of 4 variables each; choose 4 input variables from the 7 inputs (A E, QX, QY).You have to choose 2 of the inputs from the 5 CLB inputs (A E); then one function output connects to and the other output connects to G. You can split the 32-bit LUT in half, using one of the 7 input variables as a select input to a 2: UX that switches between and G (to implemen some functions of 6 and 7 variables) XC4 Logic Block

10 SECTION 5 PROGRAABLE ASIC LOGIC CELLS ASICS... THE COURSE I data in QX flip-flop Q A C E B QY combinational function CL G QX R G QY flip-flop X CLB outputs Y Q EC enable clock '' (enable) R K R clock reset direct '' (inhibit) (global reset) programmable UX The Xilinx XC3 CLB (configurable logic block) (Source: Xilinx.)

11 ASICs... THE COURSE 5.2 Xilinx LCA G:G4 :4 to/from adjacent CLB in 4 4 C L CL out logic 4 LUT 4 LUT H IN EC S/R LUT C C2 C3 C4 IN ' G' H' G' H' ' four control lines per CLB for internal control or SRA control clock enable programmable UX SET/RST control S QY EC R flip-flop Y CLB outputs X K in logic out to/from adjacent CLB global clock IN ' G' H' = programmable UX SET/RST control EC S QX flip-flop R The Xilinx XC4 family CLB (configurable logic block). (Source: Xilinx.)

12 2 SECTION 5 PROGRAABLE ASIC LOGIC CELLS ASICS... THE COURSE XC52 Logic Block I 4: 4 LC to LC and LC2 to LC3 only 5_UX data in LUT combinational function = programmable UX CO CI out S in Logic Cell (LC) 3 chain 3 flip-flop or latch Q CE CLK CLR CE, CK, CLR O Q X LC3 LC2 LC LC CLB (4 LCs in a CLB) CE, CK, CLR The Xilinx XC52 family Logic Cell (LC) and configurable logic block (CLB).(Source: Xilinx.) Xilinx CLB Analysis The use of a LUT has advantages and disadvantages: An inverter is as slow as a five-input NAN A LUT simplifies timing of synchronous logic atched to large SRA programming technology Xilinx uses two speed-grade systems: aximum guaranteed toggle rate of a CLB flip-flop (in Hz) as a suffix higher is faster Example: Xilinx XC32-25 has a toggle frequency of 25Hz elay time of the combinational logic in a CLB in ns lower is faster Example: XC4-6 has t ILO =6.ns Correspondence between grade and t ILO is fairly accurate for the XC2, XC4, and XC52 but not for the XC3

13 ASICs... THE COURSE 5.2 Xilinx LCA 3 t ICK t CKO t ILO t ICK t CKO setup time clock to output delay combinational logic delay setup time.8 ns 5.6ns 2.3ns 5.8ns 5.8ns clock to output delay Xilinx LCA timing model (XC52-6) (Source: Xilinx.) internal signal I CLB CLB2 CLB3 Q CL CL Q O CLKC I2 CLKC3 IK internal clock = variable routing delay

14 4 SECTION 5 PROGRAABLE ASIC LOGIC CELLS ASICS... THE COURSE 5.3 Altera LEX (a) Altera LEX Logic Array Block (LAB) local interconnect 4 4: 4 4: 3 LC2:LC Logic Element (LE) LUT CL chain PRE, CLR CRYO CL out CASCO CL cascade out cascade chain LE3 LE2 OUT PRE Q CLK flip-flop CLR (b) LE2 8 LEs per LAB LC4:LC3 LC4:LC CLK in CRYI CASCI cascade in = programmable UX LE LE (c) The Altera LEX architecture (a) Chip floorplan (b) Logic Array Block (LAB) (c) etails of the Logic Element (LE) (Source: Altera (adapted with permission).)

15 ASICs... THE COURSE 5.4 Altera AX Altera AX programmable AN array (2i jk) k macrocells product term j-wide OR array j Q OUT j CLK macrocell A B C i i inputs A registered PAL with i inputs, j product terms, and k macrocells. (Source: Altera (adapted with permission).) eatures and keywords: product-term line programmable array logic bit line word line programmable-an array (or product-term array) pull-up resistor wired-logic wired-an macrocell 22V PL

16 6 SECTION 5 PROGRAABLE ASIC LOGIC CELLS ASICS... THE COURSE 5.4. Logic Expanders (a) (b) LAB LAB LAB (Logic Array Block) LAB LAB LA Altera AX LAB chipwide interconnect LAB 6 macrocells per LAB 5 LA (local array) programmable inversion product term 5 select 3 system clock(s) system clear clock, clear, preset, enable Q macrocell macrocell 2 OUT macrocell output shared expander parallel expander to next macrocell macrocell feedback 4 other macrocells in LAB (c) The Altera AX architecture (the macrocell details vary between the AX families the functions shown here are closest to those of the AX 9 family macrocells) (Source: Altera (adapted with permission).) (a) Organization of logic and interconnect (b) LAB (Logic Array Block) (c) acrocell eatures: Logic expanders and expander terms (helper terms) increase term efficiency Shared logic expander (shared expander, intranet) and parallel expander (internet) eterministic architecture allows deterministic timing before logic assignment Any use of two-pass logic breaks deterministic timing Programmable inversion increases term efficiency

17 ASICs... THE COURSE 5.4 Altera AX Timing odel (a) internal signal I t LOCAL t LA t SU t R (b) local array logic array setup register delay local array I total=8.5ns t LA t 4 t t 2 t3 internal signal O t 2 t 3 macrocell array t 4 O LA 2 (c) t LOCAL t LA t PEXP t SU t R (d) local array.5 logic array 4. parallel expander setup register delay. 3.. total=9.5ns I2 t t2 t3 internal signal I2 LA t t 2 t 3 2 t 5 t 4 internal signal O2 LA t 4 t 5 2 O2 (e) internal signal I3 t LOCAL t LA local logic array array.5 4. LA t t 2 t SEXP shared expander 5. t LOCAL local array.5 LA t COB combinational. t 3 t 4 t 5 2 internal signal O3 total=ns (f) LA I3 t t 2 t 3 t 4 t 5 2 O3 Altera AX timing model (ns for the AX 9 series, '5' speed grade) (Source: Altera.) (a) A direct path through the logic array and a register (b) Timing for the direct path (c) Using a parallel expander (d) Parallel expander timing (e) aking two passes through the logic array to use a shared expander (f) Timing for the shared expander (there is no register in this path)

18 8 SECTION 5 PROGRAABLE ASIC LOGIC CELLS ASICS... THE COURSE Power issipation in Complex PLs Key points: static power Turbo Bit 5.5 Summary Key points: The use of multiplexers, look-up tables, and programmable logic arrays The difference between fine-grain and coarse-grain PGA architectures Worst-case timing design lip-flop timing Timing models Components of power dissipation in programmable ASICs eterministic and nondeterministic PGA architectures 5.6 Problems