REPEAT EXAMINATIONS 2004 SOLUTIONS

Transcription

1 REPET EXMINTIONS 24 SOLUTIONS MODULE: EE Digital Electronics COURSE:.Eng. in Electronic Engineering (year ).Eng. in Info and Communications Engineering (year ).Eng. in Mechatronic Engineering (year 2).Eng. in Digital Media Engineering (year ).Eng. in Engineering Common Year (year ) YER: & 2 (as above) EXMINER: Dr. Ovidiu Ghita (DCU extension 7637) SOLUTIONS Digital Electronics EE Repeat 24-SOLUTIONS Page

2 uestion. n engine has 4 fail-safe sensors. The engine should keep running unless any of the following conditions arise: o If sensor 2 is activated. o If sensor and sensor 3 are activated but sensors 2 and 4 are down. o If sensor 3 and sensor 4 are activated at the same time. (a) Derive the truth table for this system. = Sensor =Sensor2 C=Sensor3 D=Sensor4 Sensor activated = = Shutdown= C D [4 marks for correct table] Digital Electronics EE Repeat 24-SOLUTIONS Page 2

3 (b) Design, using arnaugh Map techniques, a minimum ND-OR gate network for this system. Draw the resulting digital circuit diagram. CD Resulting expression is: = + CD + C C D [8 marks for expression & diagram] (c) Design, a digital circuit that will implement the minimal ND-OR gate network found in (b) using both (i) NND gates only and (ii) NOR gates only. ssume that each logic gate can have any number of inputs and that inverted inputs are available. (i) NND = + CD + C = + CD + C =. CD. C C D (ii) NOR Digital Electronics EE [3 marks] Repeat 24-SOLUTIONS Page 3

4 = + CD + = + CD + C C = + ( C + D) + ( + C) = = + ( C + D) + ( + C) C D [3 marks] (d) If the time delay experienced by a NND gate is 8ns and the time delay experienced in a NOR gate is 2ns. Which implementation of (c) is faster? y how long? or the NND gates the total delay is 2 x 8ns = 6ns or the NOR gates the total delay is 3 x 2ns = 36ns NND gate implementation is faster by 2ns [3 marks] (e) Prove the rule of oolean algebra: + = + + = = ( + )( + ) =.( + ) = + [4 marks] uestion 2. (a) Explain the operation of an exclusive OR gate. Draw the symbol. Calculate the truth table for its operation. Describes events that are true if and only if one of the motivating events is true. bbreviated XOR. Digital Electronics EE Repeat 24-SOLUTIONS Page 4

5 Symbol: Truth table: [2 marks description + symbol] [2 marks truth table] (b) Give 2 ways of expressing an exclusive OR gate and obtain the logic diagrams using ND, OR and NOT gates. rom the truth table in (a) we can say = if = or = but not if and = (i)=> = ( + )( ) rom this table we can also say (ii) = + (i) (ii) [4 marks each diagram (8 total)] Digital Electronics EE Repeat 24-SOLUTIONS Page 5

6 (c) Convert to binary the following number (each step should be shown clearly): 5.75 conversion to binary in two stages. 5/2 = 7 remainder 7/2 = 3 remainder 3/2 = remainder LHS =.75 * 2 = carry of.5 * 2 = carry of. RHS =. NS. 2 [6 marks] (c) Perform the following operation using 9 s complement CD: =? (get 9 s complement ->34) No end around carry >>> negative number 9 s complement of 78 >>> 2 NS = -2 [7 marks] uestion 3. (a) Explain the operation of a half-adder. What are the logic equations? Draw the logic diagram for a half-adder. To add 2 least significant bits (the LS) we do not need a carry input from a previous stage. Therefore we only need a half adder. S C Where S is the sum and C is the carry. The logic equations are: Digital Electronics EE Repeat 24-SOLUTIONS Page 6

7 S C = = + = The logic diagram can be drawn as: o o C o o o o o S o o o [4 marks for correct diagram] [4 marks for the description] (b) Describe the operation of a full-adder. How is a full adder constructed from two half-adders? In what situation would a half-adder not be sufficient, meaning that a full-adder would be required? or all other bits a half adder will not suffice as there may be a carry input from a previous stage. full adder has 3 inputs k k C k- and 2 outputs S k and C k full adder may be constructed from two half adders using additional logic. C - HL DDER C' = HL DDER C" = C - ( ) + C - ( ) C - C S One half adder adds k to k to give and intermediate sum S k and carry C k. nother half adder then adds S k and C k- to give the final sum S k and another intermediate carry C k [4 marks for correct diagram] [4 marks for the description] Digital Electronics EE Repeat 24-SOLUTIONS Page 7

8 (c) How can a Two s complement dder/subtractor be built using full adders. Show a diagram of the extra logic circuitry required. DD/SU CIN S3 S2 S S This circuitry can generate the 2 s complement when we wish to do a subtraction When DD / SU = => the circuit adds When DD / SU = => the circuit subtracts XOR gates act as True/Complement in that they invert when the DD / SU line is set to and a is added to the LS, so that the two s complement will be generated. [5 marks for correct diagram] [4 marks for the description] uestion 4. (a) Explain the operation of a right/left shift register. Draw the logic diagram to help explain its operation. R/L igure: Right Left Shift Register Serial in (to Right) Serial in (to left) R L R L R L 2 2 Serial Out (right) 2 2 CLOC 2 Serial Out (left) [6 marks for diagram] Digital Electronics EE Repeat 24-SOLUTIONS Page 8

9 Shift registers can be used to transfer data from right to left, shift left by connecting the output of a flip-flop back to the input of the flip-flop on its left. shift from left to right, shift right, can be carried out during normal operation of the shift register shift right and shift left register can be combined by suitable gating and control signals. In the operation above R / L = => shift right In the operation above R / L = => shift left Explain the operation of the logic gates simply an ND gate with a value of has an output of zero and an ND gate with one input of. will have the output. In effect the R/L line turns either the Right or Left ND gate on or off. The OR gate simply combines the output of the two ND gates to bring forward the correct output. [6 marks for description] (b) Explain the operation of a shift register with feedback. 3 2 If the serial output of a shift register is connected back to the input [ to ], [ to ] then the sequence of numbers stored in the register will circulate. E.g. 3 2 pulse pulse 2 pulse 3 pulse 4 Note that the last row is the same as the first row. [8 marks for diagram] [5 marks for description] uestion 5. Digital Electronics EE Repeat 24-SOLUTIONS Page 9

10 (a) Explain the operation of a master-slave flip-flop with asynchronous set and reset inputs. Draw the diagram and derive the truth table. S Truth table: R [4 marks for diagram] S R n+ X X NOT LLOWED X X X X n NORML OPERTION n [5 marks for truth table] The set & reset inputs [S,R] override the, inputs and their operation is not affected by the application of the clock signal. When the asynchronous inputs are set to the flip-flop operates as a normal master-slave flip-flop. [4 marks for description] (b) Explain the operation and outline the problems associated with asynchronous Digital Electronics EE Repeat 24-SOLUTIONS Page

11 counters. Draw a graph of the outputs to help explain your answer. 2 [3 marks] If the output of one counter is connected to the clock of the next counter then all 2 N states can be used in the binary counter. N flip-flops => 2 N states, base 2 N This counter is called an asynchronous or ripple counter as the clock pulse effectively ripples through the counter. [3 marks] The correct waveform is shown here: igure: Cumulative Delay of synchronous Counters ( t represents delay) CLOC t t 2 t 2 3 t There is a cumulative delay which is a major disadvantage. This cumulative delay of an asynchronous counter limits the rate at which a counter can be clocked and can also create decoding problems. alse outputs that result are called glitches. [6 marks] Digital Electronics EE Repeat 24-SOLUTIONS Page