Plasma dicing 300mm framed wafers - Analysis of improvement in die strength and cost benefits for thin die singulation

Transcription

1 2017 IEEE 67th Electronic Components and Technology Conference Plasma dicing 300mm framed wafers - Analysis of improvement in die strength and cost benefits for thin die singulation Richard Barnett SPTS Technologies Ltd Newport, United Kingdom Richard.Barnett@orbotech.com Abstract Plasma Dicing uses Deep Reactive Ion Etch (DRIE), also known as The Bosch Process. This is a wellestablished front-end technology, used in silicon MEMS micromachining and via etching in 3D packaging, which is now finding a new home as a dicing technology in the back-end of semiconductor processing. This paper will discuss the key issues and integration challenges. This is not only in wafer design and preparation, but also how the process flow is not disrupted to the extent where it becomes a hindrance to the adoption of a technology that offers so many potential benefits. Keywords-plasma dicing, thin die singulation, silicon DRIE I. INTRODUCTION With the variety of technologies for mobile applications evolving so rapidly, from smartphones & smart-watches to even smaller wearables integrated into fabrics and other clothing, the demand for smaller device packages that are, thinner, and provide faster and more power efficient components shows little evidence of abating. We, the consumer, are fuelling this with our expectations; that our mobile and wearable devices survive our lifestyle activities, our medical/automotive/smart-home sensors function for as long as is needed, etc. One parameter above all others coming to the fore as a consequence of device shrink and performance expectations is die strength, which is something that plasma dicing has the capability to improve significantly. Conventional blade and LASER dicing will still be a cost-effective method to singulate die in some cases, however, there are a growing number of applications where plasma dicing can offer economic and die quality benefits when compared to conventional techniques. In some cases, namely for smaller and thinner die, plasma dicing enables singulation which is virtually impossible with the other methods. Plasma dicing before grind (DBG) has been used in selected applications for a number of years, but plasma dicing after grind (DAG) is at the early stages of adoption for volume production. The trend toward thinner, smaller die, along with the in-service reliability demands, distinguishes plasma dicing as an increasingly attractive alternative. Silicon plasma dicing uses Deep Reactive Ion Etch (DRIE) technology, more typically referred to as the Bosch process. This is a well-established production technology, used in silicon MEMS micromachining and via etching in 3D packaging. DRIE is now adding dicing technology in the back-end of semiconductor processing to its portfolio of production applications. Like any other dry step in the device process flow, integration is key, and these challenges are the only gate to the use of plasma as a singulation method. These considerations are not only related to wafer layout and preparation, but also accommodating the standard back-end frames and tape combinations. The objective is that the process flow is not disrupted to the point where it becomes a hindrance to the adoption of a technology that offers so many potential benefits. II. BENEFITS OF PLASMA DICING A. No Damage = Stronger Die / Higher Yield In mechanical dicing, through the use of high speed rotating blades, the constant risk of chipping and causing significant damage at the edge of the die is a known issue. In LASER dicing heat damage has to be accounted for, alongside the secondary issue of ablated by-products being re-distributed across the wafer. For both blade & LASER these concerns become much more significant for smaller and thinner die. As a largely chemical process, plasma dicing eliminates all of the damage caused by the other traditional methods of singulation, e.g. crack initiation, thermal damage, edge chipping, contamination. Furthermore, plasma dicing can remove the necessity for liquids to be used, i.e. cool blades, direct LASERs and postsingulation rinses to remove debris. However, there are some integration schemes where use of wet processes, in combination with plasma can be considered. These will be discussed later /17 $ IEEE DOI /ECTC

2 Figure 1. Silicon Scallop Characteristic DRIE scallops cause no crack initiation The Bosch process, which is made up of alternating etch and deposition steps creates a characteristic scallop on the sidewalls of the die (see Fig 1), each scallop representing a single etch-passivation cycle. Typically, a scallop has <3μm lateral incursion into the silicon and, as they are generated through a chemical etch, do not cause crack initiation nor act as stress raisers. Use of electrostatic clamping is normal practice for DRIE and for security of the overall substrate is vital. A more detailed discussion of this point follows later. B. Increased Die Counts Dicing lane widths are set as a consequence of many demands, from the width of the saw blade or LASER spot, to the placement and accuracy for test pads. Another aspect of dicing damage limitation is the use of extended die area as a buffer zone. Considering plasma, dicing lanes are not restricted by the singulation method and can be significantly reduced, leading to more available silicon real estate for increased die per wafer. The only limitation here will be the method of lane definition, options for which are considered later. For smaller die, like RFID chips with typical dimensions around 200nm-400nm, this additional space can substantially increase the number of devices patterned onto the wafer, in some cases in the region of % more. For larger die, the lane width benefit is not so influential. However, with plasma dicing eliminating chipping and cracks, there are additional options. Most die have built in regions to protect the active region from any singulation induced damage. These are referred to as crack stop areas, guard rings, seal rings, etc. There is the potential for removal of this unproductive space the die layout providing further material for active die. This option is not so straightforward, as over time, these regions along with the dicing lanes, have become home to various structures, including test pads, EMC protection, and so on. There has to be a motivation by the user to move these structures elsewhere on the device, or wafer, otherwise this major benefit cannot be fully realised. Alongside the lane width reduction and removal of crack stop regions, another way that a die count gain can be achieved with plasma relates to the overall die layout on the wafer. Plasma is not reliant on the use of a directional cutting medium and therefore there is no necessity to have a wafer layout constrained by orthogonal dicing paths. Plasma dicing also gives device designers much greater freedom in creating appropriate die shapes and sizes, for the eventual end products as well as the positioning of test groups to make best use of the available wafer area. C. Increased throughputs for smaller, thinner die Currently, when smaller die sizes are implemented, the number of dicing lanes increases accordingly. For the serial singulation approaches such as LASER or blade, the consequence is that the number of passes increases giving a reduction in throughput. Plasma dicing is a parallel process, with all of the dicing lanes being etched simultaneously. The throughput of plasma dicing is largely governed by the wafer thickness, or aspect ratio of the etch, and not by the number of dicing lanes, or die, per wafer (See Fig 2). As mentioned earlier, there is a trend towards thinner die and the mechanical sawing and laser dicing approaches will encounter serious challenges when wafer thickness goes to <50μm. Here, further decreases in throughput will occur as parameters such as feed speeds, blade speeds, LASER power levels, have to be reduced to prevent mechanical or thermal damage affecting these fragile devices. Plasma Figure 2. Curves showing how Blade and LASER increase cycle time as die size reduces. Plasma dicing (orange dashed line) has constant dicing rate regardless of die size. The converse is true for plasma dicing, thinner wafers will be singulated in less time leading to gains in throughput (see Fig 3). Considering both the use of plasma dicing and reduced dicing time, for thinner wafers an increase of throughput will be achieved, while still providing higher die strengths. 344

3 Figure 3. Effect of wafer thickness on silicon etch rate Due to the front end genesis of the plasma approach, cluster platforms are available capable of carrying multiple modules thereby giving an easy scaling from pilot to volume production. D. Consistency = Increased Throughput DRIE processes are designed for consistent behavior, wafer-to-wafer and batch-to-batch. Plasma dicing takes advantage of that behaviour to produce consistent die. Design features of the plasma source as well as the process recipes ensure the etch conditions are repeatable for each substrate processed. The use of an endpoint control system also assists in managing the process, particularly at the point where the singulation is completed and the tape becomes exposed. For both the die and the tape, when Plasma is employed, an endpoint solution is a critical aspect which is an enabling function for the successful use of plasma dicing. The same cannot be said for the current technologies, where blade dicing, for example, requires a regular blade dressing (reducing throughput) to maintain a consistent blade shape and performance. LASER sources deteriorate over time and also need to be managed to ensure consistent delivery of power through the lifetime of the source. Consistency, from plasma and the use of endpoint control, can reduce the need for 100% inspection and further emphasizes the yield and quality advantages for the plasma dicer. III. INTEGRATION CONSIDERATIONS The easiest way of adopting all of the measures necessary to release all of the benefits of plasma dicing is to start from a blank sheet of paper, effectively designing in plasma dicing from the outset of a device life cycle. There are, however, novel approaches which have already proven that plasma dicing can be implemented for existing process flows. Key to integration of plasma dicing is a simple tenet, to provide a defined and compatible dicing lane for the plasma etch step. The first challenge to plasma dicing is the materials that occupy the dicing lane. For the purposes of this paper, we are focusing on silicon plasma dicing which uses the Bosch process. A process module, designed as a silicon etcher, is used for this step. Metals in the dicing lane are a blocking point, and dielectrics cause some additional integration challenges. The ideal scenario, of course, would be for these non-si materials to have been dealt with before the substrates reach the plasma dicing stage. The chemistries and conditions necessary to etch the metals, likely to be present, would present considerable risks to the frames and tapes and potentially have compatibility issues with any exposed bondpads or bumps that may also be exposed. For dielectric layers, there is the possibility of etching through, however the typical silicon etch modules used for plasma dicing can only be considered as reasonable dielectric etchers. This means there are some compromises in terms of rate (and therefore throughput) and selectivity. Both of these will affect the costs of the step as well as the integration scheme overall. Aside from coping with these layers in the dicing step itself, process flow and die layout and design come into view. Metal is the worst case scenario. Whereas metal test groups can be relocated for new device layouts, existing products will need an additional step to manage them. This can be completed during the front end process flow with an etch step to remove them or alternatively, LASERs and/or mechanical saws can be used to pre-define the dicing lanes. In this method, more appropriate for larger die, the LASER or blade is solely used to cut through the lane, and whatever stack of materials is present, stopping at the silicon. Without cutting into the silicon itself, these methods do not affect the die strength as there are no cracks, or damage, imparted into the bulk of the device. As this approach retains the limitations in terms of orthogonal layout, lane width and speeds, larger die are less affected and would benefit most from this type of scheme. To catch any debris and protect the active die from this additional step, some coatings can be employed which will then require removal post-singulation. Removal of these layers can be either singular use or combination of wet and dry stripping methods. Some available options can be rinsed off using DIwater only, or may require something more linked to PR stripping as in the front-end of line. Due to this, some ide applications, e.g. bio-mems, may not be compatible with this approach. Another method for defining the dicing lane is adding a mask layer using standard photolithography techniques. Although use of this approach would be limited due to the alignment required and the difficulty in exposing a thinned substrate suspended on a non-fixed tape. This would add costs and complexity including the necessity of a post-etch strip step, as discussed above. More easily adopted is the approach of using existing layers, but at increased thicknesses to allow for erosion during plasma etching. The layers at the conclusion of the front-end will comprise of dielectrics or organics, both of which are both ideal mask layers for the silicon DRIE process. This latter method can be described as self-masking or maskless and requires the lane to be opened during process steps including bondpad opening. Test pads are a common feature on all wafers, and with the range and size of test probes available, there are minimum dimensional limits on test group features, which 345

4 then imposes a minimum consideration for the lane width itself. In conventional dicing schemes, these test pads are simply obliterated by the blade or LASER dicing method. When plasma dicing is introduced, allowing the designer to reduce the lane widths, there is now a conflict regarding the location of the test groups. Taking full advantage of the additional real estate with reduced lane widths and the flexibility of die shape/positioning, alternative locations can be readily found, maybe through creation of test group die which can be singulated and retained for future references. There is also the opportunity to use on-die test locations. Blank-sheet design for plasma dicing, obviously makes the effort to relocate these test structures much easier. IV. SUBSTRATE MANAGEMENT As mentioned previously, our substrate is no longer just the wafer, there must be consideration given to the frame and the tape. materials available it is no surprise that whilst the majority can be readily used for plasma dicing, some are not so capable. TABLE I: Table showing some properties of typical dicing tape materials. Tape Product Melt Comment Tape PET=Polyethyleneterephthalte 250 C Resin-based. 70 C glass temperature Thermoplastic. 82 C Tape PVC = Polyvinylchloride ~160 C glass temperature, Decomposes at 140 C Tape PO = Polyolefin ~ C Tape PI = polyimide - Tape PA = polyamide C Frame Polyphenylene sulphide 275 C Thermoplastic. Softens 20 C below melt. Actually a composite typically PP/elastomer/+stiffn ers, stabilizers & additives OK to 450 C. Shrinks 1%at 400 C Thermoplastic. Glass temp 190 C Frame Stainless Steel Indestructible? Figure 4 Example of a typical mounted wafer In plasma dicing, as is normal practice for DRIE in MEMS, etc, the wafers are clamped electrostatically on a chuck with active cooling. This is a critical aspect that must be managed closely to maintain a low substrate temperature. The substrate, in the case of DAG, now includes the frame and tape, on which the wafer is mounted (See Fig. 4). The DRIE process is exothermic and the temperatures generated from this process increase as the silicon etch rate increases. Given the cost sensitivity of this step, high rates are demanded to provide cost effective throughputs. As the dicing etch approaches complete singulation the original thermal mass of the wafer is replaced with a body much less able to deal with the thermal component of the process. The heat generated poses a risk to both the integrity of the tape and control of the silicon etch conditions. Loss of this control will lead to catastrophic failure of the tape and ultimately scrapping of the wafer in its most costly form. The tape is now the weakest element in the chain that forms our new substrate. Infrastructure surrounding die singulation, such as tapes and frames, has been around for decades and so plasma dicing has, for the most part, had to accept these elements. With such a variety of tape film Working with the plasma etch vendor will give the best opportunity to reach a conclusion on tape selection. The ultimate choice will depend on the subsequent steps e.g. if a backside metal is present. Coming back to the management of the tape, the reaction to the increased temperature of the process will have an impact on the tape, or more specifically the adhesive. It is easy to forget that the tape is made of a number of constituent parts, typically a film layer (or layers) and an adhesive layer, illustrated schematically in Fig. 5. Figure 5 Simple description of typical dicing tape The majority of adhesives on dicing tapes are UV treatable allowing the adhesive strength to be reduced ready for pick and place. This is important since the adhesives, normally acrylic in make-up, can react to increased temperatures changing the nature of the adhesive. 346

5 During heating phase, adhesion reduces. After cooling to RT, adhesion is increased proprietary method, but the SPTS Sentinel TM approach gives an early warning that the substrate is no longer under active cooling and stops the process (See Fig 8). This then allows the user to remove the affected substrate, and if possible, to rectify the cause and complete singulation. Ability to catch these events and recover the substrates greatly enhances the plasma dicing capability. Figure 6 Chart showing tape adhesion strength and modulus compared to exposed temperature. In Fig 6 above it can be see that as the temperature increases the tape softens encouraging a further conformation to the adhering surface, which is rendered permanent upon cooling. Adhesion strength, as a consequence is increased and cannot be recovered through reheating, where the cycle simply repeats itself. Active cooling of the substrate using a re-engineered ESC ensures the magnitude of these temperature excursions is minimized (See Fig 7). Figure 7 Cooling advantage of advanced dicing ESC Some of the UV components may also be affected by the vacuum conditions reducing the efficiency of the UV release step. With this in mind, a risk of increased adhesion strength and lack of release, it can be seen how critical it is to prevent the temperature excursions. The quality of the tape/wafer interface is also a critical feature for plasma dicing, whereas it was not such an issue for the blade and LASER techniques. Any trapped volumes can expand when the etch process starts due to the generated heat and cause the wafer to be removed from the cooling surfaces within the process chamber. This results in the loss of control mentioned earlier that leads to the ultimate loss of the wafer. There are means to avoid this happening. Firstly, in the taping process ensuring the tension of the tape and the mounting procedures are such that to avoid the creasing or slackening of the tape. Trapping of gases will then be prevented and the bubbles would not appear. In the event of a poor tape quality incident, even after control of the taping procedure is maintained, there have been no real opportunities based on normal wafer monitoring to detect an event during the process. Recent developments, however, have generated a methodology that can provide an endpoint control functionality whilst monitoring the substrate for loss of cooling and abort the process before any real damage is caused. The technology referred to is still a Figure 8 Chart showing Sentinel TM signal highlighting loss of substrate cooling. Previously, OES endpoint had been the dominant method for process control for DRIE processes to a stop layer or buried cavity. However, the OES plasma monitoring on its own does not have the ability to spot potential events occurring with respect to wafer integrity. The Sentinel approach, described above, combines the monitoring capability with an endpoint detection that matches enhanced OES, such as the SPTS Claritas TM.[2] Figure 9 Chart showing Sentinel signal comparing to Claritas OES endpoint As can be seen from the comparison traces in Fig. 9, the Sentinel signal change matches the Claritas enhanced signal in highlighting the exposure of the tape in the dicing lanes. Having this dual functionality gives the user the ultimate security of their substrates, even managing to indicate where upstream steps have failed. We will see later that this endpoint capability is also fundamental to ensuring that plasma dicing provides the promised increase in die strength. 347

6 Some substrates will come with backside metal layers, typically solderable layers for power and LED submount applications. Metals will not be etched, so a method for separating the die with the metal layer in place, after plasma dicing must be found. Tape choice becomes more relevant here with a requirement to prevent stringers or loose metal fragments from accompanying the picked die. There are several methods for the backside metal separation ranging from the use of LASER and blade through hot or cold expansion, stretching and cleaving. This paper does not have a detailed discussion on these techniques, suffice it to say that the plasma process does have an influence on the success of each method. Having the appropriate adhesive control, based on the tape starting properties and process management, will assist the chosen method in clean picking of die ready for placement or shipping. The tapes used in current singulation steps are nonconductive and through the Bosch process polymer removal step, which is bias driven, will become positively charged. This standing charge will deflects negative ions within the plasma towards the silicon sidewall, removing the protective polymer coating allowing a lateral etch to occur at the base of the die. V. DIE STRENGTH COMPARISONS Recent work [3] has shown that plasma dicing increase the strength of resulting singulated die. This gain in die strength remains even if integration with the existing process flow uses lane definition by a blade or LASER. With these combination methods, significant strength/yield increase can be achieved. However, as indicated above and from the graph below it can be seen that the importance of plasma processing control cannot be underestimated. Plasma dicing, even when defined by photolithography, can result in reduced die strength if the process control is insufficient and a large sized notch is allowed to form at the wafer/tape interface. This notch is, in reality, uncontrolled silicon etching of and into the underside of the die. Plasma dicing does offer major benefits compared to all other dicing methods, but without the necessary process control these benefits will be negated by a loss of die strength and device reliability. Previously, we have seen that plasma dicing eliminates all mechanical damage associated with conventional methods. It is important, for plasma, that this notch risk is tightly controlled. Two patented technologies, already wellestablished and proven in SOI MEMS manufacturing, can be employed to prevent damage to the silicon and the tape during plasma dicing. Sentinel TM was described earlier and as a proprietary endpoint technology can accurately monitor the progress of the etch front and trigger the recipe software to initiate the required change in process conditions when the tape is exposed. Patented bias pulsing [4] is then employed during the final stage, or overetch, of the die singulation step. Pulsing allows the standing charge to dissipate and prevents the loss of sidewall passivation leading to any lateral under-etching of the die, or notching. Fig 11 compares the strength of the various plasma dicing schemes. Plasma singulated die with small or optimized reduced notching is typically twice that of a blade or blade/laser approach. However, plasma dicing without control of the notching, via endpoint and pulsing, sees a severe deterioration in the resulting die strength. Figure 10 Schematic showing notch phenomena The outcome of this phenomenon is a notch. The same effect is observed in etching MEMS devices from silicon-oninsulator (SOI) wafers where the oxide becomes charged once exposed (illustrated in Fig 10). Patented methods to combat this notching developed for the MEMS industry have now proved useful to optimize plasma dicing to a tape. When combined with an endpoint detection that spots the tape exposure at the earliest possible moment, the notch size can be limited to the absolute minimum if not completely eliminated. Figure 11. Effect of dicing method on die strength 348

7 VI. COST OF OWNERSHIP Examples where the die size is not sufficiently small, the relative wafer throughput of LASER dicing could appeal to prospective users, especially when comparing the capital cost of a laser dicing system against that of a plasma etch system. Careful consideration, however, must be made relating to the ongoing cost of ownership when selecting the most appropriate solution for a specific device application, as well as the coming trends in die size and wafer thickness. If all the on-wafer aspects of plasma are utilised, combining the topics previously discussed, this reveals the potential of a major cost advantage over the conventional methods. Figure 12. Cost of ownership comparison for Blade vs LASER vs plasma dicing for two different die sizes (incorporating the possibility of a thinner wafer and narrower dicing lanes for plasma dicing) In Fig 12, the cost of the singulation step for 1000 die has been compared (for two die sizes, 1mmx1mm and 3mmx3mm). For the conventional methods a 100μm thick wafer is used with 80μm dicing lanes. For plasma dicing, the wafer is thinned to 50μm with lanes reduced to 10μm. When coupled with the expected yield gains and increased die counts from lane reduction, and the ability to eliminate crack stop areas, it becomes clear there are substantial savings possible using the plasma approach. For the 1mmx1mm die, the blade singulation cost per 1000 die is 20 times that of the plasma dicing approach. This calculation does not include potential costs of integration, but the clear indication is that there would be sufficiently rapid ROI for the introduction of a plasma singulation method. VII. CONCLUSIONS Despite many integration challenges, plasma dicing offers considerable benefits for die singulation, with opportunities to achieve increased throughput and die count per silicon area, flexibility for die layout and design and, perhaps most important of all, improved die quality/strength. As such, plasma dicing is well positioned to become the benchmark technology for fabs seeking to increase die strength, throughputs and yields for small or thinned fragile die, on 150mm, 200mm or 300mm wafers. ACKNOWLEDGMENT I would like to acknowledge the support of the SPTS Etch Applications team (Janet Hopkins, Oliver Ansell and Martin Hanicinec) as well the support from various other industry colleagues in the fields of dicing tapes and die separation who have preferred to remain anonymous at this time. REFERENCES [1] Thin Wafer Processing and Dicing Equipment Market report, Yole Développement, May 2016 [2] US Patent No 9,159,599 Apparatus for chemically etching a workpiece [3] R. Barnett, D. Thomas, O. Ansell, J, Carpenter, W. Worster, G. Ragunathan Improving Device Yields and Throughput using Plasma Dicing presented at IWLPC2015 [4] US Patent No: 6,187,685 - Method and apparatus for etching a substrate 349