ME 515 Mechatronics. Introduction to Digital Electronics

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1 ME 55 Mechatronics /5/26 ME 55 Mechatronics Digital Electronics Asanga Ratnaweera Department of Faculty of Engineering University of Peradeniya Tel: 8239 (3627) Introduction to Digital Electronics Digital circuits are evolved from transistor circuits being able to output at one of the two voltage levels depending on the levels at its inputs. The two levels, usually or 5 V are the low and high signals and represented by and. Therefore, binary number system is widely used with digital circuitry. 5 October 26 Asanga Ratnaweera, Department of 2

2 ME 55 Mechatronics /5/26 Boolean Expressions, Logic Gates & Truth Tables Z=A.B Z=A+B AND OR A B Z A B Z Z A = A B Z B XOR Z Z=A NOT 5 October 26 Asanga Ratnaweera, Department of A Z 3 Boolean Expressions, Logic Gates & Truth Tables Z=A+B NOR A B Z F = AB NAND F F = A F BUF 5 October 26 Asanga Ratnaweera, Department of 4 2

3 ME 55 Mechatronics /5/26 Commercial Logic ICs +Vcc Vcc Gnd (V) Gnd ( V ) 5 October 26 Asanga Ratnaweera, Department of 5 Logic Families Description Code Supply voltage Max. supply current TTL 74XX, 74LSXX V - ma Input Output CMOS 4XX or 74HCXX 5-5 V -.2 ma Input Output state Voltage / V Current / ma state Voltage / V V 4.95 Current / ma Max. Op. frequency Active power Cons. 33 MHz 8 mw 5 October 26 Asanga Ratnaweera, Department of MHz. mw 6 3

4 ME 55 Mechatronics /5/26 Classification of Digital circuits Digital electronics is classified as: Combinational logic circuits Combination logic output depends only on the inputs levels. Sequential logic circuits. The output of sequential logic depends on both stored levels and the input levels. Therefore, sequential logic is capable of remembering a particular state. 5 October 26 Asanga Ratnaweera, Department of 7 Combinational logic circuits A B C Z Z = A.B.C Z = A.B.C Therefore; Z = A.B.C or A.B.C Z = A.B.C + A.B.C Truth Table 5 October 26 Asanga Ratnaweera, Department of 8 4

5 ME 55 Mechatronics /5/26 Combinational logic circuits Producing Boolean expressions from truth table: Find the s in the Z column Write the Boolean expression for each ( logic high output) Write the expressions out in words, e.g. Z = ( A AND NOT B AND C) OR (A AND B AND C) Write out the inputs, e.g. A, B C Draw in any NOT gates Draw in the AND gates Finally draw in the OR gates if required 5 October 26 Asanga Ratnaweera, Department of 9 Combinational logic circuits A B C Z Z = A.B.C + A.B.C A B C Z 5 October 26 Asanga Ratnaweera, Department of 5

6 ME 55 Mechatronics /5/26 Combinational logic circuits Pin-out Diagrams & Drawing Circuits You must be able to select suitable logic ICs (chips) and draw in the connections for a given logic system. An example is given below. Don t forget to draw in the connections for +Vcc ( the positive supply voltage) and v. Remember you don t need to use all the logic gates in a chip if you only need one, you only use one! 5 October 26 Asanga Ratnaweera, Department of Combinational logic circuits +Vcc +Vcc Vcc Input A Input B Gnd (V) OUTPUT Gnd (V) v 5 October 26 Asanga Ratnaweera, Department of 2 6

7 ME 55 Mechatronics /5/26 Combinational logic circuits Boolean simplification De Morgan s theorem x y = x + y x + y = x y Karnaugh Map A grid of 2 N squares where N is the number of input variables in the Boolean expressions. K-maps are usually used for minimization expressions with six or fewer variables 5 October 26 Asanga Ratnaweera, Department of 3 Combinational logic circuits Ex: For three variables Each square represents one minterm Only one variable changes between adjacent squares The maps are constructed to wrap around so that top and bottom corresponding squares are adjacent 5 October 26 Asanga Ratnaweera, Department of 4 7

8 ME 55 Mechatronics /5/26 Combinational logic circuits For two variables For four variables 2 4 = 6 5 October 26 Asanga Ratnaweera, Department of 5 Combinational logic circuits Filling out K-Map The adjacent squares that have s are combined in groups of 2, 4 or 8. When squares can be chosen as several groups, the largest group has to be selected and each square should be used only once 5 October 26 Asanga Ratnaweera, Department of 6 8

9 ME 55 Mechatronics /5/26 Combinational logic circuits AC BC AB Identify the variables which do not change within the cluster and write them down as a Boolean expression X = BC +AC + AB 5 October 26 Asanga Ratnaweera, Department of 7 Combinational logic circuits More examples CD AB 5 October 26 Asanga Ratnaweera, Department of 8 9

10 ME 55 Mechatronics /5/26 Design of Combination Logic circuits Ex: Three push buttons are provided to turn on a machine in an automobile assembly plant. For safety purposes, the machine is to be turned on, only if at least two of the buttons are pushed. Obtain a suitable Logic Circuit. 5 October 26 Asanga Ratnaweera, Department of 9 Applications of Combinational circuits Adders / substructures Half adder Full adder 5 October 26 Asanga Ratnaweera, Department of 2

binary number should be generated at the output of the encoder 5 October 26 Asanga Ratnaweera,

11 ME 55 Mechatronics /5/26 Applications of Combinational circuits Encoders A binary encoder generates a binary code corresponding to the input value presented at its inputs Ex: 8 bit encoder If 5 is pressed, binary number should be generated at the output of the encoder 5 October 26 Asanga Ratnaweera, Department of 2 Applications of Combinational circuits Encoders 5 October 26 Asanga Ratnaweera, Department of 22

12 ME 55 Mechatronics /5/26 Applications of Combinational circuits Decoders A binary decoder converts binary information to discrete outputs. 5 October 26 Asanga Ratnaweera, Department of 23 Applications of Combinational circuits Decoders 5 October 26 Asanga Ratnaweera, Department of 24 2

13 ME 55 Mechatronics /5/26 Applications of Combinational circuits Multiplexers A multiplexer selects binary information from one of many input lines and directs it to a single output line. 5 October 26 Asanga Ratnaweera, Department of 25 Applications of Combinational circuits Multiplexers 5 October 26 Asanga Ratnaweera, Department of 26 3

14 ME 55 Mechatronics /5/26 Applications of Combinational circuits De-multiplexers A de-multiplexer receives binary information on a single input line and passes this information to one of its many output lines. 5 October 26 Asanga Ratnaweera, Department of 27 Sequential logic circuits The output of a sequential logic device depends on its present internal state and the present inputs. Sequential logic device has some kind of memory of at least part of its ``history'' (i.e., its previous inputs). The memory elements in a sequential circuit are called flip-flops. 5 October 26 Asanga Ratnaweera, Department of 28 4

15 ME 55 Mechatronics /5/26 Flop-Flops A flip-flop circuit can be constructed from two NAND gates or two NOR gates. 5 October 26 Asanga Ratnaweera, Department of 29 Flop-Flops Clocked SR Flip-Flop Information from the S and R inputs passes through to the basic flip-flop only when the clock pulse goes to. With both S= and R=, the occurrence of a clock pulse causes both outputs to momentarily go to. 5 October 26 Asanga Ratnaweera, Department of 3 5

16 ME 55 Mechatronics /5/26 Flop-Flops D Flip-Flop The D input goes directly into the S input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock pulse. If it is, the flip-flop is switched to the set state (unless it was already set). If it is, the flip-flop switches to the clear state. 5 October 26 Asanga Ratnaweera, Department of 3 Flop-Flops JK Flip-Flop A JK flip-flop is a refinement of the SR flipflop in that the indeterminate state of the SR type is defined in the JK type. 5 October 26 Asanga Ratnaweera, Department of 32 6

17 ME 55 Mechatronics /5/26 Flop-Flops T Flip-Flop The T flip-flop is a single input version of the JK flip-flop. The output of the T flip-flop "toggles" with each clock pulse. 5 October 26 Asanga Ratnaweera, Department of 33 Flop-Flops Triggering of Flip-flops The clock pulse goes through two signal transitions: from to and the return from to. The positive transition is defined as the positive edge and the negative transition as the negative edge. These flipflops are termed edge-triggered flip-flops 5 October 26 Asanga Ratnaweera, Department of 34 7

flip-flops Level-triggered flip-flops respond to their inputs while the clock signal is at a high level and retain

18 ME 55 Mechatronics /5/26 Triggering of Flip-flops Edge-triggered flip-flops Ex: Positive edge triggered SR flip-flop Truth table Timing diagram 5 October 26 Asanga Ratnaweera, Department of 35 Triggering of Flip-flops Level-triggered flip-flops Level-triggered flip-flops respond to their inputs while the clock signal is at a high level and retain their output values after the level change Timing diagram Truth table 5 October 26 Asanga Ratnaweera, Department of 36 8

19 ME 55 Mechatronics /5/26 Clock pulse generation 555 timer 5 October 26 Asanga Ratnaweera, Department of 37 Clock pulse generation 5 October 26 Asanga Ratnaweera, Department of 38 9

20 ME 55 Mechatronics /5/26 Clock pulse generation 555 timer T =.7 (R + 2R2) C f =.4 (R + 2R2) C T = time period in seconds (s) f = frequency in hertz (Hz) R = resistance in ohms ( ) R2 = resistance in ohms ( ) C = capacitance in farads (F) The time period can be split into two parts: T = Tm + Ts Mark time (output high): Tm =.7 (R + R2) C Space time (output low): Ts =.7 R2 C 5 October 26 Asanga Ratnaweera, Department of 39 Clock pulse generation 555 timer 5 October 26 Asanga Ratnaweera, Department of 4 2

21 ME 55 Mechatronics /5/26 Flop-Flop ICs Flip-flops are commercially available as IC packages 5 October 26 Asanga Ratnaweera, Department of 4 State Machine A state machine is a device that stores the status of something at a given time and can operate on input to change the status and/or cause an action or output to take place for any given change. Ex: computer. 5 October 26 Asanga Ratnaweera, Department of 42 2

22 ME 55 Mechatronics /5/26 State Machine Ex: Design of a modulo-4 up-down counter State transition diagram 5 October 26 Asanga Ratnaweera, Department of 43 Design of an up-down counter Ex: Design of a modulo-4 up-down counter State Table Input x Current state / q 5 October 26 Asanga Ratnaweera, Department of Current state / q 2 Next state / Q Next state / Q

2 d d d d 5 October 26 Asanga Ratnaweera, Department of 45 Design of an up-down

23 ME 55 Mechatronics /5/26 Design of an up-down counter Ex: Design of a modulo-4 up-down counter State Transition Table with SR flip flops x q q 2 Q Q 2 S R S 2 R 2 d d d d 5 October 26 Asanga Ratnaweera, Department of 45 Design of an up-down counter Use K-maps for simplification 5 October 26 Asanga Ratnaweera, Department of 46 23

24 ME 55 Mechatronics /5/26 Design of an up-down counter Logic circuit 5 October 26 Asanga Ratnaweera, Department of 47 Applications of Digital Electronics Binary counters 5 October 26 Asanga Ratnaweera, Department of 48 24

Ex: LS 749 IC Output sequence 5 October 26 Asanga Ratnaweera, Department of 49 Applications of Digital Electronics

25 ME 55 Mechatronics /5/26 Applications of Digital Electronics Decade counters Use to perform binary counting A negative edge-triggered counter and the output is binary coded decimal (BCD) consists of four bits. Ex: LS 749 IC Output sequence 5 October 26 Asanga Ratnaweera, Department of 49 Applications of Digital Electronics Decade counters Timing diagram Remember: this is a negative edge-triggered counter 5 October 26 Asanga Ratnaweera, Department of 5 25

Output D can be used as the clock input for the second decade counter (749) Cascading two together in order to raise the range for

26 ME 55 Mechatronics /5/26 Applications of Digital Electronics Decade counters BCD counters can be cascaded in order to count in powers of. Output D can be used as the clock input for the second decade counter (749) Cascading two together in order to raise the range for counting from to October 26 Asanga Ratnaweera, Department of 5 Applications of Digital Electronics Decade counters Note:IC 7447 negative logic seven segment LED code (LED Switches ON when output is low) 5 October 26 Asanga Ratnaweera, Department of 52 26

27 ME 55 Mechatronics /5/26 Applications of Digital Electronics Data registers 5 October 26 Asanga Ratnaweera, Department of 53 Applications of Digital Electronics Serial & Parallel Interfaces 5 October 26 Asanga Ratnaweera, Department of 54 27

28 ME 55 Mechatronics /5/26 Applications of Digital Electronics Serial & Parallel Interfaces 5 October 26 Asanga Ratnaweera, Department of 55 28

TYPICAL QUESTIONS & ANSWERS

DIGITALS ELECTRONICS TYPICAL QUESTIONS & ANSWERS OBJECTIVE TYPE QUESTIONS Each Question carries 2 marks. Choose correct or the best alternative in the following: Q.1 The NAND gate output will be low if