Topics of Discussion

Transcription

1 Digital Circuits II VHDL for Digital System Design Practical Considerations References: 1) Text Book: Digital Electronics, 9 th editon, by William Kleitz, published by Pearson Spring 2015 Paul I-Hai Lin, Professor of ECET Dept. of Computer, Electrical and Information Technology Indiana University-Purdue University Fort Wayne Prof. Paul Lin 1 Topics of Discussion Flip-Flop Time Parameters Automatic Reset Schmitt Trigger ICs Switch Debouncing Sizing Pull-up Resistors Practical Input and Output Considearions Prof. Paul Lin 2 1

2 Flip-Flop Time Parameters Race condition: When inputs to a triggered device are changing at the same time that the active trigger edge of the input clock is making its transition AC Setup Requirements Clock pulse width (High), Clock pulse width (Low), Reset pulse width Setup time, Hold time Setup time: The length of time before the active clock edge that the flip-flop looks back to determine the levels to use at the inputs Hold time: The length of time after the active clock edge Active clock edge Propagation delay The delay from input to output Prof. Paul Lin 3 Flip-Flop Time Parameters Figure 11.1 A possible race condition on a J-K flip-flop creates an undetermined result at Q Prof. Paul Lin 4 2

3 Flip-Flop Time Parameters Figure 11.2 Setup time waveform specifications for a 74LS76 Prof. Paul Lin 5 Flip-Flop Time Parameters Figure 11.3 Setup and hold parameters for a 74LS76 Prof. Paul Lin 6 3

4 Flip-Flop Time Parameters Figure 11.8 Propagation delay for the asynchronous input to Q output for a 74LS76 Prof. Paul Lin 7 Flip-Flop Time Parameters (Modifications) Use Logic gate to obtain extra time delay Delay gate (ns): 5, 10, 15, 20 nsc Prof. Paul Lin 8 4

5 RC Circuit (Time Delay) Power-up Reset Automatic Reset Prof. Paul Lin 9 Schmitt Trigger ICs Schmitt trigger: transform slow changing waveforms into sharply defined, jitter-free output signals. Positive feedback; Hysteresis effect Prof. Paul Lin 10 5

6 Schmitt Trigger ICs Figure Transfer function for a 7414 Schmitt trigger inverter Hysteresis effect Prof. Paul Lin 11 Switch Debouncing Switch bounce effect Debouncing Circuits JK Flip-flops (Figure 11.37) RC time delay circuit RS flip flop (NAND) Prof. Paul Lin 12 6

7 Switch Debouncing Debouncing Circuits Bouncing effect (Figure 11.38) Prof. Paul Lin 13 Switch Debouncing RC time delay circuit (Figure 11.39) Prof. Paul Lin 14 7

8 Switch Debouncing RS flip flop (NAND) Figure Prof. Paul Lin 15 Sizing Pull-up Resistors Figure Complete 5V, 1 A TTL power supply Prof. Paul Lin 16 8

9 Sizing Pull-up Resistors Figure Accurate 60 Hz, TTL-level clock pulse generator Prof. Paul Lin 17 Sizing Pull-up Resistors Figure Driving an LED Prof. Paul Lin 18 9

10 Sizing Pull-up Resistors Figure Phototransistor used as an input to a latching alarm system Prof. Paul Lin 19 Sizing Pull-up Resistors Figure A opto-coupler provides isolation in a level-shifting application Prof. Paul Lin 20 10

11 Sizing Pull-up Resistors Figure Optical interrupter switch Prof. Paul Lin 21 Sizing Pull-up Resistors Figure Using the optical interrupter switch to encode motor shaft position Prof. Paul Lin 22 11

12 Sizing Pull-up Resistors Figure Connecting the optical interrupter switch in a digital system to count events Prof. Paul Lin 23 Sizing Pull-up Resistors Figure Using a power MOSFET to interface logic to high-power ac circuit Prof. Paul Lin 24 12

13 Sizing Pull-up Resistors Figure Using an LM339 analog comparator to interface to digital logic Prof. Paul Lin 25 Sizing Pull-up Resistors Figure Internal circuitry of a Hall-effect switch IC Prof. Paul Lin 26 13

14 Sizing Pull-up Resistors Figure The flux line from a south magnet triggering a Hall-effect switch IC Prof. Paul Lin 27 Sizing Pull-up Resistors Figure A magnetic rotor triggering a Hall-effect switch IC Prof. Paul Lin 28 14

15 Sizing Pull-up Resistors Figure Multiple inputs and outputs connected to a CPLD or FPGA Prof. Paul Lin 29 Summary & Conclusion Prof. Paul Lin 30 15