Feedback Sequential Circuits

Transcription

1 Feedback Sequential Circuits sequential circuit output depends on 1. current inputs 2. past sequence of inputs current state feedback sequential circuit uses ordinary gates and feedback loops to create memory

2 Simplest Memory Element strictly digital analysis two stable states Vout1, high or low no inputs, no control from an analog perspective three stable states

3 Metastability From a practical perspective: may happen at power up marginal triggering conditions asynchronous inputs do not meet flip-flop setup and hold times especially severe in high speed systems clock period too short hold may require more that one clock period

4 Latch vs Flip-flop latch sequential device that changes outputs when inputs change (no clock) level sensitive flip-flop sequential device that changes outputs at times determined by clocking signal edge sensitive

5 SR Latch (set-reset latch) if S=R=0 S=0;R=1 S R Q Q_N 0 0 Q t-1 Q_N t S=1;R=0 S=R=1

6 SR Latch Timing Parameters propagation delay, t plh, t phl time for transition on input to produce a transition on output minimum pulse width (shaded), t pw if pulse < minimum, output is metastable

7 SR Latch in VHDL library IEEE; use IEEE.std_logic_1164.all; entity srlatch is port ( R, S : in std_logic; Q, QN : buffer std_logic); end entity srlatch; architecture srlatch_a of srlatch is begin Q <= R nor QN; QN <= S nor Q; end architecture srlatch_a;

8 Quartus (older versions) what you used to see functional timing

9 QSim what you now see functional timing

10 Quartus what happens? 1. Functional Start Analysis & Synthesis Simulate via Qsim 2. Functional + Design Assistant Start Analysis & Synthesis Processing Start Start Design Assistant Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. 3. Timing Start Compilation Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational loops as latches. Simulate via QSim

11 D latch (data latch, transparent latch, dlatch) C D Q Q_N 0 -- Q t-1 Q_N t SR latch constrained so that S=R eliminates simultaneous assertion problem C enable (level triggered)

12 D Latch Timing Parameters propagation delay, t plh, t phl setup time, t setup (t s ); hold time, t hold (t h ) keep input stable before and after clock transition if setup and hold not met, output unpredictable and may become metastable

13 D Flip-flop (positive edge trigger) clk = 0, master slave D CLK Q Q_N Q t-1 Q_N t-1 1 Q t-1 Q_N t-1 clk = 1, master slave BUT clk => means that there will be a setup and hold time requirement

14 D Flip-flop VHDL as dataflow library IEEE; use IEEE.std_logic_1164.all; entity dlatchedge is port ( D, clk : in std_logic; Q, QN : buffer std_logic); end entity dlatchedge; architecture dlatche_a of dlatchedge is signal QM, QMN : std_logic; begin QM <= (D nand not clk) nand QMN; QMN <= (not D nand not clk) nand QM; Q <= (QM nand not(not clk)) nand QN; QN <= (not QM nand not(not clk)) nand Q; end architecture dlatche_a; A1L5_p1_out = A1L5 & clk; A1L5_p2_out =!clk & D; A1L5_p3_out = A1L5 & D; A1L5_or_out = A1L5_p1_out # A1L5_p2_out # A1L5_p3_out; A1L5 = A1L5_or_out; A1L8_p1_out =!A1L8 &!clk; A1L8_p2_out = clk &!A1L5; A1L8_p3_out =!A1L8 &!A1L5; A1L8_or_out = A1L8_p1_out # A1L8_p2_out # A1L8_p3_out; A1L8 =!(A1L8_or_out); A1L7_p1_out =!A1L5 & clk; A1L7_or_out = A1L7_p1_out #!A1L8; A1L7 = A1L7_or_out; D = INPUT(); clk = INPUT(); QM = OUTPUT(A1L5); Q = OUTPUT(A1L8); QN = OUTPUT(A1L7);

15 D Flip-flop if clock library IEEE; use IEEE.std_logic_1164.all; entity dlatchedge2 is port ( D, clk : in std_logic; Q : out std_logic); end entity dlatchedge2; architecture dlatche2_a of dlatchedge2 is begin process (clk) begin if clk'event and clk='1' then Q <= D; end if; end process; end architecture dlatche2_a;

16 D Flip-flop if clock library IEEE; use IEEE.std_logic_1164.all; entity dlatchedge2 is port ( D, clk : in std_logic; Q : out std_logic); end entity dlatchedge2; architecture dlatche2_a of dlatchedge2 is begin process (clk) begin if clk'event and clk='1' then Q <= D; end if; end process; end architecture dlatche2_a; A1L4Q_or_out = D; A1L4Q_reg_input = A1L4Q_or_out; A1L4Q = DFFE(A1L4Q_reg_input, GLOBAL(clk),,, ); --D is D at PIN_41 --operation mode is input D = INPUT(); --clk is clk at PIN_43 --operation mode is input clk = INPUT(); --Q is Q at PIN_12 --operation mode is output Q = OUTPUT(A1L4Q);

17 D Flip-flop wait until library IEEE; use IEEE.std_logic_1164.all; entity dlatchedge3 is port ( D, clk : in std_logic; Q : out std_logic); end entity dlatchedge3; architecture dlatche3_a of dlatchedge3 is begin process begin wait until clk'event and clk='1'; Q <= D; end process; end architecture dlatche3_a;

18 Implied Memory library IEEE; use IEEE.std_logic_1164.all; entity implied is port ( A, B : IN std_logic; AeqB : OUT std_logic); end entity implied; - when executed, AeqB is always 1, why? architecture behav of implied is begin process (A, B) begin if A = B then AeqB <= '1'; end if; end process; end architecture behav;

19 Implied Memory Warning (10631): VHDL Process Statement warning at implied.vhd(11): inferring latch(es) for signal or variable "AeqB", which holds its previous value in one or more paths through the process

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