Theory Lecture Day Topic Practical Day. Week. number systems and their inter-conversion Decimal, Binary. 3rd. 1st. 1st

Size: px
Start display at page:

Download "Theory Lecture Day Topic Practical Day. Week. number systems and their inter-conversion Decimal, Binary. 3rd. 1st. 1st"

Transcription

1 Lesson Plan Name of the Faculty : Priyanka Nain Discipline: Electronics & Communication Engg. Semester:5th Subject:DEMP Lesson Plan Duration: 15 Weeks Work Load(Lecture/Practical) per week (In Hours): Lectures-05, Practicals-03 Week 1st Theory Lecture Day Topic Practical Day 1st 2nd 3rd number systems and their inter-conversion Decimal, Binary 1st 4th number systems and their inter-conversion Octal, Hexadecimal 5th practice of number system 6th BCD and ASCII code 2nd 7th Binary addition, subtraction and multiplication 2nd 8th Hexadecimal addition, subtraction and multiplication 9th 10th 11th 12th 1 s complement methods of addition/subtraction 2 s complement methods of addition/subtraction practice Definition, symbol and truth tables for inverter, OR, AND, gates 3rd 13th Definition, symbol and truth tables for NAND, NOR,X-OR exclusive NOR gates 3rd 14th 15th 16th Universal gates Boolean Relations and their applications Boolean Relations and their applications

2 4th 5th 6th 7th 8th 17th DeMorgan s Theorems 18th K-Map upto four variables 19th K-Map upto four variables 20th K-Map upto four variables 21st K-Map upto four variables 22nd practice 23rd adders 24th Half adder 25th Full adder 26th 27th Test 28th Encoder 29th Decoder 30th Multiplexer 31st Demultiplexer 32nd Display Devices (LED, LCD and 7-segment display 33rd flip flop 34th J-K Flip-Flop 35th R-S Flip-Flop 36th D-Type Flip-Flop 37th T-Type Flip-Flop 38th Applications of Flip-Flops 39th Introduction to Shift Registers 4th 5th 6th 7th 8th 40th Introduction to Shift Registers 41st 42nd 43rd Introduction to Counters Introduction to Counters Introduction to converters 9th 44th A/D converter (Counter ramp, 9th 10th 45th 46th 47th 48th A/D converter (successive approximation method of A/D Conversion) D/A converters (Binary weighted) D/A converters (R-2R D/A Converter) Specification of A/D converters 10th 49th Specification of D/A converters 50th 51st 52nd Test

3 11th 53rd Semi-conductor Memories 11th 54th 55th Types, merits, demerits, and applications Features of th Study of 8085 architecture 12th 13th 57th 58th 59th 60th 61st 62nd 63rd 64th pin configuration, bus organisation, registers flags interrupts instruction format Instruction set of 8085 addressing modes Writing some simple assembly language programmes stacks and sub-routines 12th 13th 65th Interfacing and data transfer between peripheral, I/O and 14th 15th 66th 67th 68th 69th 70th 71st 72nd 73rd 74th 75th , Introduction of 16-bit, 32-bit advantages over 8-bit Test 14th 15th

4 Practical Topic Introduction Verification and interpretation of truth table for AND, OR, NOT, NAND, NOR, X-OR gates Construction of Half Adder/Full Adder using gates

5 Construction of Half Adder/Full Adder using gates revision To verify the truth table for R-S and JK flipflop Construction and testing of any counter Verification of operation of a 8-bit D/A Converter Verification of operation of a 8-bit D/A Converter Writing assembly language programme using numemoanics and test them on Kit

6 Writing assembly language programme using numemoanics and test them on Kit Writing assembly language programme using numemoanics and test them on Kit Assembly language programming for different applications on 8051 microcontroller Viva Viva

Minnesota State College Southeast

Minnesota State College Southeast ELEC 2211: Digital Electronics II A. COURSE DESCRIPTION Credits: 4 Lecture Hours/Week: 2 Lab Hours/Week: 4 OJT Hours/Week: *.* Prerequisites: None Corequisites: None MnTC Goals: None Minnesota State College

More information

R13 SET - 1 '' ''' '' ' '''' Code No: RT21053

R13 SET - 1 '' ''' '' ' '''' Code No: RT21053 SET - 1 1. a) What are the characteristics of 2 s complement numbers? b) State the purpose of reducing the switching functions to minimal form. c) Define half adder. d) What are the basic operations in

More information

R13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A

R13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A SET - 1 Note: Question Paper consists of two parts (Part-A and Part-B) Answer ALL the question in Part-A Answer any THREE Questions from Part-B a) What are the characteristics of 2 s complement numbers?

More information

Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24

Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 2065 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 Time: 3 hours. Candidates are required to give their answers in their own words as for as practicable. Attempt any TWO questions:

More information

TIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic

TIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic COURSE TITLE : DIGITAL INSTRUMENTS PRINCIPLE COURSE CODE : 3075 COURSE CATEGORY : B PERIODS/WEEK : 4 PERIODS/SEMESTER : 72 CREDITS : 4 TIME SCHEDULE MODULE TOPICS PERIODS 1 Number system & Boolean algebra

More information

1. Convert the decimal number to binary, octal, and hexadecimal.

1. Convert the decimal number to binary, octal, and hexadecimal. 1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay

More information

Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology

Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology Course Title: Digital Logic Full Marks: 60 + 0 + 0 Course No.: CSC Pass Marks:

More information

TRAINING KITS ON DIGITAL ELECTRONIC EXPERIMENTS. Verify Truth table for TTL IC s AND, NOT, & NAND GATES

TRAINING KITS ON DIGITAL ELECTRONIC EXPERIMENTS. Verify Truth table for TTL IC s AND, NOT, & NAND GATES TRAINING KITS ON DIGITAL ELECTRONIC EXPERIMENTS CEE 2800 Basic Logic Gates using TTL IC's (7 in 1) To verify the truth table For TTL AND, OR. NOT, NAND,NOR, EX-OR, & EX-NOR Gates. Instrument comprises

More information

1. True/False Questions (10 x 1p each = 10p) (a) I forgot to write down my name and student ID number.

1. True/False Questions (10 x 1p each = 10p) (a) I forgot to write down my name and student ID number. CprE 281: Digital Logic Midterm 2: Friday Oct 30, 2015 Student Name: Student ID Number: Lab Section: Mon 9-12(N) Mon 12-3(P) Mon 5-8(R) Tue 11-2(U) (circle one) Tue 2-5(M) Wed 8-11(J) Wed 6-9(Y) Thur 11-2(Q)

More information

EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true.

EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true. EXPERIMENT: 1 DATE: VERIFICATION OF BASIC LOGIC GATES AIM: To verify the truth tables of Basic Logic Gates NOT, OR, AND, NAND, NOR, Ex-OR and Ex-NOR. APPARATUS: mention the required IC numbers, Connecting

More information

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS)

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) 1. Convert Binary number (111101100) 2 to Octal equivalent. 2. Convert Binary (1101100010011011) 2 to Hexadecimal equivalent. 3. Simplify the following Boolean function

More information

MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM

MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM MDETS UCTECH's Modular Digital Electronics Training System is a modular course covering the fundamentals, concepts, theory and applications of digital electronics.

More information

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational

More information

1 Hour Sample Test Papers: Sample Test Paper 1. Roll No.

1 Hour Sample Test Papers: Sample Test Paper 1. Roll No. 6.1.2 Sample Test Papers: Sample Test Paper 1 Roll No. Institute Name: Course Code: EJ/EN/ET/EX/EV/IC/IE/IS/MU/DE/ED/ET/IU Subject: Principles of Digital Techniques Marks: 25 1 Hour 1. All questions are

More information

DIGITAL FUNDAMENTALS

DIGITAL FUNDAMENTALS DIGITAL FUNDAMENTALS A SYSTEMS APPROACH THOMAS L. FLOYD PEARSON Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal

More information

4.S-[F] SU-02 June All Syllabus Science Faculty B.Sc. II Yr. Instrumentation Practice [Sem.III & IV] S.Lot

4.S-[F] SU-02 June All Syllabus Science Faculty B.Sc. II Yr. Instrumentation Practice [Sem.III & IV] S.Lot [Sem.III & IV] S.Lot. - 1 - [Sem.III & IV] S.Lot. - 2 - [Sem.III & IV] S.Lot. - 3 - Syllabus B.Sc. ( Instrumentation Practice ) Second Year ( Third and Forth Semester ) ( Effective from June 2014 ) [Sem.III

More information

MODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1

MODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1 DAY MODU LE TOPIC QUESTIONS Day 1 Day 2 Day 3 Day 4 I Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation Phase Shift Wein Bridge oscillators.

More information

PURBANCHAL UNIVERSITY

PURBANCHAL UNIVERSITY [c] Implement a full adder circuit with a decoder and two OR gates. [4] III SEMESTER FINAL EXAMINATION-2006 Q. [4] [a] What is flip flop? Explain flip flop operating characteristics. [6] [b] Design and

More information

1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.

1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1. [Question 1 is compulsory] 1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. Figure 1.1 b) Minimize the following Boolean functions:

More information

Course Plan. Course Articulation Matrix: Mapping of Course Outcomes (COs) with Program Outcomes (POs) PSO-1 PSO-2

Course Plan. Course Articulation Matrix: Mapping of Course Outcomes (COs) with Program Outcomes (POs) PSO-1 PSO-2 Course Plan Semester: 4 - Semester Year: 2019 Course Title: DIGITAL ELECTRONICS Course Code: EC106 Semester End Examination: 70 Continuous Internal Evaluation: 30 Lesson Plan Author: Ms. CH SRIDEVI Last

More information

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the

More information

ME 515 Mechatronics. Introduction to Digital Electronics

ME 515 Mechatronics. Introduction to Digital Electronics ME 55 Mechatronics /5/26 ME 55 Mechatronics Digital Electronics Asanga Ratnaweera Department of Faculty of Engineering University of Peradeniya Tel: 8239 (3627) Email: asangar@pdn.ac.lk Introduction to

More information

Semester III. Subject Name: Digital Electronics. Subject Code: 09CT0301. Diploma Branches in which this subject is offered: Computer Engineering

Semester III. Subject Name: Digital Electronics. Subject Code: 09CT0301. Diploma Branches in which this subject is offered: Computer Engineering Semester III Subject Name: Digital Electronics Subject Code: 09CT0301 Diploma Branches in which this subject is offered: Objective: The subject aims to prepare the students, To understand the basic of

More information

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7).

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7). VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603203 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Academic Year: 2015-16 BANK - EVEN SEMESTER UNIT I PART-A 1 Find the octal equivalent of hexadecimal

More information

[2 credit course- 3 hours per week]

[2 credit course- 3 hours per week] Syllabus of Applied Electronics for F Y B Sc Semester- 1 (With effect from June 2012) PAPER I: Components and Devices [2 credit course- 3 hours per week] Unit- I : CIRCUIT THEORY [10 Hrs] Introduction;

More information

North Shore Community College

North Shore Community College North Shore Community College Course Number: IEL217 Section: MAL Course Name: Digital Electronics 1 Semester: Credit: 4 Hours: Three hours of Lecture, Two hours Laboratory per week Thursdays 8:00am (See

More information

TYPICAL QUESTIONS & ANSWERS

TYPICAL QUESTIONS & ANSWERS DIGITALS ELECTRONICS TYPICAL QUESTIONS & ANSWERS OBJECTIVE TYPE QUESTIONS Each Question carries 2 marks. Choose correct or the best alternative in the following: Q.1 The NAND gate output will be low if

More information

Nirma University Institute of Technology. Electronics and Communication Engineering Department. Course Policy

Nirma University Institute of Technology. Electronics and Communication Engineering Department. Course Policy Nirma University Institute of Technology Electronics and Communication Engineering Department Course Policy B. Tech Semester - III Academic Year: 2017 Course Code & Name : Credit Details : L T P C 4 2

More information

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION Spring 2012 Question No: 1 ( Marks: 1 ) - Please choose one A SOP expression is equal to 1

More information

SEMESTER ONE EXAMINATIONS 2002

SEMESTER ONE EXAMINATIONS 2002 SEMESTER ONE EXAMINATIONS 2002 EE101 Digital Electronics Solutions Question 1. An assembly line has 3 failsafe sensors and 1 emergency shutdown switch. The Line should keep moving unless any of the following

More information

Note 5. Digital Electronic Devices

Note 5. Digital Electronic Devices Note 5 Digital Electronic Devices Department of Mechanical Engineering, University Of Saskatchewan, 57 Campus Drive, Saskatoon, SK S7N 5A9, Canada 1 1. Binary and Hexadecimal Numbers Digital systems perform

More information

Find the equivalent decimal value for the given value Other number system to decimal ( Sample)

Find the equivalent decimal value for the given value Other number system to decimal ( Sample) VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI 65 009 Department of Information Technology Model Exam-II-Question bank PART A (Answer for all Questions) (8 X = 6) K CO Marks Find the equivalent

More information

Experiment (6) 2- to 4 Decoder. Figure 8.1 Block Diagram of 2-to-4 Decoder 0 X X

Experiment (6) 2- to 4 Decoder. Figure 8.1 Block Diagram of 2-to-4 Decoder 0 X X 8. Objectives : Experiment (6) Decoders / Encoders To study the basic operation and design of both decoder and encoder circuits. To describe the concept of active low and active-high logic signals. To

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ T Flip-Flops & JK Flip-Flops CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander

More information

SETH JAI PARKASH POLYTECHNIC, DAMLA COMPUTER ENGINEERING AIDED-3 RD SEMESTER

SETH JAI PARKASH POLYTECHNIC, DAMLA COMPUTER ENGINEERING AIDED-3 RD SEMESTER LESSON PLAN Sub: Multimedia Sanjeev Sehgal WEE K THEORY LECTUR E DAY TOPIC (Including assignment/ test) PRACTICAL PRACTICA L DAY TOPIC Ist 1st Introduction to multimedia Ist Installation of various MA

More information

Microprocessor Design

Microprocessor Design Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004 To my wife and children Windy, Jonathan and Michelle Contents 1. Designing a Microprocessor... 2 1.1 Overview

More information

Contents Circuits... 1

Contents Circuits... 1 Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...

More information

Dev Bhoomi Institute Of Technology PRACTICAL INSTRUCTION SHEET EXPERIMENT NO. ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE : PAGE:

Dev Bhoomi Institute Of Technology PRACTICAL INSTRUCTION SHEET EXPERIMENT NO. ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE : PAGE: Dev Bhoomi Institute Of Technology LABORATORY MANUAL PRACTICAL INSTRUCTION SHEET EXPERIMENT NO. ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE : PAGE: LABORATORY Name & Code: Digital Electronics SEMESTER:

More information

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops Objective Construct a two-bit binary decoder. Study multiplexers (MUX) and demultiplexers (DEMUX). Construct an RS flip-flop from discrete gates.

More information

WINTER 15 EXAMINATION Model Answer

WINTER 15 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

Lecture 12. Amirali Baniasadi

Lecture 12. Amirali Baniasadi CENG 24 Digital Design Lecture 2 Amirali Baniasadi amirali@ece.uvic.ca This Lecture Chapter 6: Registers and Counters 2 Registers Sequential circuits are classified based in their function, e.g., registers.

More information

MODULE 3. Combinational & Sequential logic

MODULE 3. Combinational & Sequential logic MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational

More information

BCN1043. By Dr. Mritha Ramalingam. Faculty of Computer Systems & Software Engineering

BCN1043. By Dr. Mritha Ramalingam. Faculty of Computer Systems & Software Engineering BCN1043 By Dr. Mritha Ramalingam Faculty of Computer Systems & Software Engineering mritha@ump.edu.my http://ocw.ump.edu.my/ authors Dr. Mohd Nizam Mohmad Kahar (mnizam@ump.edu.my) Jamaludin Sallim (jamal@ump.edu.my)

More information

The word digital implies information in computers is represented by variables that take a limited number of discrete values.

The word digital implies information in computers is represented by variables that take a limited number of discrete values. Class Overview Cover hardware operation of digital computers. First, consider the various digital components used in the organization and design. Second, go through the necessary steps to design a basic

More information

Subject : EE6301 DIGITAL LOGIC CIRCUITS

Subject : EE6301 DIGITAL LOGIC CIRCUITS QUESTION BANK Programme : BE Subject : Semester / Branch : III/EEE UNIT 1 NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES Review of number systems, binary codes, error detection and correction codes (Parity

More information

AIM: To study and verify the truth table of logic gates

AIM: To study and verify the truth table of logic gates EXPERIMENT: 1- LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various Logic gates and their output. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main

More information

Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics

Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and

More information

Department of Computer Science and Engineering Question Bank- Even Semester:

Department of Computer Science and Engineering Question Bank- Even Semester: Department of Computer Science and Engineering Question Bank- Even Semester: 2014-2015 CS6201& DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common to IT & CSE, Regulation 2013) UNIT-I 1. Convert the following

More information

EE Chip list. Page 1

EE Chip list. Page 1 Chip # Description 7400 Quadruple 2-Input Positive NANDS 7401 Quadruple 2-Input Positive NAND with Open-Collector Outputs 7402 Quadruple 2-input Positive NOR 7403 Quadruple 2-Intput Positive NAND with

More information

Logic Design Viva Question Bank Compiled By Channveer Patil

Logic Design Viva Question Bank Compiled By Channveer Patil Logic Design Viva Question Bank Compiled By Channveer Patil Title of the Practical: Verify the truth table of logic gates AND, OR, NOT, NAND and NOR gates/ Design Basic Gates Using NAND/NOR gates. Q.1

More information

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET LABORATORY MANUAL EXPERIMENT NO. 1 ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE :

More information

I B.SC (INFORMATION TECHNOLOGY) [ ] Semester II CORE : DIGITAL COMPUTER FUNDAMENTALS - 212B Multiple Choice Questions.

I B.SC (INFORMATION TECHNOLOGY) [ ] Semester II CORE : DIGITAL COMPUTER FUNDAMENTALS - 212B Multiple Choice Questions. Dr.G.R.Damodaran College of Science (Autonomous, affiliated to the Bharathiar University, recognized by the UGC)Re-accredited at the 'A' Grade Level by the NAAC and ISO 9001:2008 Certified CRISL rated

More information

AM AM AM AM PM PM PM

AM AM AM AM PM PM PM FACULTY OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING COURSE PLAN Course Code : CS0003 Course Title : DIGITAL COMPUTER FUNDAMENTALS Semester : III Course Time : Jun 204 to

More information

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science

Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Project Resources Project resources are allocated on a per

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

QUICK GUIDE COMPUTER LOGICAL ORGANIZATION - OVERVIEW

QUICK GUIDE COMPUTER LOGICAL ORGANIZATION - OVERVIEW QUICK GUIDE http://www.tutorialspoint.com/computer_logical_organization/computer_logical_organization_quick_guide.htm COMPUTER LOGICAL ORGANIZATION - OVERVIEW Copyright tutorialspoint.com In the modern

More information

List of the CMOS 4000 series Dual tri-input NOR Gate and Inverter Quad 2-input NOR gate Dual 4-input NOR gate

List of the CMOS 4000 series Dual tri-input NOR Gate and Inverter Quad 2-input NOR gate Dual 4-input NOR gate List of the CMOS 4000 series 4000 - Dual tri-input NOR Gate and Inverter 4001 - Quad 2-input NOR gate 4002 - Dual 4-input NOR gate 4006-18 stage Shift register 4007 - Dual Complementary Pair Plus Inverter

More information

REPEAT EXAMINATIONS 2002

REPEAT EXAMINATIONS 2002 REPEAT EXAMINATIONS 2002 EE101 Digital Electronics Solutions Question 1. An engine has 4 fail-safe sensors. The engine should keep running unless any of the following conditions arise: o If sensor 2 is

More information

7454 4x2 AND/NOR x4 AND/NOR x2 Ex-NOR/Ex-OR x NAND 2x INVERTER X8 OR/NOR 14. EXPANDER x4 AND EXPANDER 14

7454 4x2 AND/NOR x4 AND/NOR x2 Ex-NOR/Ex-OR x NAND 2x INVERTER X8 OR/NOR 14. EXPANDER x4 AND EXPANDER 14 NAND GATES 7400 4x2-Input 14 7401 4x2-Input 14 7403 4x2-Input 14 7410 3x3-Input 14 7412 3x3-Input 14 7420 2x4-Input 14 7422 2x4-Input 14 7426 4x2-Input 15V 14 7430 1x8-Input 14 74133 1x13-Input 16 74134

More information

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date:

More information

Electrical and Telecommunications Engineering Technology_TCET3122/TC520. NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York

Electrical and Telecommunications Engineering Technology_TCET3122/TC520. NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York DEPARTMENT: SUBJECT CODE AND TITLE: COURSE DESCRIPTION: REQUIRED: Electrical and Telecommunications Engineering Technology TCET 3122/TC

More information

Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours

Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours Aim To investigate the basic digital circuit building blocks constructed from combinatorial logic or dedicated Integrated

More information

UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers.

UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers. UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers. Digital computer is a digital system that performs various computational tasks. The word DIGITAL

More information

Chapter 5 Sequential Circuits

Chapter 5 Sequential Circuits Logic and Computer Design Fundamentals Chapter 5 Sequential Circuits Part 2 Sequential Circuit Design Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)

More information

Digital Circuits ECS 371

Digital Circuits ECS 371 Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 0 Office Hours: BKD 360-7 Monday 9:00-0:30, :30-3:30 Tuesday 0:30-:30 Announcement HW4 posted on the course web site Chapter 5:

More information

DIGITAL ELECTRONICS MCQs

DIGITAL ELECTRONICS MCQs DIGITAL ELECTRONICS MCQs 1. A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8

More information

A Matlab-Based Teaching Tool for Digital Logic

A Matlab-Based Teaching Tool for Digital Logic Session 1520 A Matlab-Based Teaching Tool for Digital Logic Clark T. Merkel, Mechanical Engineering Rose-Hulman Institute of Technology Abstract: This paper introduces, shows, and makes available a tool

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev

More information

HS Digital Electronics Pre-Engineering

HS Digital Electronics Pre-Engineering Course This course covers fundamentals of analog and digital electronics. Students learn about the different number systems used in the design of digital circuitry. They design circuits to solve open-ended

More information

Operating Manual Ver.1.1

Operating Manual Ver.1.1 Keyboard Encoder Operating Manual Ver.1.1 An ISO 9001 : 2000 company 94-101, Electronic Complex Pardesipura, Indore- 452010, India Tel : 91-731- 2570301/02, 4211100 Fax: 91-731- 2555643 e mail : info@scientech.bz

More information

NORTHWESTERN UNIVERSITY TECHNOLOGICAL INSTITUTE

NORTHWESTERN UNIVERSITY TECHNOLOGICAL INSTITUTE NORTHWESTERN UNIVERSITY TECHNOLOGICL INSTITUTE ECE 270 Experiment #8 DIGITL CIRCUITS Prelab 1. Draw the truth table for the S-R Flip-Flop as shown in the textbook. Draw the truth table for Figure 7. 2.

More information

Chapter 9 MSI Logic Circuits

Chapter 9 MSI Logic Circuits Chapter 9 MSI Logic Circuits Chapter 9 Objectives Selected areas covered in this chapter: Analyzing/using decoders & encoders in circuits. Advantages and disadvantages of LEDs and LCDs. Observation/analysis

More information

VU Mobile Powered by S NO Group

VU Mobile Powered by S NO Group Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register.

More information

Chapter Contents. Appendix A: Digital Logic. Some Definitions

Chapter Contents. Appendix A: Digital Logic. Some Definitions A- Appendix A - Digital Logic A-2 Appendix A - Digital Logic Chapter Contents Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A. Introduction A.2 Combinational

More information

FUNCTIONS OF COMBINATIONAL LOGIC

FUNCTIONS OF COMBINATIONAL LOGIC FUNCTIONS OF COMBINATIONAL LOGIC Agenda Adders Comparators Decoders Encoders Multiplexers Demultiplexers Adders Basic Adders Adders are important in computers other types of digital systems in which numerical

More information

UNIT 1 NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES 1. Briefly explain the stream lined method of converting binary to decimal number with example. 2. Give the Gray code for the binary number (111) 2. 3.

More information

Combinational Logic Design

Combinational Logic Design Lab #2 Combinational Logic Design Objective: To introduce the design of some fundamental combinational logic building blocks. Preparation: Read the following experiment and complete the circuits where

More information

LESSON PLAN. Sub Code: EE2255 Sub Name: DIGITAL LOGIC CIRCUITS Unit: I Branch: EEE Semester: IV

LESSON PLAN. Sub Code: EE2255 Sub Name: DIGITAL LOGIC CIRCUITS Unit: I Branch: EEE Semester: IV Unit: I Branch: EEE Semester: IV Page 1 of 6 Unit I Syllabus: BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 9 Boolean algebra: De-Morgan s theorem, switching functions and simplification using K-maps & Quine

More information

RAO PAHALD SINGH GROUP OF INSTITUTIONS BALANA(MOHINDER GARH)123029

RAO PAHALD SINGH GROUP OF INSTITUTIONS BALANA(MOHINDER GARH)123029 DIGITAL ELECTRONICS LAB( EE-224-F) DIGITAL ELECTRONICS LAB (EE-224-F) LAB MANUAL IV SEMESTER RAO PAHALD SINGH GROUP OF INSTITUTIONS BALANA(MOHINDER GARH)2329 Department Of Electronics & Communication Engg.

More information

Chapter 3. Boolean Algebra and Digital Logic

Chapter 3. Boolean Algebra and Digital Logic Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how

More information

SUBJECT NAME : DIGITAL ELECTRONICS SUBJECT CODE : EC8392 1. State Demorgan s Theorem. QUESTION BANK PART A UNIT - I DIGITAL FUNDAMENTALS De Morgan suggested two theorems that form important part of Boolean

More information

UNIVERSITI TEKNOLOGI MALAYSIA

UNIVERSITI TEKNOLOGI MALAYSIA SULIT Faculty of Computing UNIVERSITI TEKNOLOGI MALAYSIA FINAL EXAMINATION SEMESTER I, 2016 / 2017 SUBJECT CODE : SUBJECT NAME : SECTION : TIME : DATE/DAY : VENUES : INSTRUCTIONS : Answer all questions

More information

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Lab Manual for Computer Organization Lab

More information

Operating Manual Ver.1.1

Operating Manual Ver.1.1 Event Counter Operating Manual Ver.1.1 An ISO 9001 : 2000 company 94-101, Electronic Complex Pardesipura, Indore- 452010, India Tel : 91-731- 2570301/02, 4211100 Fax: 91-731- 2555643 e mail : info@scientech.bz

More information

Half-Adders. Ch.5 Summary. Chapter 5. Thomas L. Floyd

Half-Adders. Ch.5 Summary. Chapter 5. Thomas L. Floyd Digital Fundamentals: A Systems Approach Functions of Combinational Logic Chapter 5 Half-Adders Basic rules of binary addition are performed by a half adder, which accepts two binary inputs (A and B) and

More information

GUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT. COURSE CURRICULUM COURSE TITLE: DIGITAL ELECTRONICS AND DIGITAL INSTRUMENTS (Code: )

GUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT. COURSE CURRICULUM COURSE TITLE: DIGITAL ELECTRONICS AND DIGITAL INSTRUMENTS (Code: ) GUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT COURSE CURRICULUM COURSE TITLE: DIGITAL ELECTRONICS AND DIGITAL INSTRUMENTS (Code: 3340904) Diploma Programmes in which this course is offered Electrical

More information

Principles of Computer Architecture. Appendix A: Digital Logic

Principles of Computer Architecture. Appendix A: Digital Logic A-1 Appendix A - Digital Logic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational

More information

Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \

Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \ Sequential Logic Analysis and Synthesis Joseph Cavahagh Santa Clara University r & Francis TaylonSi Francis Group, Boca.Raton London New York \ CRC is an imprint of the Taylor & Francis Group, an informa

More information

DIGITAL ELECTRONICS LAB MANUAL FOR 2/4 B.Tech (ECE) COURSE CODE: EC-252

DIGITAL ELECTRONICS LAB MANUAL FOR 2/4 B.Tech (ECE) COURSE CODE: EC-252 DIGITAL ELECTRONICS LAB MANUAL FOR /4 B.Tech (ECE) COURSE CODE: EC-5 PREPARED BY P.SURENDRA KUMAR M.TECH, Lecturer D.SWETHA M.TECH, Lecturer T Srinivasa Rao M.TECH, Lecturer Ch.Madhavi, Lab Assistant 009-00

More information

SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF ELECTRONICS AND ELECTRICAL ENGINEERING DEPARTMENT OF ECE COURSE PLAN

SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF ELECTRONICS AND ELECTRICAL ENGINEERING DEPARTMENT OF ECE COURSE PLAN SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF ELECTRONICS AND ELECTRICAL ENGINEERING DEPARTMENT OF ECE COURSE PLAN Course Code : EC0205 Course Title : DIGITAL SYSTEMS Semester : III Course

More information

BHARATHIDASAN ENGINEERING COLLEGE, NATTRAMPALLI DEPARTMENT OF ECE

BHARATHIDASAN ENGINEERING COLLEGE, NATTRAMPALLI DEPARTMENT OF ECE BHARATHIDASAN ENGINEERING COLLEGE, NATTRAMPALLI DEPARTMENT OF ECE CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN 1 st year 2 nd semester CSE & IT Unit wise Important Part A and Part B Prepared by L.GOPINATH

More information

Digital Electronics Course Outline

Digital Electronics Course Outline Digital Electronics Course Outline PLTW Engineering Digital Electronics Open doors to understanding electronics and foundations in circuit design. Digital electronics is the foundation of all modern electronic

More information

Engineering College. Electrical Engineering Department. Digital Electronics Lab

Engineering College. Electrical Engineering Department. Digital Electronics Lab Engineering College Electrical Engineering Department Digital Electronics Lab Prepared by: Dr. Samer Mayaleh Eng. Nuha Odeh 2009/2010-1 - CONTENTS Experiment Name Page 1- Measurement of Basic Logic Gates

More information

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in

More information

S.K.P. Engineering College, Tiruvannamalai UNIT I

S.K.P. Engineering College, Tiruvannamalai UNIT I UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES Part - A Questions 1. Convert the hexadecimal number E3FA to binary.( Nov 2007) E3FA 16 Hexadecimal E 3 F A 11102 00112 11112 10102 So the equivalent binary

More information

THE KENYA POLYTECHNIC

THE KENYA POLYTECHNIC THE KENYA POLYTECHNIC ELECTRICAL/ELECTRONICS ENGINEERING DEPARTMENT HIGHER DIPLOMA IN ELECTRICAL ENGINEERING END OF YEAR II EXAMINATIONS NOVEMBER 006 DIGITAL ELECTRONICS 3 HOURS INSTRUCTIONS TO CANDIDATES:

More information

ROEVER COLLEGE OF ENGINEERING & TECHNOLOGY ELAMBALUR, PERAMBALUR DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

ROEVER COLLEGE OF ENGINEERING & TECHNOLOGY ELAMBALUR, PERAMBALUR DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING ROEVER COLLEGE OF ENGINEERING & TECHNOLOGY ELAMBALUR, PERAMBALUR-621220 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING DIGITAL LOGIC CIRCUITS UNIT-1 BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1.

More information

Semester 6 DIGITAL ELECTRONICS- core subject -10 Credit-4

Semester 6 DIGITAL ELECTRONICS- core subject -10 Credit-4 Semester 6 DIGITAL ELECTRONICS- core subject -10 Credit-4 Unit I Number system, Binary, decimal, octal, hexadecimal-conversion from one another-binary addition, subtraction, multiplication, division-binary

More information

Question Bank. Unit 1. Digital Principles, Digital Logic

Question Bank. Unit 1. Digital Principles, Digital Logic Question Bank Unit 1 Digital Principles, Digital Logic 1. Using Karnaugh Map,simplify the following boolean expression and give the implementation of the same using i)nand gates only(sop) ii) NOR gates

More information

Laboratory Objectives and outcomes for Digital Design Lab

Laboratory Objectives and outcomes for Digital Design Lab Class: SE Department of Information Technology Subject Logic Design Sem : III Course Objectives and outcomes for LD Course Objectives: Students will try to : COB1 Understand concept of various components.

More information