Review: What is it? What does it do? slti $4, $5, 6

Transcription

1 Review: What is it? What does it do? Reg Src Instrction Instrction [3-] I [25-2] I [2-6] I [5 - ] 2 Src Op Reslt em em emtoreg I [5 - ] etend slti $, $5, 6 Reg Src Instrction Instrction [3-] I [25-2] I [2-6] I [5 - ] 2 Src Reslt Op em em emtoreg I [5 - ] etend 2

2 Control The control nit is responsible for setting all the control signals so that each instrction is eected properly The control nit s inpt is the 32-bit instrction word The otpts are vales for the ble control signals in the path ost of the signals can be generated from the instrction opcode alone, and not the entire 32-bit word To illstrate the relevant control signals, we will show the rote that is taken throgh the path by R- type, lw, sw and beq instrctions 3 R-type instrction path R-type instrctions inclde add, sb, and, or, and slt Op is determined by the instrction s fnc field Reg Src Instrction Instrction [3-] I [25-2] I [2-6] I [5 - ] 2 Src Reslt Op em em emtoreg I [5 - ] etend 2

3 lw instrction path An eample load instrction is lw $t, ($sp) Op mst be (add) to compte the effective Reg Src Instrction Instrction [3-] I [25-2] I [2-6] I [5 - ] 2 Src Op Reslt em em emtoreg I [5 - ] etend 5 sw instrction path An eample store instrction is sw $a, 6($sp) Op mst be (add) again to compte the effective Reg Src Instrction Instrction [3-] I [25-2] I [2-6] I [5 - ] 2 Src Reslt Op em em emtoreg I [5 - ] etend 6 3

4 beq instrction path A sample branch instrction is beq $at, $, offset. The Op is (sbtract) to test for eqality Reg Src The branch may or may not be taken, depending on the s otpt Instrction Instrction [3-] I [25-2] I [2-6] I [5 - ] 2 Src Op Reslt em em emtoreg I [5 - ] etend 7 Control signal table OperationRegSrcOp em ememtoreg add sb and or slt lw sw X X beq X X sw and beq are the only instrctions that don t write any s lw and sw are the only instrctions that se the constant field. They also depend on the to compte the effective Op for R-type instrctions depends on the instrctions fnc field The Src control signal (not listed) shold be set if the instrction is beq and the s otpt is tre 8

5 Generating control signals The control nit needs 3 bits of inpts Si bits make p the instrction s opcode Si bits come from the instrction s fnc field It also needs the otpt of the The control nit generates bits of otpt, corresponding to the signals mentioned earlier Yo can bild the actal circit by sing big K-maps, big Boolean algebra, or big circit design programs The tetbook presents a slightly different control nit Instrction Instrction [3-] I [3-26] I [5 - ] Control Reg Src Op em em emtoreg Src 9 Logic Array 5

6 A Closer Look At the Operation Consider the instrction add $t, $t, $t2 opcode rs rt rd shamt fnc Assme $t and $t2 initially contain and 2 respectively. Eecting this instrction involves several steps.. The instrction word is read from the instrction, and the program conter is incremented by 2. The sorces $t and $t2 are read from the file 3. The vales and 2 are added by the. The reslt (3) is stored back into $t in the file The add moving throgh the path + Instrction [3-] Instrction I [25-2] I [2-6] I [5 - ] Reg Src Reslt Op Src em em emtoreg I [5 - ] etend

7 State Elements In an instrction like add $t, $t, $t2, how do we know $t is not pdated ntil after its original vale is read? Reg em 2 em 3 The path and the clock STEP : A new instrction is loaded from. The control nit sets the path signals appropriately so that s are read, otpt is generated, is read and branch target es are compted STEP 2: The file is pdated for arithmetic or lw instrctions is written for a sw instrction The is pdated to point to the net instrction In a single-cycle path everything in Step mst complete within one clock cycle. 7

8 The lw moves throgh the path 5 The beq moves throgh the path 6 8

9 Net Steps Designing a compter is only the first step Net, we mst consider how fast it rns, And how to make it rn faster We have a single cycle design that assmes all operations complete within one clock cycle 7 The slowest instrction... If all instrctions mst complete within clock cycle, then the cycle time >= slowest instrction For eample, lw $t, ($sp) needs 8ns, assming the Instrction delays shown here Instrction [3-] I [25-2] I [2-6] I [5 - ] ns I [5 - ] ns reading the instrction reading the base $sp compting $sp- reading the storing back to $t 2 etend ns ns Reslt 2ns ns 2ns 2ns ns ns 8 8ns 9

10 ...determines the clock cycle time If we make the cycle time 8ns every instrction will take 8ns, even if they don t need that mch time For eample, the instrction add $s, $t, $t2 really needs jst 6ns reading the instrction reading s $t and $t2 compting $t + $t2 storing the reslt into $s 2ns ns 2ns ns 6ns Instrction [3-] Instrction I [25-2] I [2-6] I [5 - ] ns I [5 - ] ns 2 etend ns ns Reslt ns 9 Smmary A path contains all the fnctional nits and connections necessary to implement an instrction set architectre For or single-cycle implementation, we se two separate memories, an, some etra adders, and lots of mltipleers IPS is a 32-bit machine, so most of the bses are 32-bits wide The control nit tells the path what to do, based on the instrction that s crrently being eected Or processor has ten control signals that reglate the path The control signals can be generated by a combinational circit with the instrction s 32-bit binary encoding as inpt Net, we ll see the performance limitations of this single-cycle machine and try to improve pon it 2