Spiral Content Mapping. Spiral 2 1. Learning Outcomes DATAPATH COMPONENTS. Datapath Components: Counters Adders Design Example: Crosswalk Controller

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1 -. -. piral Content Mapping piral Theory Combinational Design equential Design ystem Level Design Implementation and Tools Project piral Performance metrics (latency vs. throughput) Boolean Algebra Canonical Representations Decoders and muxes ynthesis with min/maxterms ynthesis with Karnaugh Maps Edge triggered flip flops Registers (with enables) Encoded tate machine design tructural Verilog HDL CMO gate implementation Fabrication process path Components: Counters s Design Example: Crosswalk Controller hannon's Theorem ynthesis with muxes & memory and comparator design Bistables, latches, and Flipflops Counters Memories One hot state machine design Control and datapath decomposition 3 HW/W partitioning Bus interfacing ingle cycle CPU MO Theory Capacitance, delay and sizing Memory constructs Power and other logic families EDA design process Mark Redekopp Learning Outcomes I understand the control inputs to counters I can design logic to control the inputs of counters to create a desired count sequence I understand how smaller adder blocks can be combined to form larger ones I can build larger arithmetic circuits from smaller building blocks I understand the timing and control input differences between asynchronous and synchronous memories DATAPATH COMPONENT

2 Digital ystem Design (CU) and Unit (DPU) paradigm eparate logic into datapath elements that operate on data and control elements that generate control signals for datapath elements path:,, comparators,, registers (shift, with enables, etc.), memories, FIFO s Control Unit: /sequencers clk reset Control ignals Control Condition ignals COUNTER Inputs path Outputs Counters Count (Add to Q) at each clock edge Up Counter: Can also build a down counter as well ( ) tandard counter components include other features Resets: Reset count to Enables: Will not count at edge if EN= Inputs: Can initialize count to a value P (i.e. Q* = P rather than Q+) REET (+) Register How would you design the adder block above for a 4 bit counter? Q ample 4 bit Counter 4 bit Up Counter RT: a synchronous reset input and P i inputs: loads Q with P when is active : Count Enable Must be active for the counter to count up (Terminal Count) output Active when Q= AND counter is enabled = output Indicates that on the next edge it will roll over to RT Q*, P P P P3 RT 4-bit CNTR Q Q Q Q3

3 Counters Counter Exercise RT P3-P RT Q3-Q P[3:] Q[3:] R=active at clock edge, thus Q= Q*=Q+ Enable = off, thus Q holds Q*=Q+ Q*=Q+ = active, thus Q*=Q+ Q*=Q+ Q=P Mealy Tput: EN Q3 Q Q Q Counter Design Design a bit Counter (Why?) ketch the design of the 4 bit counter presented on the previous slides P P P P3 RT 4-bit CNTR Q Q Q Q3 Q[3:] Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q Q Q P[3:] RT + D[3:] CLR Reg Q[3:] Q[3:] P P P P3 RT P P P P3 RT 4-bit CNTR 4-bit CNTR Q Q Q Q3 Q Q Q Q3 Q[7:4] Q[:8]

4 Counter Example (Using Parallel Inputs) Design a circuit that counts each clock cycle to produce the pattern 5, 6, 7, 8, 9, 5, 6, 7, 8, 9, 5...9, 59, P P P P3 RT 4-bit CNTR Q Q Q Q3 ADDER Intro Intro o how would we build a circuit to add two numbers? Let's try to design a circuit that can add AN two 4 bit numbers, [3:] and [3:] How many inputs? Can we use K Maps or sum of minterms, etc? + = = REET (+) Register Q Idea: Build a circuit that performs column of addition and then use of those circuits to perform the overall 4 bit addition Let's start by designing a circuit that adds bits: and that are in the same column of addition + = =

5 Addition Half s Addition Half s Addition is done in columns Inputs are the bit of, Outputs are the um Bit and Carry Out ( ) Design a Half (HA) circuit that takes in and and outputs and = + Half = um We d like to use one adder circuit for each column of addition Problem: No place for of last adder circuit olution Redesign adder circuit to include an Half + = = Half Addition s Addition s Add a Carry In input( ) New circuit is called a (FA) Design the internal circuitry on the next slide = + = C out Find the minimal level implementations for Cout and

6 -. -. Logic Addition s = Recall: is defined as true when ODD number of inputs are trueexactly when the sum bit should be Cout = Carry when sum is or more (i.e. when at least inputs are ) Circuit is just checking all combinations of inputs Use for each column of addition Addition s Addition s Connect bits of bottom number to inputs = Use for each column of addition = + = + =

7 Addition s Addition s Use for each column of addition = Use for each column of addition = + = + = Addition s Addition s Use for each column of addition = + = Use for each column of addition = + =

8 Performing ubtraction w/ s Performing ubtraction w/ s To subtract Flip bits of Add - = = + To subtract Flip bits of Add - = = bit s Building an 8 bit 74L83 chip implements a 4 bit adder A 3 A A A + B 3 B B B 4 3 = A = B = Use () 4 bit adders to build an 8 bit adder to add =[7:] and = [7:] and produce a sum, =[7:] and a carry out, C8. Make sure you understand the difference between system labels (actual signal names from the top level design) and device labels (placeholder names for the signals inside each block). A 3 B 3 A B A B A B 74L83 3

9 -.33 Adding Many Bits -.34 EERCIE ou know that an FA adds + + Ci Use FA and/or HA components to add 4 individual bits: A + B + C + D Adding 3 Numbers Mapping Algorithms to HW Add [3:] + [3:] + Z[3:] to produce F[?:] using the adders shown plus any FA and HA components you need Wherever an if..then..else statement is used usually requires a mux if(a[3:] > B[3:]) Z = A+ else Z = B+5 B[3:] A[3:] A[3:] B[3:] Circuit Circuit Comparison Circuit I I A>B Z[3:]

10 Mapping Algorithms to HW / ubtractor Wherever an if..then..else statement is used usually requires a mux if(a[3:] > B[3:]) Z = A+ else Z = B+5 B[3:] A[3:] A[3:] B[3:] I I I I A>B Comparison Circuit Circuit Z[3:] If sub/~add = Z = [3:] [3:] Else Z = [3:]+[3:] / ubtractor Another Example If sub/~add = Z = [3:] [3:] Else Z = [3:]+[3:] Design a circuit that takes a 4 bit binary number,, and two control signals, A5 and M and produces a 4 bit result, Z, such that: Z = + 5, when A5,M =, Z =, when A5,M =, Z =, when A5,M =, 4 bit Input A5 M B3 B B B d d d d UB/ ~ADD i Bi

11 Memories ROM AND MEMORIE Memories store (write) and retrieve (read) data Read Only Memories (ROM s): Can only retrieve data (contents are initialized and then cannot be changed) Read Write Memories (RWM s): Can retrieve data and change the contents to store new data ROM s ROM s Memories are just tables of data with rows and columns When data is, one entire of data is read out The row to be read is selected by putting a binary number on the inputs A A A Inputs ROM Example Address = 4 dec. = bin. is provided as input ROM outputs data in that row ( bin.) Address: = 4 A A A ROM Outputs D 3 D D D : Row 4 is output D 3 D D D

12 Memory Dimensions RWM s Memories are named by their dimensions: x n rows and m columns => n x m ROM n rows => n address bits (or k rows => log k address bits) m cols. => m data outputs A A A n- n - n - ROM... Writable memories provide a set of data inputs for write data (as opposed to the data outputs for read data) A control signal R/W (= / = ) is provided to tell the memory what operation the user wants to perform Address Inputs Inputs A A A DI DI DI DI 3 R/W x4 RWM D m- D Outputs DO 3 DO DO DO RWM s Asynchronous Memories Write example Address = 3 dec. = bin. DI = dec. = bin. R/W = => Write op. in row 3 is overwritten with the new value of bin. Address Inputs Inputs R/W A A A 3 DI 4 DI DI 5 DI R/W 8x4 RWM DO 3 DO DO DO Notice that there is signal with this memory Devices that do not use a clock signal are called " " devices For these memories, the address must be kept and stable for at least t acc amount of time A[:] DI[3:] R/W DO[3:] A[:] DI[3:] R/W t acc t acc DO[3:] Outputs????

13 Asynchronous vs. ynchronous Memories ynchronous Timing Asynchronous memories use no signal For read: Address and R/W signal must be held steady for a certain period of time before DO outputs become valid For write: Address, DI, and R/W signal must be held steady for a certain period of time before internal memory is updated ynchronous memories use a signal For read: Address and R/W signal will be registered on the edge and then DO will become valid during that subsequence clock cycle For write: Address, DI and R/W signals will be registered on the edge and then the internal memory updated during the subsequent clock cycle A A A DI DI DI DI 3 R/W DO DO DO DO 3 ynchronous memories add a clock signal and the input values at a clock edge will only be processed during the subsequence clock cycle For synchronous memories the address must be valid and stable at but then may be changed EN = enable (unless it is ) the memory won't read or write WEN = = Write / = read A[:] DI[3:] EN WEN A[:] DI[3:] WEN twrite M[3] DO[3:] DO[3:]??? mem[3] = mem[6] = Assume EN= tacc Using Memories Add two 8 number arrays (C[i] = A[i] + B[i]) D Q EN reg RT EN RT cntr Q A[:] DI[3:] EN 8x4 Memory WEN A[:] DO[3:] A + A[:] DI[3:] EN 8x4 Memory WEN DO[3:] Crosswalk Controller TEM DEIGN EAMPLE DI[3:] EN 8x4 Memory WEN DO[3:] B i[3:] A & B??? A[] & B[] A[] & B[] A[] & B[] i_q CMEM[]??? A[]+B[]

14 Digital ystem Design Crosswalk Controller Control and path Unit paradigm eparate logic into datapath elements that operate on data and control elements that generate control signals for datapath elements path: s, muxes, comparators, counters, registers (w/ enables) Control Unit: tate machines/sequencers clk reset Control Design a crosswalk controller to adhere to the following description 8 ticks of the clock in the WALK phase 8 ON/OFF BLINKING hand cycles (6 total ticks) Count 8 downto on the NUM display while hand is blinking 6 cycles in the OLID hand NUM(3:) NUM_ON HAND WALK Control ignals Condition ignals Inputs path Outputs Crosswalk tate Machine Crosswalk Controller Operation Use a 4 bit counter to count cycles along with an additional gate or two P P P P3 RT 4-bit CNTR Q Q Q Q3

15 -.57 ummary ou should now be able to build: Registers (w/ Enables) Counters s