Switching Circuits & Logic Design

Transcription

1 witching Circuits & Logic esign Jie-Hong oland Jiang 江介宏 epartment of Electrical Engineering National Taiwan University Fall 24 Latches and Flip-Flops 2

2 Outline Introduction et-reset latch Gated latch Edge-triggered flip-flop - flip-flop J-K flip-flop T flip-flop Flip-flops with additional inputs ummary 3 Introduction Combinational circuits Output is a function depending on the present input, but noast inputs Given an arbitrary input, a combinational circuiroduces only one possible output (after certain delay) Not necessarily acyclic (without feedback) equential circuits Output is a function depending on the past sequence of inputs Must be cyclic (with feedback) ynchronous sequential circuits With synchronization signals (clocked) Asynchronous sequential circuits Without synchronization signals (clockless) 4

3 Introduction Combinational circuits (without memory) 2 3 f z = f(, 2, 3 ) equential circuits (with memory) s mem f g z = f(,s) s + = g(,s) time inde z = f(,s ) z = f(,g(,s )) z2 = f(2,g(,g(,s))) 5 Introduction To construct a system (e.g., circuit, neural network, etc.) that remembers something about the past history of the inputs Need feedback! (assuming no memristive effectives) Closed loops formed in a circuit connection 6

4 Introduction Memory devices Memory devices Latches and flip-flops can assume one of two stable output states, and have one or more inputs that can cause the output state to change Latch Have no clock input Flip-flip Change output state in response to a clock input, but not a data input 7 Introduction Feedback Unstable Oscillator Feedback X X Inverter with feedback Oscillation at inverter output table Memory (-bit) 8

5 et-eset Latch - latch (a) table: = (b) et: : : (a) table: = (b) eset: : : 9 et-eset Latch Cross-coupled form - latch symbol ' ' L eset et eset et directly above (different from the cross-coupled form)

6 et-eset Latch Improper - latch operation When = =, the circuit is unstable isallow = = for - latch et-eset Latch Timing diagram ' є є t t 2 t 3 t 4 t t +є t 3 +є : two NO-gate delay The duration of the (or ) inpuulse must normally be no less than in order for a change in the state of to occur 2

7 et-eset Latch Operation Net-state equation (or characteristic equation): + = +' (=, i.e., == disallowed) resent (or current) state The state of the output of the latch or flip-flop at the time the input signals are applied (or changed) Net state + The state of the output after the latch or flip-flop has reacted to these input signals (t) (t) (t) (t+ ) - - hold reset set prohibited (t) (t) (t) (t+є)=(t)+'(t)(t) 3 et-eset Latch Application witch debouncing Note: only work for a double throw switch, switching between two contacts (but not for a single throw switch) why? +V b a witch at a Bounce at a witch between a and b Bounce at b witch at b 4

8 et-eset Latch Alternative Implementation - latch - latch using NAN gates + L ' - - hold reset set prohibited ' Inputs and are active low 5 Gated Latch Gated latch G G L ' Truth table ymbol L G ' G + hold ( + = ) transparent ( + = ) G + = G'+G 6

9 Edge-Triggered Flip-Flop Unlike latch, flip-flip output changes only in response to the clock, not to a change in rising (or positive) edge triggered (-to- transition on clock) falling (or negative) edge triggered (-to- transition on clock) ' FF ' FF + + = ising-edge trigger Falling-edge trigger Truth table 7 Edge-Triggered Flip-Flop Timing diagram (falling-edge trigger) 8

10 Edge-Triggered Flip-Flop Implementation flip-flop (rising-edge trigger) Composed of two gated latches CLK L G 2 2 L 2 G 2 Time analysis L 2 hold L hold L 2 hold CLK=G 2 If L starts following before L 2 takes on, the FF will not function properly G 9 Edge-Triggered Flip-Flop etup Time and Hold Time ropagation delay: The time between the active edge of the clock and the resulting change in the output etup time: t su The amount of time must be stable before the active edge Hold time: t h The amount of time must hold the same value after the active edge t su t h allowed to change 2

11 Edge-Triggered Flip-Flop etermine Minimum Clock eriod imple flip-flop circuit eample ( 5ns, t su 3ns, inverter delay 2ns) CLK t su inv delay CLK etup time not satisfied t su t su etra 5ns inv delay inv delay etup time satisfied Minimum clock period 2 - Flip-Flop imilar to - latch but with clock input ame truth table and characteristic equation Interpretation of + is different Latch: + is the value of after the propagation delay through the latch FF: + is the value that assumes after the active clock edge - flip-flop ' changes at clock edges Operation summary: == no state change =,= set to (after active edge) =,= reset to (after active edge) == not allowed 22

12 - Flip-Flop Implementation - flip-flop (master-slave flip-flop) Composed of two - latches Only allow the and inputs to change while CLK is high CLK Master 2 lave ' ' ' Time analysis 2 CLK CLK t t 2 t 3 t 4 t 5 ising-edge-triggered FF: Inputs can change while CLK is low Master-slave FF: Incorrect if inputs change while CLK is low 23 J-K Flip-Flop J-K flip-flop is an etended version of - flip-flop + = J'+K' J corresponds to (Jump to ); K corresponds to (Klear to ) tate toggled when J=K= Clk J-K flip-flop ' K FF CK J J K J K + Hold t t 2 t 3 Clear to Jump to Toggle CLK J K Master ' 2 lave 2 ' ' 24

13 T Flip-Flop T flip-flop ' FF T T + hold toggle + = T'+T' = T T = + = T = + = ' T t t 2 t 3 t 4 25 T Flip-Flop Implementation Conversion of J-K to T Connect J and K inputs of a J-K FF together + =J'+K' + =T'+T' Conversion of to T Let = T + = + = T ' ' K CK J Clk T Clk T 26

14 Flip-Flops with Additional Inputs Asynchronous Clear and reset Flip-flops often have additional inputs to set the flip-flops to an initial state independent of the clock ren ClrN + ClrN ' ren,, (not allowed) (no change) ClrN and ren are asynchronous clear and preset inputs (they override the and inputs) ClrN and ren are active low signals When ClrN=reN=, the FF is in normal operation should not be applied to ClrN and ren simultaneously 27 Flip-Flops with Additional Inputs Asynchronous Clear and reset Timing diagram for flip-flop with asynchronous clear and preset CLK ClrN ren t t 2 t 3 t 4 28

15 Flip-Flops with Additional Inputs Clock Enable flip-flop with clock enable (CE) -CE symbol CE ' Implementation : gating the clock Clk En ' Implementation 2: no clock gating Loss of synchronization when ) clock arrive at some FFs at different times 2) En changes at the wrong time CE + = = (CE)' + in (CE) in No synchronization problem Clk ' 29 ummary Latch (w/o clock input) vs. flip-flop (w/ clock input) ropagation delay, setup time, hold time resent (current) state, net state Characteristic (net-state) equations + = +' (=) (- latch or flip-flop) + = G+G' (gated latch) + = ( flip-flop) + = CE+ CE' (-CE flip-flop) + = J'+K' (J-K flip-flop) + = T = T'+T' (T flip-flop) estrictions For - latch/flip-flop, and can not be simultaneously For master-slave - flip-flop, and should not change during the half clock cycle preceding the active edge etup and hold time constraints 3