MSCI 222C Fall 2018 Introduction to Electronics

Transcription

1 MSCI 222C Fall 2018 Introduction to Electronics Charles Rubenstein, Ph. D. Professor of Engineering & Information Science Session 9: Mon/Tues 11/05/18 & 11/06/18 (H8,Q7,L7) Take Home Midterm EXAM REVIEW Mondays 1:00-3:50pm; Tuesdays 2:00-4:50pm ARC E-13 1

2 Class Seating Chart Mondays Electronics Cabinet Cabinet Door Sitai Justin Jordan Jane David Ava Cabinet MONDAY 1pm Luke Toni Aidan Jingyi Khalil Instructor Station Cabinet Cabinet Whiteboard and Screen 2

3 Class Seating Chart Tuesdays Electronics Cabinet Cabinet Door Cabinet Jairo Yeri Yide Danni Elaine Brandon TUESDAY 2pm Leo Andy Stephanie Instructor Station Cabinet Cabinet Whiteboard and Screen 3

4 MSCI 222 Fall Class Schedule & Due Dates MONDAY TUESDAY NOTES 27 August 28 August Session 1. Introduction, Review of Syllabus, Basic Concepts 3, 10 September 11 September NO CLASSES Labor Day / Instructor Unavailable 17 September 4 September Session 2. Basic Electronic Devices (Homework #1 Due) 24 September 18 September Session 3. Semiconductor Materials & Semiconductor Diodes (H2, Q1,L1) 1 October 25 September Session 4. Decimal and Computer Number Systems (H3, Q2,L1) 8 October 2 October Session 5. Transistors as Switches and Amplifiers (H4, Q3,L2) 15 October 9 October Session 6. Analog and Digital Concepts (H5, Q4. L3) 16 October NO Tuesday CLASSES Midterm Break 22 October (*) 23 October (*) Session 7. The Operational Amplifier (H6, Q5, L4) 29 October(**) 30 October (**) Session 8. Digital Integrated Circuit Logic Gates (H7, Q6, L5) 5 November (***) 6 November (***) Session 9. Flip-Flops & "Clocks" (H8, Q7, L6) 12 November 13 November Session 10. Digital Counters (H9, Q8, L7) 19 November 20 November Session 11. Digital Shift Registers (H10, Q9, L8) 26 November 27 November Session 12. Using Analog and Digital IC Circuits Together (Q10, L9) 3 December 4 December Session 13. Interfacing Computers; RFID Last Day for Labs (L10) 10 December 11 December In-class 2.5 hour Final Examination NOTE: 5-minute Quizzes one week after homework due & reviewed session MIDTERM: (*) Distributed; (**) Exam/Draft Paper Due; (***) Reviewed in class In-class Final Exams 10/11 December (Monday 10 December = Conflict Day) 4

5 MSCI 222C Class Readings Schedule In addition to the Class Notes (222Notes.pdf)!!! Session Due Notes 2 EW1: Pp 1-27; Armstrong: Chapters 1 3 (Pp 1-16) 3 EW1: Pp 28-65; Armstrong: Chapters 4 6 (Pp 17-63) 4 EW1: Pp 66-76; Armstrong: Chapters 7 9 (Pp ) 5 EW1: Pp 77 -End; Armstrong: Chapters (Pp ) 6 EW2: Pp 1-50 and Pg 90; Armstrong: Chapters (Pp ) 7 EW2: Pp 51-79, Review Pg 12; Armstrong: Ch. 14 End (Pp ) 8 EW2: Pp 80 - End, Review Pg 12 (CD4013, CD4017) 9 EW2: Review Pg 12 (CD4013, CD4017) 10 EW2: Review Pg 37 (555 Timer) 11 Review EW1 and EW2 as necessary, Sensors Lab Manual if interested 12 and on Review EW1 and EW2 as necessary KEY EW1 = Basic Electronics: Transistors and Integrated Circuits, Workbook I by Forrest M. Mims, III (ew1.pdf) EW2 = Digital Electronic Projects, Workbook II by Forrest M. Mims, III (ew2.pdf) Armstrong = Man of High Fidelity (armstrong2.pdf) Sensors = Radio Shack Electronic Sensors Lab by Forrest M. Mims, III (sensors.pdf) 5

6 MSCI 222C Hands-on Lab Modules #01: Measuring Resistance and Voltage #02: Voltage Sources, LEDS, Diodes & Characteristic Curves #03: Capacitors, Time Constants & Transistor Gain #04: Voltage Regulation & Transistor Switching #05: Analog IC Voltage Comparator #06: Basic Digital Logic #07: Set-Reset Latches & Type D Flip-Flops #08: Decade Counter and One Shot Switch Debouncer #09: Three Stage Type D Flip-Flop Shift Register #10: NE555 IC Timer Circuits Optional Labs (Additional Labs may be added or substituted): #A: Sound Detector Circuit (Audio-triggered One-shot) #B: Seven Segment Display Decoder-Driver Circuit 6

7 Instructor Contact Information Dr. Charles Rubenstein Professor of Engineering & Information Science Pratt Brooklyn Campus Office: ARC G-49 Fall 2018 Office hours (by appointment *) Mondays: 4:00pm - 5:00 pm = ARC G-49 (or E-13) Tuesdays: 5:00pm - 6:00pm = ARC G-49 (or E-13) (*Please me at least a day in advance if you plan on coming to office hours ) Send me an crubenst@pratt.edu Subject line: 222C or Electronics 7

8 * Class Session Archives 18fa09.pdf (Class PowerPoint slides)* 18fa09_h.pdf (6-slide/page handout format)* *Power points normally available by Wednesday evening After last class of the session 8

9 UPDATED: Fall 2018 Tutoring Sessions 9

10 Fall OPEN LAB TIME - ARC E-13 Mondays 9am - 1pm Wednesdays 12 noon - 5pm Thursdays 12 noon - 5pm Fridays 9am - 5pm BY PRE-ARRANGEMENT ONLY CONTACT: Mrs. Margaret Dy-So, Assistant to the Chairperson Mathematics & Science Department ARC G-41 On pre-arranged day, access to E-13 and the White Console Cabinet is obtained from Ms. Dy-So or the student assistant in room G-39 10

11 Today s Class - Session #09: DUE: Homework Set #08 Readings: Review Pg 12 (CD4013, CD4017) Lecture: Digital Integrated Circuit Logic Gates 2 Do: Quiz #07, Review Homework Set #08 and Lab #06 Module #07: Set-Reset Latches & Type D Flip-Flops REVIEW: Midterm Exam, Paper and WTC Form For Session 10: DUE: Homework Set #09 Readings: EW2: Review Pg 12 (CD4013, CD4017) 2 Do: Quiz #08, Review Homework Set #09 and Lab #07 Module #08: Decade Counter and One Shot Switch Debouncer 11

12 Questions? 12

13 MSCI 222C Electronics Review Kirchhoff s Laws - KCL & KVL Ohms Law Power Law emath Calculations Combining Resistors Time Constants Voltage Divider Equation 13

14 Kirchhoff s Laws: KCL and KVL KCL: The current going into any point has to be the same as the current going out of the point also called The Law of Conservation of Current KVL: The sum of all the voltages, as you go around a circuit from some fixed point and return there from the opposite direction, and taking polarity into account, is always ZERO also called The Law of Conservation of Voltage 14

15 OHMS LAW & the POWER LAW There are three common forms for each Equation: Ohms Law: V=IR Power Law: P = I V V = I R R = V / I I = V / R P = I V P = I 2 R P = V 2 / R 15

16 About Electronics Math Calculations Ohms Law equation: V=IR and I = V / R 1. If R is 1 Ohm = 1 Ω and V is 1 volt: then I = 1 Ampere 2. If R is 1MΩ = 1,000,000 Ω and V is 1 volt: then I = 1 microampere = (1 ua = 1 µa) 3. If R is 1k Ohm = 1kΩ = 1000Ω and V is 1 volt: then I = 1 milliampere ( = 1 ma) This is the most common calculation for our labs 16

17 Series Resistors CURRENT THROUGH resistors is the same in series circuits 1. Resistors in SERIES add R ab = R 1 + R R n 2. For n Like Resistors in SERIES: R ab = n R 17

18 Parallel Resistors The VOLTAGE ACROSS Resistors is the same in parallel circuits 1. The Inverse of Resistances in PARALLEL add 1/R ab = 1/R 1 + 1/R /R n 2. For TWO Resistors in Parallel; R ab = R 1 R 2 / (R 1 + R 2 ) 3. For n Equal Resistances in Parallel; R ab = R / n 18

19 Simple Series/Parallel Resistor Circuits The Equivalent Resistance of the circuit above: R ab = [ R 1 R 2 / (R 1 + R 2 ) ] + R 3 19

20 Time Constant NOTES The time required to charge or discharge a capacitor requires calculating: τ = R C with τ in seconds, R in ohms, C in Farads 20

21 The Voltage Divider Equation Vout = Vin [ R 2 / (R 1 + R 2 ) ] When a voltage is applied to two (or more) resistors in series, the voltage across a particular resistor is the applied voltage times the selected resistor divided by the sum of the resistors 21

22 Typical Voltage Dividers Math Analysis Drawing: More Realistic Schematic: Voltage Divider Equation: Vout = Vin [ R 2 / (R 1 + R 2 ) ] 22

23 About Transistor Calculations The NPN schematic symbol can be divided into: 1. A Base-Emitter circuit where the base-emitter junction forms a silicon diode: and V be = V d = 0.6v 2. And a Collector-Emitter circuit where: a. I C = I B h FE b. And the transistor saturation current is calculated as if the C-E junction is a short circuit thus giving a maximum collector current possible: when the transistor is fully on (V CE 0) 23

24 NOTES: Non-Inverting NPN Transistor Switch As shown, with switch DOWN: V in = 0 Voltage at the base, V b = 0 And the LED is OFF With the switch in the UP position: V in = +Vcc Voltage at the base, V b = V cc V R1 KVL: LED Voltage, V LED = V cc V R1 V be And the LED is ON NOTE: V CE zero apx short circuit when transistor is ON ) 24

25 NOTES: Inverting NPN Transistor Switch As shown, with switch DOWN: V in = 0, voltage at the base, V b = 0 Note: V CE apx OPEN circuit And the LED is ON With the switch in the UP position: V in = +Vcc Voltage at the base, V b = 0.6v Note: V CE apx SHORT circuit And the LED is OFF as V c is at ground 25

26 LOGIC Gates & Truth Tables Truth Table Review A B AND NAND OR NOR ExOR ExNOR Bit Binary Decoding Chart 2 7 = = = = = = = =

27 +5 Volt Voltage Regulator Circuit You ALREADY have the 7805 Voltage Regulator connected as a 5 Volt Source (with a 1K Resistor and Green LED): DO NOT REMOVE REGULATOR CIRCUIT!!! You will be using it as the power source for the remainder of the semester 27

28 Questions? 28

29 What does reading the text Man of High Fidelity mean to you with respect to your intellectual property? Your DRAFT paper + WTC = (WTC = Your FINAL paper + WTC = (WTC = Your final paper must be at least SIX pages long it MUST include direct references to the Armstrong text and at least three (3) other resources 29

30 V. Method of Assessment & Grading Hands-on Lab Work Ten Homework Quizzes 30% (3% each)* 20% (2% each) EXAMS & Research Papers: Take Home Mid-Term 10% MidTerm Paper (Draft 5%; WTC %) 5% Final Examination 20% Final Paper (Draft 5%; WTC 15%, Final 15%) 15% (* - two each 5% Optional Labs after completing 10) 30

31 MSCI 222C FALL 2018 Introduction to Electronics Charles Rubenstein, Ph. D. Professor of Engineering & Information Science MIDTERM REVIEW 31

32 MSCI 222 Electronics FALL 2018 MidTerm (8): 57 ave; 101 hi / 48 low (9): 64 ave; 82 hi / 42 low OVERALL 17 exams: 60! Average normally apx high / 42 low 32

33 Homework #07 Quiz Audio Amplifier Circuits 33

34 Homework QUIZ #07 7.1) Audio Amplifier REVIEW Questions (Check your answer) Is the effect of negative feedback on an audio amplifier to: 7-1a) increase or decrease amplification? You have five minutes to solve 34

35 QUIZ: Homework # a) Does negative feedback increase or decrease amplification? Per Class Notes #06: negative feedback INCREASES amplification 35

36 MSCI 222 Electronics Homework #07 Review 36

37 Homework # a) Does negative feedback increase or decrease amplification? Per Class Notes #06: INCREASES amplification 7-1b) Does negative feedback increase or decrease distortion? Per Class Notes #06: DECREASES distortion 7-1c) Does negative feedback widen (i.e., improve) frequency response or narrow (i.e., make worse) frequency response? Per Class Notes #06: IMPROVED frequency response 37

38 Homework #07 3, 4 8-3) Refer to Figure 8-3 and write out the truth table for the circuit. (A) NOT A B (AND) C = NAND ) Refer to Figure 8-4 and write out the truth table for the circuit. (A) NOT A B (OR) C = NOR

39 MSCI 222 Electronics Homework #08 Review 39

40 Homework #08 1a/1b 8.1a. Redraw the schematic sketch on the bottom lower left of page 5 of EW2 which shows how to make an OR Gate out of three (3) NAND Gates. Since a single CD4011 IC contains four NAND gates this circuit can actually be implemented. Be sure to label your circuit inputs and outputs: Gate 1 In, Gate 2 In, Gate 1 Out, Gate 2 Out, and Gate 3 Out. 8.1b. Add pin numbers to the sketch In 1 In 2 (Note: Not shown - Pin 14 goes to Vcc and Pin 7 goes to Ground) (Input Pins 12/13 and Output Pin 11 for the fourth NAND gate are not shown) 40

41 Homework #08 2, 3 8-2) Using truth tables (entering the symbols 0 and 1 only) prove that the three NAND gates of problem 1, above, will actually perform the OR function, i.e., fill in the 5 columns of the truth table below. Gate 1 In Gate 2 In Gate 1 Out Gate 2 Out Gate 3 Out ) Are the leftmost two columns and the last column consistent with logical OR? (Yes or No? - if No, please correct your work <grin>.) Yes 41

42 Homework #08 2a 8.2a) Using the symbols 0 and 1 only write the logic outputs as indicated for two-input NAND gates, OR gates and NOR gates in the columns of the truth table below. (Presume the inputs are to each of separate logic gate devices ) Gate 2 NAND OR In Out Out Gate 1 In Table 7.1 Three Gate Truth Table NOR Out

43 7-Segment Display Outputs We know a 7-Segment Display displays the Numbers; 0 through 9: What other characters and/or symbols could be displayed by a 7-segment display? 43

44 7-Segment Display Outputs Other symbols: A, C, E, F, H, J, L, P, U and h: b, d, and others are also possible 44

45 Questions? 45

46 MSCI 222 Electronics Lecture Notes and Class Discussion Flip-Flops and Debouncing 46

47 NOTES: Buffer Logic Gate 0 Levels Typical response of a logic gate to a variable (analog) input voltage The potentiometer R 1 varies the Vin, the voltage divider input into the non-inverting or buffer logic gate IC 1 as shown. When Vin is reduced to the 0 threshold, the output Vout goes from Vcc (= 1 ) to zero volts, and the gate turns OFF. 47

48 TTL & CMOS 0 and 1 Logic Levels TTL in: 0 = 0-0.6v 1 = 2.0v+ CMOS in: 0 = 0-1.5v 1 = 3.7v+ 48

49 NOTES: How Noise Effects Logic Gates Slowly-changing DC or signal with AC noise* superimposed Each time the extraneous noise level dips below the 0 threshold level the gate sees a 0 Each time the level rises above the 1 level it sees a 1 *NOTE: Any unconnected lead wires act as antennas(!) 49

50 Switch Bouncing A push button switch is a metal piece that can be pressed onto a contact to close the switch allowing current to flow. In inexpensive switches, the metal is not far from the contact and when released may actually bounce up and down giving the appearance of more than one output pulse to a fast (high speed) IC input: Note that an IC Gate (input) has a threshold voltage above which the Gate sees a logical 1 input 50

51 Flip-Flop NOTES A digital Flip-Flop normally has TWO outputs. One output is labeled Q and the other, which is the inverse of the Q output, is labeled Q-not or as Q on a schematic diagram. The Truth Table for these outputs is therefore: Q Q-NOT The CD4013 has a pair of D type Flip-Flops inside the package, each has the schematic: 51

52 Clocking a One Stage Shift Register One Stage, Rising Edge Triggered, Shift Register: ( Rising edge-triggered F/F ) 52

53 Clocking a Two Stage Shift Register Two Stage, Falling Edge Triggered, Shift Register: ( Falling edge-triggered F/F ) 53

54 MSCI 222 Electronics Session 9 Flip-Flops and "Clocks" (Pulse Train Sources) 1. Why would clocked logic be more reliable than un-clocked logic in digital circuits? 2. Considering what we saw about clocked logic, what would computer clock speed mean? Don t forget to insert ICs ACROSS breadboard notches with Pin 1 at top left: 54

55 4017 Decade Counter NOTES 1 1) The CD4017 is powered by connecting pin 16 to +Vcc and pin 8 to ground. 2) The 4017 counts, or is clocked by, rises of the input clock line 3) Note that CE the "clock enable" line actually disables the clock when high connect CE to ground if you don t get the clock to work... 4) IC Pin 14 is marked Clk meaning Clock input pin 5) The ten states of the CD4017 Decade Counter are labeled 0-9 to represent the count of clock pulses after reset. 6) Your first step is to label each of the diagrams (figures ) and mark each pin with its function (e.g., mark pin 15 as "reset", mark pin 11 as "output count 9", mark pin 13 as "clock enable ). 55

56 4017 Decade Counter NOTES 2 Additional Hints to consider in 4017 Decade Counter problems: a) Where are clock pulses coming from? In this problem from a standard clock source (e.g., periodic pulses). b) Will the counter count all the way back to count zero or will the clock enable pin go high at some point and halt further counting? c) Will the counter count all the way back to state zero or will the reset pin go high at some point causing a direct reset back to count 0? d) Will the output be very brief because the output line going high brings itself low by forcing a reset? e) Will the output line go high and stay high because in going high it causes a halt (disables the clock)? f) Will the output be normal width (from rise to rise of the clock pulse) because the output line does not cause reset and does not cause halt? 56

57 Questions? 57

58 MSCI 222 Electronics Hands-On Lab Module 6 - REVIEW 58

59 Lab Module 6 Part 1 & 2 Part 1: SERIES SWITCH AND Gate Truth Table S1 S2 LED OFF OFF OFF OFF ON OFF ON OFF OFF ON ON ON Part 2: PARALLEL SWITCH OR Gate Truth Table S1 S2 LED OFF OFF OFF OFF ON ON ON OFF ON ON ON ON 59

60 Lab Module 6 Parts 3 & 4 Parts 3/4: CD4011/4001 QUAD 2-INPUT NAND/NOR GATE IC NAND Truth Table S1 S2 LED NOR Truth Table S1 S2 LED

61 Questions? 61

62 MSCI 222 Electronics Hands-On Lab GENERAL NOTES 62

63 Basic Lab Notes 1) To conserve your multimeter s 9V battery, be sure to turn the meter off if not in use for over 5 minutes. 2) All work is to be done individually, and submitted before you leave the class. Double check when leaving that your meter is turned off and in your Pratt kit. There are no lab reports" in this course. 3) Enter all results on both the Instructions Sheet if printed out -and the Results Sheet. Keep the Instruction Sheets as a reference. Turn in the Results Sheets at the end of the period, finished or not, for grading. There are NO results sheets after Module 7! You MUST have the instructor view your work! 63

64 CMOS Precautions!!! CMOS (Complementary Metal-Oxide-Silicon) ICs Please note that CMOS ICs require special handling In industry, a grounding strap is typically used when handling more sensitive CMOS devices to avoid static discharge from your hands getting into a gate input. Our chips are not THAT sensitive 1. ALWAYS insert CMOS ICs into circuits with the power OFF 2. Connect any UNUSED pins that feed logic gates to ground or +Vcc to avoid erroneous outputs 3. The voltage at any CMOS input gate must NOT exceed +Vcc 64

65 ** CAUTION ** Most electronic component leads have been tinned with a tin-lead coating to make them easier to solder into a circuit. Although we will NOT do soldering in this class, AFTER working with components, please avoid lead poisoning by washing your hands. Thank You! 65

66 MSCI 222 Electronics Hands-On Lab Lab Module #07 66

67 Parts Needed for Lab Module 7 (1) GREEN Light-Emitting Diode (LED) (1) RED Light-Emitting Diode (LED) (3) RED LED Devices #1, # 4 and # 7 (on Console) (2) 1KΩ Resistor (Part 1: R3, R4) (2) 4.7KΩ Resistor (R1, R2) (2) 10KΩ Resistor (Part 2: R3, R4) (1) S1, S2, S3, S4 Switches (on Console) (1) CD4001 Quad 2-Input NOR Gate IC (4 per IC) (1) CD4013 Dual Flip-Flop IC (2 per IC) 67

68 CD4001 Quad 2-Input NOR Gate The CD4001 is a CMOS logic circuit that contains four individual NOR logic gates in a 14-pin DIP package. Supply Voltage Range: +3 to +18 volts Note: +Vcc at pin 14 and Common Ground at pin 7 SAME pinouts as CD4011 Quad NAND Gate (See Precautions for working with CMOS circuits) 68

69 MSCI 222 Electronics Inserting a 14-pin DIP into the prototype board IC Notch Pin 1 Pin 14 Vcc Pin 7 (gnd) Trench 69

70 Lab Module 7 Part 1: CD4001 Part 1: Set-Reset Latch using a CD4001 Quad 2-input NOR Gate Pressing S1 puts the flip-flop into one state (e.g., LED1 ON) where it stays or latches and Pressing S2 puts it into the other state where it also stays - latches 70

71 CD4013 Dual Type-D Flip-Flop The CD4013 is a CMOS logic integrated circuit containing two D-Type Flip-Flops in a 14-pin DIP package. A clock pulse will store data in the D input. Connecting Clock and Q outputs makes a toggle Flip-Flop for counting circuits. Note: +Vcc at pin 14 and Common Ground at pin 7 (See Precautions for working with CMOS circuits) 71

72 Lab Module 7 Part 2: CD4013 Part 2: Data (D) Flip-flop (using a CD4013 Dual D Flip-flop IC) S1=Clock S2=Set (direct) S3=Reset (direct) S4=Data Resistors Note 2@4.7K, 2@10K Pressing S2 sets the flip-flop (LED4 ON; LED7 OFF); Pressing S3 resets the device (LED4 OFF; LED7 ON); Pressing S1 (Clock) w/s4 OFF has no effect (LED4 OFF; LED7 ON); Pressing S4 (Data) and then pressing S1 => LED4 ON & LED7 OFF 72

73 Any Questions? Send me an or 73

74 End 74