Formal Timing Analysis of Digital Circuits

Transcription

1 Formal Timing Analysis of Digital Circuits Qurat-ul-Ain and Osman Hasan System Analysis and Verification (SAVe Lab) National University of Sciences and Technology (NUST) Islamabad, Pakistan FTSCS 2018 Gold Coast, Australia November 16, 2016

2 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Outline q Introduction q Proposed Methodology q Modeling and Verification q Case Studies q Conclusions

3 Digital Circuits Combinational Logic Osman Hasan Sequential Logic Formal Timing Analysis of Digital Circuits November 16,

4 Digital Circuits Gradual reduction in transistor sizing governed by the Moore s law IC transistor capacity would double roughly every 18 months Analysis of digital designs is becoming quite challenging Osman Hasan Formal Timing Analysis of Digital Circuits November 16,

5 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Analysis of Digital Designs Delay Input Output Real Output Propagation Delay: Time taken by the output signal to switch after the input signal has been applied

6 Delays in Sequential Circuits Clock to Q delay (t clk2q ): Time after the clock edge that output is guaranteed to be stable t clk2q Setup time (t setup ): Time before the clock edge that data must be stable Hold time (t hold ): Time after the clock edge that data must be stable Osman Hasan Formal Timing Analysis of Digital Circuits November 16,

7 Timing Analysis To determine the frequency (how fast) of operation of a circuit t pd = 2t pd_and + t pd_or T clk2q +T comb +T setup +T routing <= T clk_period T clk2q +T comb +T routing >= T hold The goal Is to find the path with the worst case delay in the whole circuit Osman Hasan Formal Timing Analysis of Digital Circuits November 16,

8 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Major Challenges in Timing Analysis Inputs Delay Models Paths Large number of input combinations Many contributing factors for delay (Resistance, Capacitance, etc.) All the circuit paths have to be considered Formal Methods

9 Related Work Author, Venue, Year of Publication Type of Implemented Circuits Delay Model Tool / Technique Max. Gates Max. FF Bozga et al. (ENTCS), 2002 Combinational and Sequential Assumed Delay Open Kronos 24 4 Salah et al. (FORMATS), 2003 Combinational Assumed Delay Open Kronos 88 Clariso et al. (DAC), 2004 Combinational and Sequential Assumed Delay Abstract Algorithm 12 3 Bara et al. (FDL), 2010 Combinational and Sequential Spice Delay Uppaal Tolga et al. (ARCS), 2015 Combinational and Sequential Assumed Delay Uppaal Abbasi et al. (FTSCS), 2016 Combinational Elmore Delay nuxmv 68 Paths have always been identified manually making the analysis prone to error Osman Hasan Formal Timing Analysis of Digital Circuits November 16,

10 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Outline q Introduction q Proposed Methodology q Modeling and Verification q Case Studies q Conclusions

11 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Proposed Methodology DELAY CALCULATION Technology Parameters Mathematical Models (Gates and Sequential Block Library) Elmore Delay Calculation Path Report PATH EXTRACTION Worst Case Timing Analysis Quartus Prime Pro TimeQuest Timing Analyzer Verilog Netlist State Space MODELING AND VERIFICATION UPPAAL Model Counter Example Timing Verification TCTL Queries (Path Delay) Formally Verified Circuit Verification Failure Successful Verification

12 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Delay Calculation (Elmore Delay Model) Combinational Gates C T C ST Data Input Output Delay Equation

13 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Delay Calculation (Elmore Delay Model) Flip Flop (True Single-Phase Clocked (TSPC) Data Input Output Delay Equation

14 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, UPPAAL Model Checker Based on timed automata (TA) theory TA = Locations Initial Location Clocks Edges Actions Invariants Name Properties Name Properties Possibly E<> P Eventually A <> P Potentially Always E [] P Leads to P à q Invariantly A [] P

15 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Outline q Introduction q Proposed Methodology q Modeling and Verification q Case Studies q Conclusions

16 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Modeling Details Timed Automata (TA) for a Combinational Circuit (Not Gate)

17 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Modeling Details Timed Automata (TA) for Sequential Circuits (Flip-Flop)

18 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Modeling Details (Composition) NOT AND_2IN NAND NOR FLIP- FLOP CLK Circuits AND (2 input) OR (2 input) AND (3 input) OR (3 input) NAND (3 input) NOR (3 input) Circuit Composition

19 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Properties Verification Sum of Delays in a Combinational Circuit

20 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Properties Verification Input to Flip-Flop Flip-Flop to Flip-Flop Flip-Flop to Output

21 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Outline q Introduction q Proposed Methodology q Modeling and Verification q Case Studies q Conclusions

22 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Case Studies Combinational Circuit ISCAS-85 C17 (6 Nand Gates) Sequential Circuit ISCAS-89 S27 (2 Nand, 6 Nor, 5 Not Gates and 3 Flip-Flops)

23 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, C17 Benchmark Circuit Path Information Properties

24 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, S27 Benchmark Circuit Path Information

25 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, S27 Benchmark Circuit Verified Properties

26 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Results - Combinational Circuits Circuit No. of Gates Total Verification NAND NOT NOR Gates Time (s) Memory (MB) C C C Full Adder Full Adder Full Adder bit RCA

27 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Results - Sequential Circuits Circuits Number of Gates Total Number of Verification Nand Nor Not Gates FF Time (s) Memory (MB) Flip-Flop bit SIPO shift register 64 bit SISO shift register 64 bit Johnson Counter 64 bit Ring Counter S S S

28 Comparison Combinational Circuits Verification Time (s) C17 C17 C17 F Adr F Adr 4-bit RCA Abbasi et al Proposed Work Osman Hasan Formal Timing Analysis of Digital Circuits November 16,

29 Comparison with Previous Techniques 1000 No. of Gates and Flip-Flops M. Bozga et al. O. Maler et al. R.Clariso A. Bara et al. Abbasi et al. Propsed Work Gates Flip-Flops Osman Hasan Formal Timing Analysis of Digital Circuits November 16,

30 Comparison with Previous Techniques Author Venue, Year M. Bozga ENTCS, 2002 O. Maler FORMATS, 2003 Comb Cct Seq Cct Auto. Path extraction Delay Modeling!! Assumed Delay! Assumed Delay R.Clariso, 2004!! Assumed Delay A. Bara FDL, 2010 Tolga ARCS, 2015 Lodhi FTSCS, 2016 Proposed Technique Tool / Technique Open Kronos Open Kronos Abstract Algorithm!! Spice Delay Kronos/ Uppaal! Assumed Delay Max. Gates Max. FF UPPAAL ! Elmore Delay nuxmv 68 0!!! Elmore Delay UPPAAL Osman Hasan Formal Timing Analysis of Digital Circuits November 16,

31 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Outline q Introduction q Proposed Methodology q Modeling and Verification q Case Studies q Conclusions

32 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Conclusions A generic framework to facilitate the formal timing analysis Mathematical modeling of Component Delays Automatic path extraction Model checking based verification of circuits Used to analyze of several digital circuits, like Full Adder, 4- Bit Ripple Carry Adder, Shift Registers as well as C17, S27, S208, and S386 benchmark circuits Ongoing and Future work Incorporate routing delays and clock skew of circuits Modeling and Verification of larger case studies

33 Osman Hasan Formal Timing Analysis of Digital Circuits November 16, Thanks!