Lecture 21: Sequential Circuits. Review: Timing Definitions

Transcription

1 Lecture 21: Sequential Circuits Setup and Hold time MS FF Power PC Pulsed FF HLFF, SFF, SAFF Source: Ch 7 J. Rabaey notes, Weste and Harris Notes Review: Timing efinitions T C : Propagation elay from Ck to, assuming has been set early enough relative to Ck T setup (U): minimum time between change and the transparency Ck Edge, such that will be guaranteed to change T hold : minimum time must be held after the triggering Clk edge T skew : spatial variation of clock arrival time between two points in the chip t t su ATA STABLE t hold t Register t c 2 q ATA STABLE t 1

2 FF/Latch esign Balancing act Power, area, speed Look for similarities in FF/Latch design Input stage X Internal Node output stage ata Storage Internal Node Stores sampled data. How? Static: stores as long as power is on ynamic: store data in a capacitor (internal node capacitance) 2

3 Sampling How do you sample data? Sampling should occur for =Hi and =Lo Consider the following Latches Timing Issues Clk t t (a) Clk- elay t T Clk- 1.05t C 2 t C 2 t Su t 2 C t H T Setup-1 (b) T Hold-1 -CK delay Time 3

4 elay vs. Setup/Hold times Ck- (ps) t setup t hold X Clk -Ck (ps) Why does t CK- increase when setup/hold times are NOT met? sampling storage X Resolve time window large X Resolve time window too small Metastable Types of Flops MASTER-SLAVE FF PULSE-TRIGGERE FF data 4

5 Hard vs. Soft Clk edges Flop Latch Power PC 603 (Gerosa, JSSC 94) 5

6 Power PC 603 (Gerosa, JSSC 94 Low power feedback and low internal power High clock load More power dissipated in clock distribution network Small Ck- delay positive setup time Pay attention to: iffusion input: overshoot/undershoot due to unbuffered input Race issues due to clock skew Sequencing: Pulsed Latches How to generate short pulse? Pulsed Latches p t pw p p Latch Combinational Logic Latch 6

7 Hybrid Latch Flip-Flop AM K-6, Hamid Partovi, ISSCC 1996 Clocked transistors ata Transistors HLFF timing waveforms X 1-1 Glitch =Hi Clk_db Clk Clk_db X 7

8 Flip-Flop features HLFF Single phase clock Edge triggered (single clock edge) Latch features Transparency period (3 inv delays) Negative setup time. Absorbs skew Hold time comparable to HLFF delay Clk- delay can be smaller than hold time (verify for all process corners) Fully Static Semi-ynamic Flip-Flop (SFF) Sun UltraSparc III, Fabian Klass, JSSC 99 8

9 SFF 1 storage S S 0 1 =Hi =Lo Embed logic into latch 9

10 Sense-amplifier based FF (SAFF) Matsui et. al EC Alpha 21264, Strong Arm Input stage Cross-coupled inv. Pre-charge/Sampling Sense Amplifier FF (SAFF) Nice interface from domino logic Pulse generation stage is fast (resolves small input voltages) Ideal for low swing input signaling Nand RS static latch is speed bottleneck and b output waveforms are not symmetric 10

11 Master-Slave vs Pulsed-Triggered Master-Slave Positive setup time Hold-time close to zero Two clock phases required istributed globally Generated locally Hard edge property Sensitive to clock skew Pulsed-Triggered Negative setup time (data can arrive after edge) Sensitive to hold-time violation (t ck-q < t hold ) Soft edge property (absorbs clock skew) Flip-Flop Performance Comparison 11

12 General Characteristics Clock Power Consumption 12