Circuit and System Design for DSP

Transcription

1 lektronik abor Circuit and System Design for DSP Prof. Dr. Martin J. W. Schubert, Electronics Laboratory, OTH Regensburg, Regensburg, Germany

2 Circuit and System Design for DSP Principles and Practices Using Matlab and VHDL Abstract. An comprehensive example of an A/D and D/A conversion system is used to illustrate several aspects of digital signal processing, digital circuit design, A/D and D/A conversion and analog circuit design for signal conditioning. Advantage is taken from the numerical power of VHDL, Matlab and Spice. 1 Introduction 1.1 Objectives and Organization of this Document This document is intended for students learning time-discrete Signal processing, A/D and D/A conversion as well as electronic design automation using VHDL. It is a comprehensive example that teaches different aspects on the same system. Students within course System Concepts (SK) get a top-level understanding of digital signal processing (DSP) systems, e.g. how to trade speed versus resolution, using ΔΣ converters as work-around to avoid aliasing problems and expensive A/D or D/A converters, and how to manage the required data rate changes. Students of course Electronic Design Automation (RED: Rechnergestützter Entwurf Digital) concentrate on the questions how to translate the theory learned in SK into real-life circuitry. There is no need to make SK and RED at the same time, but formulae given RED will be better understood knowing SK, e.g. how to compute impulse responses of digital filters. Students learning A/D or D/A Converters (ADA) are focused on these data converters in chapter 2, introduce some non-linearity as detailed in chapter 5 and may develop some own Matlab tools to model and measure quality criteria related to A/D and D/A converters such as differential and integral non-linearity (DNL/INL), spurious free dynamic range (SFDR), total harmonic distortion (THD) of effective number of bits (ENOB). Last but not least, students learning analog circuit design (SC: Schaltungstechnik) get key circuits, respective formulae and applications for circuits performing analog signal conditioning. These circuits are offered as ready-to-use recipe, detailed explanation of their operation is given in the author s lectures of course Schaltungstechnik (SC)

3 Color code of this document: Black text is addressed to everybody. Grey text is useful information (e.g. concerning mathematics) without relevance for exams. Blue text indicates exercises / solutions. Green text is addressed to students learning A/D and D/A conversion only. Pink is addressed to students learning signal processing theory, Brown text is addressed to students learning VHDL-based electronic design automation only. The organization of this document is as follows: Section 1 is this Introduction, Section 2 makes the user familiar with VHDL related hardware: DE2, DA2 and DS2, boards, Section 3 introduces the A/D/A Conversion (ADAC) system used as example, Section 4 details advanced VHDL modeling techniques for the ADAC model, Section 5 teaches linear and non-linear scaling for Signal Conditioning purposes, Section 6 details Quantization from a mathematical point of view, Section 7 applies sections 5 and 6 to Matlab based A/D and D/A converter models, Section 8 describes Sampling Rate Issues (SK) on a high-level point of view, Section 9 presents Sampling Rate Issues (RED) from circuit designer s FSM point of view, Section 10 draws relevant Conclusion and Section 11 offers some References - 3 -

4 1.2 Modeling Levels There are different levels of system design. In this tutorial we use the top 3, i.e. specification, cycle based and event driven, according to the waterfall or V models. Table 1.2: Levels of Modeling Digital Systems Level Tools Comments Specification Words, Figs., On the top level specification, working with words, Pseudo-C figures and so called pseudo-c, i.e. not suitable for Cycle Based Event Driven, Concurrent, Data Flow Simultaneous, Conservative Matlab, System C/C++ VHDL, Verilog Spice simulation, C-like expressions to sketch algorithms. Top-level verification, x faster than VHDL: Assuming synchronously clocked FSM design we can model memory as bit vector mem and next-state logic as function f_ns(stimuli,mem). Then we can compute clock cycle i as mem(i+1) = f_ns(stimuli(i),mem(i)). Simulation of gates and registers respecting gate delays. This is also called data flow level, as energy conservation is lost. Suitable up to 100 nodes only, as for any time point at any node a solution for all nodes has to be computed. Uses equations based on energy conservation. Device Pisces 3D-simulation of single devices. After process simulation is done, 3-dimensional voltage and current densities are computed within a device model, typically with finite elements. Process Suprem 3D-simulation of the device production process, e.g. oxidation, etching, ion implantation, etc

5 2 Hardware Available Hardware and Software for Hands-on Training The course makes you familiar with the Terasic's DE2 board [1] using Altera's Cyclone II FPGA [2]. More documentation is found e.g. at [3]-[5]. It is assumed that you have Altera s Quartus II 8.1 software DE2 user manual [3] and the board s schematics [4]. The last version of Quartus supporting Cyclone II FPGAs is Quartus II 13.1 which can be obtained from Altera. At OTH Regensburg, Quartus II 8.1 and 13.1 can be obtained from the school s internal network [6]. The DE2-baord is employed to operate the self-made DA2 board, which is concerned with some basic A/D and D/A conversion design techniques. The DS2 grand child board assembles A/D and D/A converters on DA2 board to form a 1 st or 2 nd order ΔΣ modulator. Use of VHDL VHDL is not case sensitive. In the following KEYWORDS will be written in ALL CAPITAL LETTERS and user defined names in lowercase letters. Exception: Capitalized initials are used for composed self-made names, e.g. AddressBus or DataBus. Self-made data types begin with t_, e.g. t_statevector. Acknowledgements The author would like to thank Terasic Technologies [1] for admission to use screen copies of Terasic documentation for teaching purposes in this lectures. At :49, Terasic - Dong Liu wrote: Dear Martin, Thank you for using DE2 board to teach VHDL. Yes, you can open all DE2 design resources for teaching purpose. Thank you! Best Regards, Doreen Liu - 5 -

6 2.1 DE2 Board Document DE2_Introduction_box.pdf This subchapter can be done without the hardware. Have the Altera documentation available or look it up in the internet. DE2 board features: Which FPGA (with how many pin-package) is employed? Cyclone II 2 C35 in a 672 pin package... Specifications: What is the accurate name of the FPGA on the board? (You will have to select it in the Quartus II software) Cyclone II EP2C35F672C Document DE2_UserManual.pdf (from Internet) Get an orientation: Look at the Contents and Read the headlines of the five chapters. See Fig. 2.1 of the User Manual (as copied below from [3]): ->>> Docum. ERROR: JP1=GPIO_0 and JP2=GPIO_1 are exchanged in Fig. 2.1 above! Check the board on the image above: Where is the power-on switch, 9V DC Power in, USB Blaster Port, Run/Prog switch, LCD display module, the 7-segment displays, the 18 red and 9 green LEDs, the 18 toggle switches and 4 push buttons, the Cyclone II FPGA and the expansion headers JP1 and JP2, corresponding to GPIO_0 and GPIO_1, respectively? (On the DE2-70 Board we have the GPIO_x names only.) - 6 -

7 Questions Related to the FPGA How many phase-locked loops (PLLs) does the FPGA have? How many multipliers with how many bits in / out does the FPGA have? You ll find the I/O bit widths in document..\datasheets\cyclone_ii\cyc2_cii5v1_01.pdf on the DE2-CD. You ll find it in the internet or at OTHR in file CD_DE2_for_Quartus7.2.zip at K:\SB\Hardware\Altera\DE2_Board_Altera-Cyclone2-EPC2C35\CD_DE2_for_Quartus multipliers with 2 x 18-bits in and 36 bits out... The FPGA is connected with a Ball-Grid-Array (BGA). How many pins does it have?... Organized in how many rows and columns? x (You may find the answer later in the Quartus II software with Assignments Pins after correct settings of Assignments Device...) Questions Related to the LEDs and Switches See chapter 4.2 Using the LEDs and Switches in the DE2 User Manual [3] and check signal names with the definitions in file DE2_pin_assignments.csv [5]. What are the names of the signals connected to the 18 toggle switches? SW(0...17) What are the names of the signals connected to the 4 push buttons switches? key(0...3) What are the names of the signals connected to the 18 red LEDs? What are the names of the signals connected to the green LEDs? Which level (High/Low) will turn a red LED on? Which level (High/Low) will turn a green LED on? LEDR(0...17) LEDG(0...8) High High Questions Related to the 7-Segment (7seg) Displays See chapter "Using the 7-Segment Displays" in the User Manual. What are the names of the signals connected to the 7-segment (7seg) displays? HEX#, #= Which level (High/Low) will turn a LED of the 7-segment display on? Undriven 7-seg.-LEDs are ON. The FPGA sets undriven output pins to state Low..'0'

8 Questions Related to the Expansion Headers Fig from DE2 User Manual [3] shows an extraction of the schematic diagram. (For complete schematics see file DE2_schematics.pdf [4].) The schematics is drawn in unreadable - 8 -

9 parts. Complete the figure below to deliver a connectedly schematics for the circuitry from the FPGA to Pins 1 and 3 of both, JP1 (=GPIO_0) and JP2 (=GPIO_1). Label all elements: resistors incl. values, diodes, pins at the expansion headers and the FPGA, supply voltages, wire names and their VHDL signal names as defined in the DE2_pin_assignments.csv file [5]. Fig (a): Cutout of DE2_schematics.pdf [4]. Fig (a) shows a cutout of the DE2 schematics [4]. From left to right: Wire name, chippin-name, intended purpose. For us it is the bridge from wire name to pin name. for example wire GPIO_B25 is connected to pin K23. To find this by yourself use the "find" function in Acrobat reader to find strings like "GPIO_B25" or "K23"

10 VCC33 JP1 / GPIO_0 GPIO_B0 47 IO_A0 RN GND D3 TopView WireBond Altera-Cyclone2, P2C35F672C6 GPIO_0(0) A B C Pin D25 D E F G H I J K L M Pin M22 N O P GPIO_1(2) Q R S T U V W X Y Z AA AB AC AD AE AF GPIO_B2 Pin E26, GPIO_0(2) GPIO_B36 VCC33 GND VCC33 D5 Pin K25, GPIO_1(0) GND 47 RN28 47 RN37 D IO_A2 JP2 / GPIO_1 1 2 IO_B0 VCC33 GPIO_B38 47 RN37 IO_B2 3 4 GND D41 Figure (b): protection circuitry between chip and GPIO expansion header pin

11 2.1.3 Getting started with Operating the DE2 Board Observe the Board Check the DE2 board in your hands: Where is the power-on switch, 9V DC Power in, USB Blaster Port, Run/Prog switch, LCD display module, the 7-segment displays, the 18 red and 9 green LEDs, the 18 toggle switches and 4 push buttons, the Cyclone II FPGA and the expansion headers JP1 and JP2? What is the labeling mistake in Fig. 2.1 on page 6? Correction? exchange JP1 JP2... Find on the DE2 board all devices that you draw in the figure above. Where are D5 and D41? D5 and D41 are on the bottom side of the DE2 board.... Connect the power cable to the power plug and switch the red power button ON. All display elements should show some activity now due to a start-up procedure Installing and Starting the Quartus II Software (Who needs much more detailed explanations than given in this subchapter is referred to file tut_quartus_intro_vhdl.pdf (30 pages) within DE2-CD\DE2_tutorials\.) First of all we need some preconditions: Create an empty directory on your Windows operating system, name it de2_start. Start Quartus II 8.1 on your computer. Comment: In CIP pools of OTH Regensburg you can start Quartus II version 8.1 and 13 + This tutorial is made for Quartus II 8.1 suitable for the Cyclone II FPGAs on DE2-Boads + Quartus II 13 handles both, Cyclone II and IV FPGAs of DE2 and DE2-115 boards, resp. + Quartus II 13 is the last version knowing the Cyclone II FPGAs on DE2 boards. + Quartus II 8.1 delivers frequently less complicated synthesis results than Quartus II 13. Select menu point Create a New Project (New PROJECT Wizard) Next What is the working directory of the project? : Navigate to \de2_start What is the name of the project? : de2_start. Top-level entity name in the 3 rd line: de2_start (must match the project name). Click on Finish. Exit Quartus II 8.1 Look into your directory de2_start. There will be the three files (and probably others) de2_start.qpf, de2_start.qsf.... Double click left on the Quatus project file de2_start.qpf. You should now be at the same point as before exiting Quartus II. Quartus II: File New VHDL File

12 Copy entity de2_start from listing into this file. Check: The last line should be "END CONFIGURATION con_de2_start;". Click on save button ( a disc, third symbol from right in the top menu), accept file name de2_start. Compilation should work now: Processing Start Compilation. You should see Infos and warnings, but no errors. After some time you should see: "Full Compilation was successful (xxx warnings"). Click in the Project Navigator window on entry de2_start to see your VHDL code again. Look at the synthesized VHDL code: Quartus II: Tools -> Netlist Viewers -> RTL Viewer Listing : VHDL test file -- For Board: Altera DE2 with FPGA Cyclone II EP2C35F672C6 LIBRARY ieee; USE ieee.std_logic_1164.all,ieee.std_logic_signed.all; ENTITY de2_start IS PORT(CLOCK_50:IN std_logic; key:in std_logic_vector(3 DOWNTO 0); -- low when pressed sw:in std_logic_vector(17 DOWNTO 0); -- low when pulled down ledg:buffer std_logic_vector(8 DOWNTO 0); -- high active ledr:buffer std_logic_vector(17 DOWNTO 0); -- high active hex0,hex1,hex2,hex3,hex4,hex5,hex6,hex7:out std_logic_vector(0 TO 6); gpio_0:buffer std_logic_vector(35 DOWNTO 0); gpio_1:inout std_logic_vector(35 DOWNTO 0) ); END ENTITY de2_start; ARCHITECTURE rtl_de2_start OF de2_start IS TYPE t_7seg IS ARRAY(0 TO 15) OF std_logic_vector(0 TO 6); CONSTANT c7seg:t_7seg:=(" ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " ", " "); BEGIN gpio_1(17 DOWNTO 0) <= sw; ledr(17 DOWNTO 0) <= sw(17 DOWNTO 0); ledg( 7 DOWNTO 4) <= key(3 DOWNTO 0); ledg( 3 DOWNTO 0) <= key(3 DOWNTO 0); ledg(8) <= sw(0); p_check_hex:process(sw(0)) BEGIN IF sw(0)='0' THEN hex0<=c7seg(0); hex1<=c7seg(1); hex2<=c7seg(2); hex3<=c7seg(3); hex4<=c7seg(4); hex5<=c7seg(5); hex6<=c7seg(6); hex7<=c7seg(7); ELSE hex0<=c7seg(8); hex1<=c7seg(9); hex2<=c7seg(10); hex3<=c7seg(11); hex4<=c7seg(12); hex5<=c7seg(13); hex6<=c7seg(14); hex7<=c7seg(15); END IF; END PROCESS p_check_hex; END ARCHITECTURE rtl_de2_start; CONFIGURATION con_de2_start OF de2_start IS FOR rtl_de2_start END FOR; END CONFIGURATION con_de2_start; So far we have no mapping of signals in the port of entity de2_start to DE2 hardware. Download file DE2_pin_assignments.csv [5] and look into it, e.g. using Notepad++ [7]. Line SW[0],PIN_N25 connects top-level entity signal SW(0) with FPGA package pin N25. Top-level entity signals with names not listed in DE2_pin_assignments.csv will be ignored without error message

13 Connecting the DE2 Hardware: Installing the USB Blaster Connect the DE2 board s USB Blaster Port via USB cable caple to your PC. Set the Run/Prog-Switch on Run, connect the USB-Blaster Port of the Board to an USB slot of your computer. (May be a The New Hardware Wizard appears.) To install the USB-Blaster for a stand-alone computer follow the instructions of tut_initialde2.pdf. (You have to install the usb_blaster by leading the system to path <Quartus_insatallation_directory>\quartus\drivers\usb-blaster.) In the Electronics Laboratory of OTH Regensburg you need to install the USB-Blaster with Quartus II 8.1. Quartus II 13.1 is also available. It is the last Quartus version supporting Cyclone II FPGAs, but it requires admin rights to install the USB blaster. After blaster installation with version 8.1 you can use version 13. Quartus II: Tools Programmer Hardware Setup. Double click left on USB-Blaster until you see this tring in the window Currently selected hardware. Then click Close. In the Programmer s window Hardware setup... you should now see the string USB- Blaster [USB-0]. Within the Programmer you should now see the file de2_start.sof, a binary file obtained by compilation, in a line with activated checkbox Program / Configure. The switch left to the 7-segment displays is set to RUN. Quartus II Programmer Start. You should now get an error message! This is because we must tell Quartus II which hardware has to be programmed! Running the DE2 Hardware doing the Necessary Assiningnments Copy file DE2_pin_assignments.csv [5] or into or your directory with project de2_start or its parent directory. Quartus II: Assignments Device... Family: Cyclone II Device Name: EP2C35F672C6 OK Quartus II: Assignments Pins: You see now the device setting above, but no pin names assigned close window. Quartus II: Processing Start Cmpilation. You should get a successful compilation! Quartus II: Tools Programmer Start. Blue LED LOAD on the DE2 board should turn on for a while and then the LED GOOD. Observe the DE2 boad immediately after pressing Programmer button Start. It should do something. But the programmed board behaves randomly because the pins are not yet assigned. Switching SWx (x=0...17) shouldn t change anything. To improve that: Quartus II: Assignments Import Assignments... <naviage to file>... DE2_pin_assignments.csv Open OK. Quartus II: Assignments Pins: You now see pin map with pins filled. Quartus II: Assignments Assignment Editor: You now see a bitg list of assignments. Compile and program file de2_start.sof into the FPGA. Now switch SWx should enlighten LEDRx (x=0...17) and SW0 should change the 7-segment display. Congratulations! You got it! Your board is ready to be tested now!

14 Commissioning Soft- and Hardware After successful download of file de2_start.sof into the FPGA we want to understand its functionality the VHDL code lines. The statements ledr(17 DOWNTO 0) <= sw(17 DOWNTO 0); ledg( 7 DOWNTO 4) <= key(3 DOWNTO 0); ledg( 3 DOWNTO 0) <= key(3 DOWNTO 0); allow to switch all red LEDs on and off using the toggle switches SW0 SW17 below the respective LEDs LEDR0 LEDR17. Try it! Does it work? Pushbuttons KEY0 KEY3 should allow to switch off the green LEDs LEDG0 LEDG3. When pushing KEY# (# = 0 3), then signal key(#) goes to state LOW... Not only LEDs are driven by the switches, also 18 pins of the expansion header JP2 (=GPIO_1) by line gpio_1(17 DOWNTO 0) <= sw; Which expansion header pin is driven by toggle switch SW0? Pin1 of JP2 (top left)... Exit Quartus II and delete all files exept de2_start.vhd, *.qpf and *.qsf and f*.sof. Use an ASCII editor to look into these files (e.g. with Notepad++ [7]): vhd: ASCII: VHDL file de2_start.vhd with the VHDL code, qpf: ASCII: Quartus Project File de2_start.qpf with project information, qsf: ASCII: Quartus Specification File de2_start.qsf with assignment information, [sof: Binary: de2_start.sof: ready for download in to the FPGA.] Having *.vhd, *.qpf and *.qsf we can easily recompile and get everything else back. There is no need to save the *.sof file, which can be used to program the FPGA without recompilation. Save directory de2_start continaing files de2_start.vhd, de2_start.qpf and de2_start.qsf

15 2.1.4 Using the 7-Segment Display Unfortunately, Quartus II does not support project renaming and copying projects ist tedious. To rename a project we d better create a new one. Copy directory de2_start de2_seg7. Within this new directory de2_seg7 rename file de2_start.vhd de2_seg7.vhd. delete all other files in directory directory de2_seg7, delete all other files in directory directory de2_seg7, Know where file DE2_pin_assignments.csv is located in your directory tee, Start QuartusII Create a New Project select working directory...\de2_seg7, name of the project: de2_seg7, Next click on "..." de2_7seg.vhd Open Add (don t forget to click on Add!) Next Cyclone II EP2C35F672C6 Next Next Finish Assignments Import Assignments (navigate ) DE2_pin_assignments.csv OK. Entity window: open (i.e. click on) de2_seg7. Edit Replace (Ctrl+H) Find: de2_start, Replace all by de2_seg7 Save. Processing Start Compilation Tools Programmer After programming your FPGA watch the 7-segment hexadecimal display, where every hex digit shows its index if SW0='0' or index+8 if SW0='1'. This is caused by the code lines IF sw(0)='0' THEN hex0<=c7seg(0); hex1<=c7seg(1); hex2<=c7seg(2); hex3<=c7seg(3); hex4<=c7seg(4); hex5<=c7seg(5); hex6<=c7seg(6); hex7<=c7seg(7); ELSE hex0<=c7seg(8); hex1<=c7seg(9); hex2<=c7seg(10); hex3<=c7seg(11); hex4<=c7seg(12); hex5<=c7seg(13); hex6<=c7seg(14); hex7<=c7seg(15); END IF; But something is wrong with the hex-displays! What? Repair it using VHDL operator NOT for bit-vectors! (e.g. not_vector <= NOT vector;). Note that hex0, hex1, are vectors. Remember: hex-display segments are driven by low-state! So: invert all driver to 7-segment-display elements: IF sw(0)='0' THEN hex0<=not c7seg(0); hex1<=not c7seg(1); hex2<=not c7seg(2); hex3<=not c7seg(3); hex4<=not c7seg(4); hex5<=not c7seg(5); hex6<=not c7seg(6); hex7<=not c7seg(7); ELSE hex0<=not c7seg(8); hex1<=not c7seg(9); hex2<=not c7seg(10); hex3<=not c7seg(11); hex4<=not c7seg(12); hex5<=not c7seg(13); hex6<=not c7seg(14); hex7<=not c7seg(15); END IF; After repairing the VHDL code save files *.vhd, *.qpf and *.qsf. and delete all other files. Then copy directory de2_seg7 to de2_dac, rename the contained file de2_seg7.vhd to de2_dac.vhd and delete all other files within directory de2_dac. Create project de2_dac with top-level entity de2_dac within directory de2_dac