ET398 LAB 4. Concurrent Statements, Selection and Process

Transcription

1 ET398 LAB 4 Concurrent Statements, Selection and Process Decoders/Multiplexers February 16, 2013 Tiffany Turner

2 OBJECTIVE The objectives of this lab were for us to become more adept at creating VHDL code for basic digital design devices; while demonstrating a more in-depth knowledge using the DE-1 board (Kelly, 2013). PROBLEM STATEMENT: Problem 1: Logic file one: Must use a when/else for the Decoder. Logic file two: Must use a combinational statement for the 4 input OR gate. Hardware file: Inputs must be assigned to switches, all outputs of the decoder must be assigned to 8 Red leds, output of the Or gate must go to green LED. Problem 2: Logic file one: Must use a with/select for the Decoder. Logic file two: Must use a combinational statement for the 3 input OR gate. Hardware file: Inputs must be assigned to switches, all outputs of the decoder must be assigned to red leds. Problem 3: Logic file one: Choose either when/else or with select for the 2 to 1 mux. Hardware file: Inputs to switches, outputs to red leds, Mux logic file must be used 4 times using port maps being careful not to forget to utilize inverters as needed.

3 Problem 4: Logic file one: Choose either when/else or with/select for the diagram. Hardware file: Inputs to switches, outputs to red leds. Include a waveform diagram in your report for this problem; only BCD values should be displayed. All designs were to be implemented using the Altera DE-1 board. (Kelly, 2013) DESIGN METHODOLOGY For Lab 4, there were four different circuits that I was required to write code for and then simulate using my DE-1 board. Among the four circuits, two were decoders and two were multiplexers. The logic requirements for each design varied; below I have discussed the details of each circuit implementation. First of all, a decoder is basically a combinational type logic circuit that converts the binary code data at its input, into one of a number of different output lines, one at a time producing an equivalent decimal code at its output. Binary Decoders have inputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data input lines, and an n-bit decoder has 2 n output lines. Therefore, if a binary decoder receives n inputs (usually grouped as a binary or Boolean number) it activates one and only one of its 2 n outputs based on that input, with all other outputs

4 deactivated. A decoder s output code normally has more bits than its input code, and practical "binary decoder" circuits include 2-to-4, 3-to-8 and 4-to-16 line configurations. A Binary Decoder converts coded inputs into coded outputs, where the input and output codes are different and decoders are available to "decode" either a Binary or BCD input pattern to a Decimal output code. An example of a 3-to-8 line decoder along with its truth table is given below. 3:8 Decoder Octal A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D A 3 to 8 decoder is an IC which activates one of its pins based upon a 3 bit code applied at the input. It consumes a similar amount microcontroller lines (3 in comparison to the parallel-out s 2), but it needs additional microcontroller lines to scale to more than 8 columns. Finally, it does allow for switches to activate external interrupts, but only one column of switches can do this at a time. The programming of this method is relatively straight forward, and it has the advantage of being independent of its previous state.

5 For this circuit, my Octal Decoder logic file from Lab 3 was used to implement the decoder logic portion of my design. However, the type of logic used did differ in Lab 4; a when/else statement was required, rather than a with/select as in Lab 3. The portion of code shown above is the actual logic of my design. As you can see, I implemented a when/else logic statement in order to simulate the first portion of my circuit. As the binary input value changes from 0 to 7, the corresponding output value is outputted. The truth table above shows the corresponding input/output criteria I used to design my decoder logic. For this circuit not only was I to write the code for the actual decoder, but I was also to write code for the OR logic associated with it. A four input OR gate was used to tie into the output data lines 0, 1, 3 and 4. I was required to use combinational logic in order to design the logic file for this portion of my circuit. The combinational logic for this is shown below. The OR logic above takes the 4 desired outputs from my decoder and ORs them together in order to display my final output. While the two logic files are what create the actual simulation of this circuit, they would not be able to perform their functions had it not been for the hardware template; which is used to communicate with the DE-1 board. For the architecture of this circuit, two components were needed rather than just one, due to the two logic file implementations utilized in this design.

6 The components are the hardware assignments according to the various input/output requirements. For the decoder there were 3 inputs (2 downto 0) and 8 outputs (7 downto 0). As for the OR gate, I set all outputs from the decoder to one bus (7 downto 0) and renamed them inputsor in order for the DE-1 board to differentiate between the outputs/inputs. From here I could simply call only the necessary outputs for the OR gate logic (0, 1, 3 and 4). The most important aspect of tying these two files together (in the hardware template) was the usage of a signal. The purpose of the signal implementation was to create a bidirectional data line in order for the outputs of the decoder to act as inputs for the OR gate. Without the signal, this would not be possible because all other assignments were set to either in or out. Above is my port map application for each logic file. The code above clearly shows my signal utilizations. All of my decoder outputs are outputted to the signal, while all of my OR gate inputs are being brought in by the same signal. My final output is simply assigned to one of the green LEDs; LEDG (0). For my second circuit design, I was to simulate one more decoder. This time, however, I was to implement 4 inputs, 16 outputs and 3, 3-input OR gates. Once again, the logic application requirements were to be different from my previous circuit. For the decoder logic a with/select statement was to be used, and for the OR gate logic, combinational logic. 4:16 Decoder

7 Dec A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D For my 4:16 decoder, the logic implemented in my design was very similar to that of my 3:8 decoder. The main difference between the two was the amount of inputs/outputs required. I needed to assign 4 inputs to switches and 16 outputs to a signal, which in turn would be sent to my 3 OR gates. For this circuit I was to use a with/select statement in my decoder logic file. My logic statement is shown below.

8 I declared my inputs as inputsdec and my outputs as outputsdec. With each input value selected using the appropriate switches, the corresponding output value will then be sent to my signal. Only select lines were to be used as inputs for my OR gates (I will discuss this in more detail later on). I assigned both my inputs and outputs to bit vector (buses) in order for their values to be treated as one value. Using the above code, my four input values were read as one value by the DE-1 board; the same went for my output values. Although it was not as necessary for my outputs to be implemented on one single bus for the same reason as my inputs, it was necessary for me to do it this way so that I could then just select which data lines (from this bus) I needed to send to my OR gates. It made things a lot simpler to do it this way. As for my OR gate logic, nothing changed from my previous circuit, aside from how many times this file was called by my hardware file. My inputs from my signal were assigned to a bit vector (2 downto 0) and my final output F was assigned to just standard logic since there was only one bit to be displayed. Seeing how I have two logic files, I needed to implement two components in my hardware file again. My code snapshot below shows this. My last circuit had only one signal, whereas with my second design I utilized two. The reason for this was due to the fact that I needed to call my OR logic file more than once. I needed two

9 different signals to use, one for the first two OR gate implementations and the second for the third OR gate (which was my final output). Port Map The Y signal was used to select only the necessary output data lines (according to the circuit schematic) from the decoder. The outputsor signal was used for the first two OR gate outputs. In the third port map assignment, the outputsor signal is used as the three inputs for the third OR gate. I used the outputsor(1) twice per the schematic diagram. My final output consisted of one bit which was sent to LEDR(0) on the DE-1 board. My last two designs were based on the Multiplexer. A multiplexer, or Mux, is an electronic device which selects from several input signals and transmits one or more output signals. Multiplexers are also referred to as Data Selectors. The simplest of the various Multiplexers is a two input Mux that has two signal inputs, one control input and one output. A very common example of an analog Mux would be the source control on a home stereo unit which allows a user to choose between the audio from a CD player, DVD player or cable television line. Multiplexers also are used in building digital semiconductors such as central processing units (CPUs) as well as graphics controllers. In these applications, the number of inputs is generally a multiple of two, the number of outputs is either one or relatively small multiple of two, and the number of control signals is related to the combined number of inputs and outputs. For example, a two-input, one-output multiplexer requires only one control signal to select the input, and a 16- input, four-output multiplexer requires four control signals to select the input and two to select the output. The first of the two multiplexers I designed consisted of 4 two input Multiplexers which all shared the same select line. The truth table for my two input Mux with one select line is shown below. SEL D F

10 The code for this design was much more straightforward compared to the previous two designs. For instance, I only needed one logic file for the Mux logic, which meant only one component, was declared in my hardware file and no signals were necessary. My logic file was simple and easy to implement. We were allowed to select between a when/else or with/select statement for our logic file, so I chose to utilize the when/else. It seemed to be the simplest in this case. There was only one select line; therefore the code was short and to the point. There was no real magic here, just your modest 2:1 Mux logic. When the select line is low (S1 = 0 ), the input data line to be outputted is D0, and when the select line is high (S1 = 1 ), the input data line to be outputted is D1. None of the outputs or inputs for this design required the use of a bit vector. All 4 were assigned to standard logic. The only tricky part to this lab was the port map implementation in my hardware file. The reason for this was that I needed to call my Mux logic file multiple times (4 to be exact). This design was basically 4 different 2 input Muxs which all shared the same SELECT line. Also, in the schematic there were inverters being used for the second input. All of these design applications were executed in the port map. The NOT before each switch assignment for D0 implies the inversion of the first input D1. The inverters merely do just that, invert the final outputs (when selected).

11 The second Mux and fourth (and final) design was the 8:4 Multiplexer. Essentially, this circuit was to consist of two four bit values and output the corresponding value, according to the single SELECT line. The summarized truth table is shown below. S0 Output 0 A 1 B Beginning with my logic file, I chose to use a when/else statement because it was the easiest for me to piece together considering the required criterion for this design. Basically, I went through all possible BCD values (0-9) for my outputs, using two conditions. One being whether or not my SELECT line ( S0 ) was HIGH or LOW, and two being whatever the input was (relating to A or B, but never both). My logic code is shown below. As for my input/output assignments (or entity), I utilized vectors for everything except my SELECT line. Reasoning behind this was so that my four bit values for both A and B would each be read as one value; also needed my output to be set up the same in order to correctly display the exact corresponding value.

12 Only one logic file was necessary for this design, meaning only one component was declared. The port map assignments for this design were by far the most straightforward of all four designs. Each input was assigned to a specific switch while each output was assigned to a particular red LED. Even though this circuit, at first glance, appeared to be the most complex; it ended up the simplest to design. Port map above shows the pin assignments for each switch and LED. IMPLEMENTATION, TEST CRITERIA and RESULTS: Once the code for each design was written and compiled it was time to implement them utilizing the DE-1 board. After each successful compilation, I would burn the board in order to test my code. For each simulated circuit I would go through the truth tables making sure that my input and output values each corresponded accordingly. My input values were implemented by using the various switches assigned to them, while my outputs were displayed using the red and green LEDs. For this lab, we were not required to test any of our circuits using waveforms except for the last one. All of my circuits were successfully demoed. The one waveform that was required is shown below with related annotations. 8:4 Multiplexer (SELECT = LOW) A is selected All A values are selected and displayed as the outputs Anything over 9 is automatically set to 9, that way only the BCD values are displayed

13 (SELECT = HIGH) B is selected All B values are selected and displayed as the outputs Anything over 9 is Set to 9, so that only BCD values are displayed CONCLUSION: Aside from the fact that I was unable to demo all four of my circuits in lab on Friday, I would consider this lab a success. I was able to successfully write and compile my code later that day in order to upload all of my files and prepare for my next opportunity to demo. Although I had to debug syntax errors on 3 out of 4 of my designs, I feel as though I am finally getting the hang of VHDL after this lab. Especially since my last code was written in notepad, opened up in Quartus and then successfully compiled without any errors. I really enjoyed this lab and all its challenges and look forward to the next.

14 REFERENCES: 1. Digital Fundamentals, Floyd, Prentice Hall, Chapters 1-4 plus appendices 2. Shock and Awe VHDL tutorial, Bryan Mealy 3. TTL Data Book Vol. II, Texas Instruments 4. In class lecture and notes, Kelly, L., ET398