Design Problem 4 Solutions

Transcription

1 CSE 260 Digital Computers: Organization and Logical Design Jon Turner Design Problem 4 Solutions In this problem, you are to design, simulate and implement a maze game on the S3 board, using VHDL. This circuit allows a user to move through a 7x7 maze with the objective of moving from the starting position (0,0) to the finish position (6,6). An example of such a maze is shown in the figure at right. At each step, the S3 board s seven segment display shows the user s (x,y) position on digits 3 and 2 of the display, the user s orientation (0=north, 1=east, 2=south, 3=west) on digit 1 of the display, and a view of the current cell, and the next cell in front (assuming there is no intervening wall) using digit 0. Two example views that might be shown on digit 0 of the display are shown in the upper right part of the figure. Start by implementing a module called maze with inputs clk, reset, left, right and move. The left and right inputs cause the user to turn to the left or 0,0 6,6 wwall(4,1)=1 sample views (3,1) north (4,1) west swall(6,4)=0 right. The move input causes the user to move forward one cell, assuming there is no wall in the way. The outputs of your circuit should include signals xpos and ypos that specify the current position in the maze (these should be specified as 3 bit signals), and a signal direction, that specifies the direction that the user is facing (0 for north, 1 for east, 2 for south, 3 for west). You should also provide a 1 bit signal called error which is asserted if the user attempts to move forward when there is a wall in the way. The error signal should stay asserted until the user performs some other action. To represent the walls of the maze, define a pair of twodimensional constant arrays, swall and wwall. Use swall(x)(y) to represent the south wall of cell (x,y) in the maze. Use wwall(x)(y) to represent the west wall of cell (x,y) in the maze. Use a 1 to indicate the presence of a wall segment and 0 to indicate the absence of a wall segment. Initialize swall and wwall so as to define the maze shown in the figure above. The following VHDL code can be used to declare wwall. Declare swall similarly. type walltype is array (0 to 7) of std_logic_vector(0 to 7 constant wwall: walltype := ( " ", " ", " ", " ", " ", " ", " ", " " You will also need to write a top module that connects to the external signals on the S3 board (use the same ucf file as in design problems 2 and 3), and connects them to the maze component and the other components you will need to use. One of these other components is the debounce circuit that was used in design problem 3. You will also need another component to control the seven segment display. On the web site, you will find a module called displayunit that can be used for this purpose. Combine these components in your top module in order to - 1 -

2 provide the desired functionality. The debounced buttons should be used for the reset and the game control inputs. In particular, use dbtn(3) for reset, dbtn(2) for left, dbtn(1) for move and dbtn(0) for right. You should equip top with logic to detect rising transitions on each of the game control buttons. For example, when dbtn(2) goes from 0 to 1, your circuit should make left high for one clock tick, so that the maze module will respond appropriately (if you just connect dbtn(2) to left, the maze module will see its left input stay high for many clock ticks, causing multiple turns to the left, rather than a single turn). Perform a functional simulation of your circuit that takes at least six steps through the maze, verifying that the left, right and move buttons work correctly and that the outputs from the maze module are correct. Be sure to verify that the error signal works correctly. Your design notes should include block diagrams for both the maze module and the top module. Create a separate project that implements your maze module by itself. Access the synthesis properties by right-clicking on the synthesis line in the Sources sub-window of Project Navigator, and set the optimization goal to Area. Synthesize the circuit and look at the HDL Synthesis section of the synthesis report. Print this section and include it when you hand in your design problem. You will find several lines in this section of the form Found 3-bit adder for signal <$add0034> created at line 93. Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 99. For all the lines that mention adders or comparators, examine the corresponding lines in your VHDL source code. Why are adders and comparators found for these lines? Are there lines in your VHDL source where additions are performed but for which no adders are mentioned in the HDL synthesis section. If so, identify those lines and explain why there are no adders mentioned for those lines. Do the same for comparators. The final part of the problem is to implement your design on one of the S3 boards in the Urbauer lab. Once you have your design on the S3 board, verify that it works by playing the maze game from start to finish, verifying that the values displayed on the S3 board are correct. When you are satisfied, have one of the TAs come into the lab and check it. Be sure to the file containing your VHDL code (please send it as a single file) as an attachment to jon.turner@wustl.edu. Please name your attachment dp4-yourname.vhd, where yourname is your first and last names (e.g. jonturner). Also, a copy of your MCS file, as a second attachment. Note that the last page of this handout is a grading template for the design problem. This should stapled to the front of the assignment when you turn it in, with your name filled in the blank space. When you demonstrate the running design to the TA, make sure he assigns a score and signs in the comment space

3 Design notes for Maze game. This circuit implements a maze game, in which a user moves through a 7x7 maze on the S3 board. The user controls the maze game using the push buttons on the S3 board. Btn(2) causes the user to turn left, btn(1) causes the user to move forward and btn(0) causes the user to turn right. The user s current position in the maze is displayed on digits 3 and 2 of the seven segment display, the user s orientation is shown on digit 1 (0 for north, 1 for east, 2 for south and 3 for west) and a view of the user s current position is shown on digit 0. The LEDs on the board are turned on if the user attempts to move through a wall and they stay on until the user performs a legal move. The circuit requires some static data to represent the maze. The 2d array wwall(i)(j)=1 if there is a wall on the west side of cell (i,j) and 2d array swall(i)(j)=1 if there is a wall on the south side of cell(i,j). The circuit also requires some dynamic state. In particular, it must remember the user s position in the maze and the direction that the user is facing. Position is represented by a pair of registers, xpos and ypos. Direction is represented by a third register, dir. A block diagram of the maze module is shown at right. The blocks labeled wwall and swall represent the two dimensional constant arrays that define the maze. The blocks labeled wselect and sselect are used to select bits from wwall xpos ypos swall wselect sselect wwall(x)(y), wwall(x+1)(y)... =0,=7 x y =0,=7 clr,+,- swall(x)(y), swall(x)(y+1)... clr,+,- Control dir direction left move right error view these arrays that are needed to make various control decisions. These circuits can be implemented using multiplexors to extract the appropriate bits. Adders and subtracters will also be needed to obtain x+1,x+2,x-1,y+1,y+2 and y-1 from x and y. These are not shown explicitly. The blocks labeled x, y and dir are up-down counters with clear inputs. The control block consists of combinational circuitry that uses the selected bits from wwall and swall and the control inputs to generate the output signals and the control signals for the counters

4 A block diagram for the top module is shown at right. The debouncer module takes the buttons as inputs and produces dbtn as an output. The circuit between debouncer and maze detects rising transitions on dbtn(2..0) and generates a one clock tick pulse for each rising transition. This way, each press of the clock triggers one move in the maze game. The error output is connected to all 8 LEDs and the other outputs of the maze game are passed to the display module. The outputs of the display module drive the seven segment display. btn debouncer dbtn(3) dbtn(2..0) D >C mclk reset left move right clk maze xpos, ypos, direction, view error led display an ssg - 4 -

5 VHDL Source Code.. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; package commondefs is constant mazesize: integer := 7; # of rows and columns in maze constant possize: integer := 3; number of bits to represent xy position constant nbtn: integer := 4; number of buttons constant nswt: integer := 8; number of switches constant nled: integer := 8; number of LEDs constant ndig: integer := 4; number of digits constant operationmode: integer := 0; use 0 for sim, 1 for S3 board subtype bigdelay is std_logic_vector(27 downto 0 type displaytype is array(ndig-1 downto 0) of std_logic_vector(7 downto 0 function int(d: std_logic_vector) return integer; Convert logic vector to integer. Handy for array indexing. end package commondefs; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; package body commondefs is function int(d: std_logic_vector) return integer is Convert logic vector to integer. Handy for array indexing. begin return conv_integer(unsigned(d) end function int; end package body commondefs; Maze game Jon Turner - 3/1/2007 This module implements an 8x8 maze. The user starts in position 0,0 of the maze and can move around the maze using the input signals, left, right and move. The left and right signals cause the user to turn to the left or right without changing position. The move signal causes the user to advance one step in the position he/she is facing, assuming there is no wall directly in front of. The outputs include the user's xy position in the maze (xpos, ypos) and orientation (0=north, 1=east, 2=south, 3=west). The output also includes a view of the user's immediate environment, using one digit of the seven segment display. This allows the user to see the walls of the current "cell" and if there is no intervening wall, the next cell in front. There is also an error signal that is asserted if the user attempts to move through a wall of the maze. The error signal remains asserted until the next action by the user. It is assumed that at most one of left, right or move is asserted in any one clock tick

6 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.commondefs.all; entity maze is port( clk, reset: in STD_LOGIC; left, right, move: in std_logic; view : out std_logic_vector(7 downto 0 xpos, ypos : out std_logic_vector(possize-1 downto 0 direction: out std_logic_vector(1 downto 0 error: out std_logic end maze; architecture a1 of maze is Signals that define the maze. wwall(x)(y) defines the west wall of cell (x,y) and swall(x)(y) defines the south wall of cell (x,y) type walltype is array (0 to mazesize) of std_logic_vector(0 to mazesize constant wwall: walltype := ( " ", " ", " ", " ", " ", " ", " ", " " constant swall: walltype := ( " ", " ", " ", " ", " ", " ", " ", " " signal x,y: std_logic_vector(possize-1 downto 0 signal dir: std_logic_vector(1 downto 0 begin xpos <= x(possize-1 downto 0 ypos <= y(possize-1 downto 0 direction <= dir; process (clk,dir,x,y) begin updtate state in response to user actions if rising_edge(clk) then if reset = '1' then x <= (x'range => '0' y <= (y'range => '0' dir <= "00"; error <= '0'; else if left = '1' then dir <= dir - 1; error <= '0'; elsif right = '1' then dir <= dir + 1; error <= '0'; elsif move = '1' then error <= '0'; case dir is when "00" => if y < mazesize-1 and swall(int(x))(int(y+1)) = '0' then y <= y + 1; else error <= '1'; when "01" => if x<mazesize-1 and wwall(int(x+1))(int(y))='0' then x <= x + 1; else error <= '1'; - 6 -

7 when "10" => if y > x"0" and swall(int(x))(int(y)) = '0' then y <= y 1; else error <= '1'; when others => if x > x"0" and wwall(int(x))(int(y)) = '0' then x <= x - 1; else error <= '1'; end case; define view from current position view <= x"00"; case dir is when "00" => view(2) <= wwall(int(x+1))(int(y) view(3) <= swall(int(x))(int(y) view(4) <= wwall(int(x))(int(y) view(6) <= swall(int(x))(int(y+1) if swall(int(x))(int(y+1)) = '0' and y < mazesize-1 then view(0) <= swall(int(x))(int(y+2) view(1) <= wwall(int(x+1))(int(y+1) view(5) <= wwall(int(x))(int(y+1) when "01" => view(2) <= swall(int(x))(int(y) view(3) <= wwall(int(x))(int(y) view(4) <= swall(int(x))(int(y+1) view(6) <= wwall(int(x+1))(int(y) if wwall(int(x+1))(int(y)) = '0' and x < mazesize-1 then view(0) <= wwall(int(x+2))(int(y) view(1) <= swall(int(x+1))(int(y) view(5) <= swall(int(x+1))(int(y+1) when "10" => view(2) <= wwall(int(x))(int(y) view(3) <= swall(int(x))(int(y+1) view(4) <= wwall(int(x+1))(int(y) view(6) <= swall(int(x))(int(y) if swall(int(x))(int(y)) = '0' and y > x"0"then view(0) <= swall(int(x))(int(y-1) view(1) <= wwall(int(x))(int(y-1) view(5) <= wwall(int(x+1))(int(y-1) when others => view(2) <= swall(int(x))(int(y+1) view(3) <= wwall(int(x+1))(int(y) view(4) <= swall(int(x))(int(y) view(6) <= wwall(int(x))(int(y) if wwall(int(x))(int(y)) = '0' and x > x"0"then view(0) <= wwall(int(x-1))(int(y) view(1) <= swall(int(x-1))(int(y+1) view(5) <= swall(int(x-1))(int(y) end case; end process; end a1;

8 Synchronize and de-bounce the push buttons. dbtn is de-bounced version of btn The constant operationmode should be set to 0 for simulation and 1 for use in S3 board. - library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.commondefs.all; entity debouncer is port( clk: in std_logic; btn: in std_logic_vector(nbtn-1 downto 0 dbtn: out std_logic_vector(nbtn-1 downto 0) end debouncer; architecture debarch of debouncer is When operationmode=1, debounceperiod=10^6 which gives a delay of 20 ms for the 50 MHz clock frequency of the S3 board. constant debounceperiod: integer := 3 + operationmode*999997; signal s1btn, s2btn, s3btn: std_logic_vector(nbtn-1 downto 0 signal count: bigdelay; begin process(clk) begin if clk'event and clk = '1' then first synchronize buttons to reduce likelihood of synchronizer failure s1btn <= btn; s2btn <= s1btn; s3btn <= s2btn; transfer new value to dbtn after it has been stable for duration of the de-bounce period if s3btn /= s2btn then count <= (count'range => '0' elsif count < debounceperiod then count <= count + 1; elsif count = debounceperiod then dbtn <= s3btn; count <= count + 1; end process; end debarch; Display unit This module displays values on a seven segment display. It is designed to accept either "raw" inputs or numeric inputs. The display input signal is an array of ndig(=4) values of 8 bits each. If display(i)(7)=1 then display(i) is interpreted as a "raw mode" input and is used to drive the display digit directly. In raw mode, a 1 in a given bit position causes that display segment to be turned on. For each i, diplay(i)(0) corresponds to the a segment on the display, display(i)(1) corresponds to the b segment and so forth. The decimal point on the display is always turned off. If display(i)(7)=0, then display(i) is interpreted as a hex digit to be decoded and then displayed - 8 -

9 The circuit drives the external display using the ssg signal and the an signal. It rotates through the values specified in display, routating through each one every 20 ms. This makes it look like the values are all being displayed continuously. The operationmode constant is used to control the amount of time each digit is displayed. It should be set to 0 for simulation and 1 for use on the S3 board. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.commondefs.all; entity displayunit is port( clk, reset: in STD_LOGIC; display: in displaytype; an : out std_logic_vector(ndig-1 downto 0 ssg: out std_logic_vector(7 downto 0) end displayunit; architecture displayarch of displayunit is These constants control which bits of the displaycnt register are used to select the display digit to display. When operationmode=0, bits 2..(2-nBits+1) select the current digit to be displayed, resulting into a very fast cycling through the values. When operationmode=1, bits 19..(19-nBits+1) select the current digit. This causes all four digits to be displayed once every 20 ms. constant nbits: integer := 2; constant displaycntbits: integer := nbits + operationmode*(19-nbits signal displaycnt: bigdelay; function ssdecode(digit: std_logic_vector(3 downto 0)) return std_logic_vector is Seven segment display decoder. The output produced specifies the segments on the display to light in order to display a hexadecimal digit for input value. variable result: std_logic_vector(7 downto 0 begin case digit is when x"0" => result := x"c0"; b" " when x"1" => result := x"f9"; b" " when x"2" => result := x"a4"; b" " when x"3" => result := x"b0"; b" " when x"4" => result := x"99"; b" " when x"5" => result := x"92"; b" " when x"6" => result := x"82"; b" " when x"7" => result := x"f8"; b" " when x"8" => result := x"80"; b" " when x"9" => result := x"90"; b" " when x"a" => result := x"88"; b" " when x"b" => result := x"83"; b" " when x"c" => result := x"c6"; b" " when x"d" => result := x"a1"; b" " when x"e" => result := x"86"; b" " when others => result := x"8e"; b" " - 9 -

10 end case; return result; end function; begin process (clk,display,displaycnt) begin displaycnt process just increments counter on each clock tick if clk'event and clk = '1' then displaycnt <= displaycnt + 1; if reset = '1' then displaycnt <= (displaycnt'range => '0' display each of the display digits an <= (an'range => '1' for i in 0 to ndig-1 loop when the relevant bits of displaycnt=i, display(i) is used to drive the seven segment display signal (ssg) and the corresponding enable (an(i)) is turned on. if int(displaycnt(displaycntbits downto displaycntbits-(nbits-1))) = i then if display(i)(7) = '1' then ssg <= '1' & (not (display(i)(6 downto 0)) else ssg <= ssdecode(display(i)(3 downto 0) an(i) <= '0'; end loop; end process; end displayarch; Top module Defines the connections among the various components and the connections between the external pins provided by the S3 board and the corresponding internal signals. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.commondefs.all; entity top is port( mclk: in STD_LOGIC; btn: in std_logic_vector(nbtn-1 downto 0 swt : in std_logic_vector(nswt-1 downto 0 led : out std_logic_vector(nled-1 downto 0 an : out std_logic_vector(ndig-1 downto 0 ssg: out std_logic_vector(7 downto 0) end top; architecture toparch of top is component maze port( clk, reset: in STD_LOGIC; left, right, move: in std_logic; view : out std_logic_vector(7 downto 0 xpos, ypos : out std_logic_vector(possize-1 downto 0 direction: out std_logic_vector(1 downto

11 error: out std_logic end component; component debouncer port( clk: in std_logic; btn: in std_logic_vector(nbtn-1 downto 0 dbtn: out std_logic_vector(nbtn-1 downto 0) end component; component displayunit port( clk, reset: in STD_LOGIC; display: in displaytype; an : out std_logic_vector(ndig-1 downto 0 ssg: out std_logic_vector(7 downto 0) end component; signal reset, error: STD_LOGIC; signal dbtn, prev_dbtn: std_logic_vector(nbtn-1 downto 0 signal left, right, move: std_logic; signal xpos, ypos: std_logic_vector(possize-1 downto 0 signal dir: std_logic_vector(1 downto 0 signal view: std_logic_vector(7 downto 0 signal display: displaytype; begin debc: debouncer port map(mclk, btn, dbtn process(mclk,error) begin prev_dbtn is the value of dbtn from previous clock tick if rising_edge(mclk) then prev_dbtn <= dbtn; turn on all the LEDs when the user attempts an illegal move for i in 0 to nled-1 loop led(i) <= error; end loop; end process; reset <= dbtn(3 generate single clock tick pulse for left, move and right whenever corresponding button is pressed left <= (not prev_dbtn(2)) and dbtn(2 move <= (not prev_dbtn(1)) and dbtn(1 right <= (not prev_dbtn(0)) and dbtn(0 mazc: maze port map(mclk,reset,left,right,move,view,xpos,ypos,dir,error Associate xpos with display digit 3, ypos with digit 2, dir with display digit 1 and users current view of the maze with digit 0. Note that bit 7 of display(0) is set to 1, since we need to use "raw mode" for this position. display(3)(7 downto possize) <= (others => '0' display(3)(possize-1 downto 0) <= xpos; display(2)(7 downto possize) <= (others => '0' display(2)(possize-1 downto 0) <= ypos; display(1) <= "000000" & dir; display(0) <= '1' & view(6 downto 0 dispc: displayunit port map(mclk, reset, display, an, ssg end toparch;

12 Simulation. The first section of the simulation shown below shows the circuit being reset and the first move. It also shows how the values of xpos, ypos, dir and view are correctly reflected in the seven segment display. btn(3) produces reset ypos changes with move initial views are ssg reflects xpos (C0), ypos (f9), dir (C0), view (af)

13 The next two sections of the simulation are zoomed out to better show the sequence of moves. The first shows how the position and direction variables change in response to the specified operations. It also shows how the error signal is triggered when the user attempts to move through a wall. The last part of correct updating position and direction in response to actions error when attempting to move through wall correct updating position and direction in response to actions views the simulation also shows proper updating of the state variables and the view diagrams at the bottom can be used to check the values of the view signal

14 Synthesis Report. The HDL Synthesis section of the synthesis report is shown below. After each line that refers to an adder or comparator, the corresponding line of the VHDL source code has been inserted, along with a comment. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit <maze>. Related source file is "C:/260designs/sequential/vhdlAM/mazeSA/maze.vhd". Found 8x16-bit ROM for signal <$rom0000>. Found 8x16-bit ROM for signal <$rom0001>. Found 8x8-bit ROM for signal <$mux0012> created at line 134. Found 8x16-bit ROM for signal <$rom0002>. Found 7-bit 4-to-1 multiplexer for signal <view<6:0>>. Found 1-bit register for signal <error>. Found 3-bit adder for signal <$add0007> created at line 124. view(0) <= swall(int(x))(int(y+2) the adder is needed to produce the signal y+2; this is first place in the source code where y+2 appears. Found 3-bit adder for signal <$add0017> created at line 134. view(0) <= wwall(int(x+2))(int(y) the adder is needed to produce the signal x+2; this is first place in the source code where x+2 appears. Found 3-bit adder for signal <$add0033> created at line 87. if y < mazesize-1 and swall(int(x))(int(y+1)) = '0' then the adder is needed to produce the signal y+1; this is first place in the source code where y+1 appears. Found 3-bit adder for signal <$add0034> created at line 93. if x < mazesize-1 and wwall(int(x+1))(int(y)) = '0' then the adder is needed to produce the signal x+1; this is first place in the source code where x+1 appears. Found 4-bit comparator greater for signal <$cmp_gt0000> created at line 99. if y > x"0" and swall(int(x))(int(y)) = '0' then the comparator is needed to compare y to 0; this is first place in the source code where y>0 appears. Found 4-bit comparator greater for signal <$cmp_gt0001> created at line 153. if wwall(int(x))(int(y)) = '0' and x > x"0"then the comparator is needed to compare x to 0; this is first place in the source code where x>0 appears. Found 4-bit comparator less for signal <$cmp_lt0000> created at line 87. if y < mazesize-1 and swall(int(x))(int(y+1)) = '0' then the comparator is needed to compare y to mazesize-1 this is use of y<mazesize-1. Found 4-bit comparator less for signal <$cmp_lt0001> created at line 133. if x < mazesize-1 and wwall(int(x+1))(int(y)) = '0' then the comparator is needed to compare x to mazesize-1 this is use of x<mazesize-1. Found 1-bit 8-to-1 multiplexer for signal <$mux0001> created at line 87. Found 1-bit 8-to-1 multiplexer for signal <$mux0003> created at line 93. Found 1-bit 8-to-1 multiplexer for signal <$mux0005> created at line 99. Found 1-bit 8-to-1 multiplexer for signal <$mux0007> created at line 105. Found 1-bit 4-to-1 multiplexer for signal <$mux0028> created at line 85. Found 3-bit 4-to-1 multiplexer for signal <$mux0029> created at line 85. Found 1-bit 8-to-1 multiplexer for signal <$mux0031> created at line 124. Found 1-bit 8-to-1 multiplexer for signal <$mux0032> created at line 134. Found 1-bit 8-to-1 multiplexer for signal <$mux0033> created at line 144. Found 1-bit 8-to-1 multiplexer for signal <$mux0034> created at line 154. Found 1-bit 8-to-1 multiplexer for signal <$mux0039> created at line 125. Found 1-bit 8-to-1 multiplexer for signal <$mux0040> created at line 135. Found 1-bit 8-to-1 multiplexer for signal <$mux0041> created at line 145. Found 1-bit 8-to-1 multiplexer for signal <$mux0042> created at line 155. Found 1-bit 8-to-1 multiplexer for signal <$mux0047> created at line 126. Found 1-bit 8-to-1 multiplexer for signal <$mux0048> created at line 136. Found 1-bit 8-to-1 multiplexer for signal <$mux0049> created at line 146. Found 1-bit 8-to-1 multiplexer for signal <$mux0050> created at line 156. Found 3-bit subtractor for signal <$sub0009> created at line 144. Found 3-bit subtractor for signal <$sub0010> created at line 154. Found 2-bit updown counter for signal <dir>. Found 3-bit register for signal <x>

15 Found 3-bit register for signal <y>. Summary: inferred 4 ROM(s). inferred 1 Counter(s). inferred 7 D-type flip-flop(s). inferred 6 Adder/Subtractor(s). inferred 4 Comparator(s). inferred 27 Multiplexer(s). Unit <maze> synthesized. There are many other lines in the VHDL that refer to the sums x+1,x+2,y+1,y+2 but only one adder is generated for each unique expression, and then the outputs from these adders are used to implement the logic for all the VHDL statements in which the expressions appear. x and y are also compared to 0 and mazesize-1 at other places in the source code, but only one comparator is generated for each unique comparison