Combinational Logic Gates

Transcription

1 Combinational Logic Gates Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author

2 Topics Combinational logic functions Static complementary logic gate structures Modern VLSI Design: Chap3 2of 19

3 Combinational logic expressions Combinational logic: function value is a combination of function arguments A logic gate implements a particular logic function Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic Modern VLSI Design: Chap3 3of 19

4 Gate design Why designing gates for logic functions is nontrivial: vmay not have logic gates in the library for all logic expressions va logic expression may map into gates that consume a lot of area, delay, or power Modern VLSI Design: Chap3 4of 19

5 Boolean algebra terminology Function: f = a b + ab a is a variable; a and a are literals ab is a term A function is irredundant if no literal can be removed with changing its truth value v Completely testable v Optimum circuit is surely irredundant Modern VLSI Design: Chap3 5of 19

6 Completeness A set of functions f1, f2,... is complete iffevery Boolean function can be generated by a combination of the functions NAND is a complete set v NOR is a complete set v {AND, OR, NOT} is not complete Transmission gates are not complete v Transmission gate + NOT (CMOS) is complete If your set of logic gates is not complete, you can t design arbitrary logic Modern VLSI Design: Chap3 6of 19

7 Topics Combinational logic functions Static complementary logic gate structures Modern VLSI Design: Chap3 7of 19

8 Static complementary gates Complementary: have complementary pullup (p-type) and pulldown(ntype) networks Static: do not rely on stored charge v Simple v Effective v Reliable v hence ubiquitous Functionality does not depend on size Varying size leads to varying v Power v Area v Speed v Modern VLSI Design: Chap3 8of 19

9 Static complementary gate structure Pullup and pulldown networks: V DD inputs pullup network pulldown network V SS Modern VLSI Design: Chap3 9of 19

10 Inverter + a Modern VLSI Design: Chap3 10 of 19

11 Inverter lay + VDD transistors a tub ties a (tubs not shown) GND transistors Modern VLSI Design: Chap3 11 of 19

12 NAND gate Pulldown: v f = (a b) Pullup: v f = a + b A B A B Vdd Gnd Modern VLSI Design: Chap3 12 of 19

13 NAND lay VDD + b a tub ties b GND a Modern VLSI Design: Chap3 13 of 19

14 NOR gate Pulldown: v f = (a + b) Pullup: v f = a b A B A B Vdd Gnd Modern VLSI Design: Chap3 14 of 19

15 NOR lay b VDD a tub ties b GND a Modern VLSI Design: Chap3 15 of 19

16 AOI/OAI gates AOI = and/or/invert OAI = or/and/invert. Implement larger functions Pullup and pulldownnetworks are compact: v Smaller area v Higher speed than NAND/NOR network equivalents AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert. Modern VLSI Design: Chap3 16 of 19

17 AOI example = [ab+c] : symbol invert circuit or and Modern VLSI Design: Chap3 17 of 19

18 Pullup/pulldown network design Pullup and pulldown networks are duals 0s and 1s in truth table correspond to pulldown and pullup networks, respectively To design one gate, first design one network, then compute dual to get other network Example: design network which pulls down when put should be 0, then find dual to get pullup network Modern VLSI Design: Chap3 18 of 19

19 Dual network construction a a b b c c dummy dummy Modern VLSI Design: Chap3 19 of 19