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1 STATE-OF-THE-ART 3D INTEGRATION GAN HUI, STEVEN OUTLINE Introduction about IMEC Application Areas Driven 3D Integration 3D Integration Technology Conclusions 1

2 IMEC Established by state government of Flanders in Belgium Non-profit organization Initial investment: 62M Initial staff: ~ World-leading research in nanoelectronics Revenue: 275 M (incl. 44 M grant from Flanders government) Staff: >1750worldwide Worldwide collaboration >600 companies IMEC CAMPUS FAB 2 3,200 m 2 Clean Room 300 mm pilot line Ball Room, Clean sub-fab Continuous operation: 24hrs / 7 days FAB 1 4,800 m 2 Clean Room 1,750 m 2 Class mm pilot line Continuous operation: 24hrs / 7 days Total: 8,000 m 2 Clean Room 2

3 One of the world s most advanced state-of-the-art research facilities Fully operational since July 2006 (~ 500M ) IMEC IN THE WORLD imec the Netherlands imec office US imec Belgium imec China imec office Japan imec Taiwan Region IMEC the Netherlands: Research Organization in Eindhoven Part of Holst Centre 3

4 IMEC S TOTAL REVENUE Total revenue (P&L), in million euro Grant from the Goverment of Flanders, in million euro ABOUT 60 REGIONS UNDER ONE ROOF foreign regions; 999 Belgian (January 2010) TOTAL STAFF: >1775 INCL. 521 RESIDENTS Belgians Albania Algeria Austria Brazil Bulgaria Canada Chili China Colombia Czechia Egypt Finland France Georgia Germany Great Britain Greece Guatemala Hungaria India Iran Iraq Ireland Israel Italy Ivory Coast Japan Korea Lithuania Malaysia Mexico Moldova Nepal Nicaragua Nigeria Pakistan Poland Portugal Romania Russia Serbia/Montenegro Singapore Slovakia South Africa Spain Sudan Sweden Switzerland Taiwan The Netherlands Tunisia Turkey U.S.A. Ukrainia Uzbekistan Venezuela Vietnam 4

5 RESEARCH CHALLENGE Need for research has never been as high Cost of research Continuous need for new materials and new processing techniques Total R&D cost vs. technology node, relative to 0.25mm, Source: TSMC PARTNERING FOR COST-EFFECTIVE RESEARCH Logic IC Memory IC Equipment Suppliers Universities Centralized Research Build critical Platform mass World-wide Share R&D Center of Excellence costs Material Suppliers Software suppliers Regional Government Europe 5

6 BUSINESS LINES IMEC CORE CMOS Lithography Logic DRAM devices Interconnects IMEC CMORE SiGe MEMS Silicon photonics HUMAN++ Wearable and implantable body area networks (with Holst Centre) IMEC ENERGY Photovoltaics IMEC SMART SYSTEMS Power-efficient green radios Vision systems 3D integration Flash memories Vision systems Power devices and mixedsignal technologies Life sciences GN GaN power electronics and LEDs Large-area electronics and systems-in-foil (with Holst Centre) Emerging devices INSITE connecting technology and system design GaN power electronics and LEDs Wireless autonomous transducer solutions (with Holst Centre) STATE-OF-THE-ART 3D INTEGRATION APPLICATION AREAS DRIVING 3D INTEGRATION 6

7 APPLICATION AREAS DRIVING 3D INTEGRATION Mobile consumer Memory stacking High Performance computing Microsystem Integration MOBILE CONSUMER ELECTRONICS Modem 2G GSM/GPRS/EDGE 3G CDMA2000/EV-HDO HSPA/WCDMA 4G LTE Power Management RF Multimedia >30MP Camera Video encoding/decoding 2D/3D gaming Audio Low power >1 GHz/1V Quadcore CPU Memory 256gB NVM >8gb DRAM Low cost 7

8 3D FOR MOBILE CONSUMER APPLICATIONS Memory/logic IC stacks Increase memory bandwidth Maintaining low power ency (Mhz) Analog-logic stacks GB/s GDDR5 GDDR3 DDR3 LPDDR2 LPDDR1 Heterogeneous technology choices Time-to-market Reuse/Adapt device solutions in adjacent market segments telematics tracking IO frequ D stack IO count Low parallelism High parallelism Game smartbooks M2M routers Set-top box ebook HIGH DENSITY MEMORY STACKS Heterogeneous Memory Stack In use today: Wire-bonded die stack Not suitable for 3D- TSV die stacking Low speed & low I/O: today: Wire-bonded die stack Strongly cost driven Homogeneous Memory Stack High speed wide bandwidth & large # tiers 3D-TSV is enabling technology Repartitioned Memory stack & Logic and I/O circuits 3D-TSV is enabling technology Efficient use of scaled memory and scaled logic technologies 3D-TSV inside applications 8

9 HIGH PERFORMANCE APPLICATIONS Very High Memory bandwidth requirement Die stacking driver Very high power processor devices: y (Mhz) IO frequenc Thermal constraints limit memory on logic stacking Use of 3D SI Interposer substrates DRAM Mobile 12.8GB/s GDDR5 GDDR3 DDR3 LPDDR2 LP DDR1 Graphics 512GB/s 16XGDD R3x1Gb Mobile Wide IO IO count Logic DRAM Logic I/O MICROSYSTEM INTEGRATION Combining advanced logic and memory technologies with heterogeneous device technologies such as analog, sensor, actuator, MEMS,... e.g. 3D detector array systems: Sensor array Analog/Digital read-out array CMOS Digital Signal processing Often: Lower volume products Reuse of standard IC s Mainly : 3D TSV processing after device fabrication Use of Si-interposers ( MCM s ) 9

10 3D integration technology: BRIDGE BETWEEN MORE MOORE AND MORE THAN MOORE 3D INTEGRATION TECHNOLOGY: BRIDGE BETWEEN MORE MOORE AND MORE THAN MOORE Combining the benefits of scaling (density/performance) and alternate device technologies such as analog, high voltage, MEMS,... By optimization across technologies, cost effective solutions can be obtained 10

11 REQUIREMENTS FOR THE SUCCESS OF 3D INTEGRATION 3D Definitions, Roadmaps 3D-Design D tools & Design methodology for 3D 3D Technology 3D-Die stacking Packaging for 3D Yield 3D KGD for 3D 3D-Test strategies Supply Chain & Standardization IMEC 3D SYSTEM INTEGRATION PROGRAM Technology TSV technology Wafer thinning and backside processing D2W stacking technologies Packaging 3D-Die stacks Design Wafer Ø Cu TSV Ø Si Via height Cu Aspect ratio TSV min-pitch 3D system exploration Path finding IP for 3D integration : 3D memory, 3D-NOC Design for 3D integration Cost modeling Demonstration: design and fabrication 200 mm 5µm 25 µm 5:1 10 µm 3D-SIC 300 mm 5µm 50 µm 10:1 10 µm 130nm on 200 mm, 65nm to 22nm on 300 mm, CMOS 3D logic-on-logic, DRAM-on-logic, heterogeneous stacking 3D-WLP 200 mm 25 µm 50 µm 2:1 50 µm 11

12 IMEC 3D-SIC TSV TECHNOLOGY Key features : Realization of a Cu-nail after FEOL, before of BEOL High aspect ratio Cu damascene technique Single litho-step Current Cu-nail Ø = 5 µm, scaling down to 2 µm Aspect ratio s via Ø /depth studied: 1:5 and 1:10 5μm 25-26μm Si 10µm 3D INTEGRATION PROCESS FLOW IC fabrication line Wafer Thinning module Wafer edge conditioning Temporary bonding to a Si-Carrier wafer Wafer thinning Backside processing 3D-SIC via middle Si FEOL Cu nail Si FEOL Cu nail exposure & backside passivation 3D-WLP via last Standard device wafer Backside TSV process Backside redistribution layer & Cu or Cu/Sn µbump 3D-Stacking process Cu-Cu bonding or Cu/Sn µbump solder bonding 12

13 PROCESSES FOR THINNING AND HANDLING OF 3D TSV WAFERS Si (LSI) wafer Si carrier wafer Edge trim wafer Particle cleaning Temporary glue layer coating Wafer to Carrier bonding Wafer thinning by grinding Grinding damage removal (Wet/dry/CMP) and cleaning Thin wafer backside process 3D-SIC or 3D-WLP TSV process Wafer / carrier debonding clean & recycle carrier Dicing thin wafer on tape Particle clean 3D stacking Picture backside 3D-SIC TSV wafer after thinning and Si-recess etching 13

14 3D-WLP, VIA LAST, BACKSIDE TSV TSVs using a polymer liner: Low Capacitance Thermal cycling 1000 cycles -40 C/150 C : no failures Low aspect ratio TSV (AR<1) High aspect ratio TSV (AR 2-3) Sn Kelvin TSV Resistance (mohm) Si Polymer point Kelvin test structures Sample number Kelvin TSV resistance (mohm) point Kelvin test structures Sample number 3D STACKING APPROACHES Die-to-wafer bonding approach: fast and accurate pickand-place step, followed by collective bonding. Cu/Sn µbump bonding: - Cu/Sn Transient-Liquid-Phase, TLP, (250 C) - diffusion bonding (150 C) - Pitch Scaling : µm - Bump planarisation Cu/Cu bonding : - High T Thermo-compression bonding - Low T Cu/Cu insertion bonding Cu oxide removal & prevention No-flow & wafer-level, pre-applied underfill 14

15 HYBRID D2W BONDING: Fast D2W placement + WL collective bonding BEOL BEOL BEOL Si Cu pad BEOL Cu nail polymer Si Cu pad BEOL Cu nail polymer Si Cu pad BEOL Cu nail polymer Si Si Si Cu nail No polymer polymer landing pad Polymer Dot Pattern 15

16 3D-130C stacked circuit demonstration IMEC 130nm CMOS 2 metal layers platform technology 3D-SIC TSV: Ø 5µm, AR 5:1 D2W collective Cu/Cu bonding Pads 12 on top layer 7 on bottom layer TOP BOTTO M 3D NOC test circuit: Two layer stack using 100 TSVs Memory Traffic Generator Switch Switch Via Control/Readout TSV bundle 36 x 2 NoC 4 x JTAG 1 x 3 plane ID 2 x 6 VDD/GND = 100 vias 10um Top tier Top tier Bottom tier 5um 25um Cu-Cu bonding Cu-Cu bonding RO Power [µw/stage] TSV R ~20mΩ; C ~40fF (depletion) TSV leakage << 1nA TSV Breakdown voltage > 100V Cascaded 3D ROs: measurements confirm values of TSV R and C 60 2D RO 41_ref 50 2D RO 21_ref 40 3D RO 41 TSV 30 3D RO 21 TSV Symbols: measured 20 lines: simulation (Spectre) RO Delay [ps/stage] 16

17 CONCLUSIONS 3D-System integration technologies are well suited to realize high integration density and high performance heterogeneous systems. System-level requirements define the required 3D integration technology Main 3D-TSV technology areas: 3D-SIC, via middle TSV, for highest density 3D-stacking 3D-WLP, via last TSV, for post-fab TSV s for microsystem integration Silicon interposers with TSV connections for high performance applications 3D-Integration technology has three key components: TSV technology Wafer thinning and thin wafer handling technology Micro-bump interconnect technology for 3D stacking 17