A MADI-based Design For CD Audio Routing

Transcription

1 A MADI-based Design For CD Audio Routing by WINSTON WONG Department of Computer Science and Electrical Engineering, The University of Queensland Submitted for the degree of Bachelor of Engineering (Honours) in the division of Computer Systems Engineering OCTOBER 1998

2 The Dean School of Engineering The University of Queensland St Lucia, Q Maisie Pl Eight Mile Plains, Q 4113 Tel: October 1998 Dear Professor John Simmons, In accordance with the requirements of the degree of Bachelor of Engineering (Honours) in the division of Computer Systems Engineering, I present the following thesis entitled A MADI-based Design For CD Audio Routing. This work was performed under the supervision of Mr Geoff Walker. I declare that the work submitted in this thesis is my own, except as acknowledged in the text and footnotes, and has not been previously submitted for a degree at The University of Queensland or any other institution. Yours sincerely, WINSTON WONG ii

3 Acknowledgments I would like to thank Mr Geoff Walker for his continued support and boundless patience in the supervision of my work on this thesis. Much thanks also goes to the encouragement and moral support of friends and colleagues during the year. Lastly, I would like to acknowledge the constant guidance of my Lord throughout the struggle. iii

4 Abstract The MADI (multi-channel audio digital interface) standard was conceived to act as a bridge between multitrack recorders and mixing consoles which tended to be incompatible as their respective manufacturers employed varying formats. It was designed to carry up to 56 channels of digital audio using a multiplexing scheme to transmit the data using one very high bit rate serial stream. MADI has since found use in routing and distributing applications, and it is this aspect that this thesis looks at. The thesis topic is to design a MADI based routing system to deliver music from a bank of CD outputs, giving the receiver a choice from up to 28 stereo signals to select for playback. The initial design would only feature one signal source and one receiver, but future extensions have been accounted for in the design. A preliminary design specification based in part on similar previous work is presented, and can be readily translated for implementation with a little more detailed design for some controller sections. Applications for the work presented and suggestions for future work are also given. iv

5 Contents ACKNOWLEDGMENTS ABSTRACT CONTENTS LIST OF FIGURES III IV V VII CHAPTER 1 1 INTRODUCTION Aims of the Thesis Overview of the Thesis 2 CHAPTER 2 3 LITERATURE REVIEW Digital Audio Transmission MADI: Employment History 5 CHAPTER 3 9 THEORY Overview of MADI Frame and Channel Data Formats Maintaining a Constant Data Bit Rate The TAXIchips 13 CHAPTER 4 16 DESIGN Functional Overview Data Acquisition 18 v

6 4.3 Formatting the Channel Data Multiplexing Into the TAXI Transmitter Transmission medium Demultiplexing the Received Data Extracting the Required Channel s Audio 25 CHAPTER 5 27 IMPLEMENTATION Availability of Design Files Multiplexer Modifications Demultiplexer Modifications Audio Data Extractor Modifications Validation of Design Entry 3 CHAPTER 6 32 CONCLUSIONS Summary and Conclusions Possible Future Work 33 BIBLIOGRAPHY 34 vi

7 List of Figures 2.1: AES/MADI coder : MADI/AES decoder : Routing MADI with a TDM parallel bus system : Overview diagram of MADI : MADI frame format : MADI channel data format : TAXI chipset overview : Block diagram of Am7968 TAXI transmitter : Block diagram of Am7969 TAXI receiver : Functional block diagram of system : CD output timing diagram Extraction of left and right channel data MADI channel data registers bit multiplexed transmitter circuit : Coaxial cable interface : Circuit for cascaded data with one TAXI receive : Audio signal extraction circuitry vii

8 Chapter 1 Introduction The term MADI is an acronym for Multi-channel Audio Digital Interface. It was originally proposed by a joint working group of representatives from Sony, Mitsubishi, Neve and SSL (Solid State Logic), for the specific purpose of acting as a standard digital connection between multitrack recorders (such as manufactured by Neve and SSL) and mixing consoles (of which Sony and Mitsubishi were manufacturers for the two leading and opposing formats). Interfacing such equipment tended to be an expensive and difficult proposition due to the incompatible formats used by the major players in the market. However, MADI has also since found applications in the routing and distribution of digital audio signals, such as required in studios and broadcast environments. The standard provides for the unidirectional point-to-point conveyance of up to 56 channels of digital audio using either 75-ohm coaxial cable or fibre-optic cable for the audio data, along with a separate connection for synchronisation signals. This serial transmission link necessarily has a very high data rate, and a feature of MADI is that the data bit rate is kept constant regardless of the number of active channels or the sampling rates of the audio on the active channels. The actual data transmission utilises hardware for an existing computer interface system called FDDI (Fibre Data Distributed Interface), which is capable of carrying up to 1 Mbits/sec of user data at a transmission rate of 125 Mbits/sec. The higher transmission rate is due to the use of the 4B/5B encoding scheme, which allows the addition of error detection and commands to control the receiving hardware. The chip set used is the TAXIchips, (Transparent Asynchronous Transmitter/Receiver Interface) produced by AMD (Advanced Micro Devices). With the production rights to the backbone of MADI belong to an independent party, protection from any proprietary claims to the interface standard is guaranteed. 1

9 1.1 Aims of the Thesis Although it has been a decade since its inception, there have been surprisingly few documented cases of the usage of MADI in the audio industry. Two published cases involve the Swiss Broadcasting Corporation [1] and the British Broadcasting Corporation [2], the latter being an experimental venture. The purpose of this thesis is to design and produce a simple, low-cost implementation of the MADI link to distribute audio output from a centralised source of signals, eg. CD player(s). The design will make use of the TAXI (Transparent Asynchronous Xmitter-Receiver Interface) transceiver chips, and incorporate multiplexing and demultiplexing units (at the transmitter and receiver ends respectively) to translate between the parallel input/output sources and the serial transmission link. Such a system can realise immediate utilisation in situations such as radio broadcasting. 1.2 Overview of the Thesis Chapter one gives an introduction to the topic of MADI and establishes the topic of the thesis. Past work and development in the area are presented and discussed in chapter two, which also looks at some alternatives to MADI. Chapter summarises the relevant sections of the MADI specification and provides the background theory for the MADI transmission link and the data it carries, as well as the TAXIchips that will be used to transmit and receive the data bits. The actual design of this CD audio routing system is developed and explained in chapter four, and the work achieved thus far is summarised in the conclusion in chapter five. 2

10 Chapter 2 Literature Review Although it has been a decade since its inception, there have been surprisingly few documented cases of the usage of MADI in the audio industry. Two published cases involve the Swiss Broadcasting Corporation [1] and the British Broadcasting Corporation [2], the latter being an experimental venture. The topic also manages to avoid any meaningful discussion or coverage in texts by most authors, with possibly the only exception being Watkinson [3] (pp ). Following a successful public demonstration of MADI at the March 1988 AES (Audio Engineering Society) Show, MADI was ratified as both an AES and ANSI (American National Standards Institute) standard. Hence standards documents giving the specification for MADI are available, as well as supplementary information such as engineering guidelines and recommended practices for using MADI. The content of these documents will be covered in more detail in the next chapter. 2.1 Digital Audio Transmission In comparing MADI to other methods for the routing and distribution of digital audio, Cutmore, Crowe and Marsden [2] discuss the leading contenders, while Caine [4] presents system issues concerning AES/EBU digital audio in particular. A summary of their findings is given below. The major standard in use for coding and transmitting signals in the digital domain is the AES/EBU format, developed by the AES in close liaison with the EBU (European Broadcasting Union) and the SMPTE (Society of Motion Pictures and Television Engineers). This format has gained widespread acceptance due to its provision for 3

11 including, along with the audio data bitstream, additional user or interface related information for editing or other purposes. One method for the routing/distribution of such signals is using cross-point, or spacedivision multiplexing. This method uses one transmission link for each audio channel, and makes selections using cross-points in a matrix. Although simple and relatively easy to implement, this method encounters several problems in needing to redefine the signal level and waveform in order to preserve signal integrity. This can be alleviated using digital buffer circuits to restore signal amplitudes and perhaps retime signal edges. Another problem is such a system s inability to pass asynchronous signals of any frequency, which can result in corrupted audio samples leading to equipment losing lock with the signal. A reframer is then required to keep the output bitstream intact. In a synchronous environment, the problems inherent in the above method can be avoided by employing a TDM (Time-Division Multiplexing) approach. In this method, the input signals are first digitised and then time-multiplexed onto the one parallel bus, from which any device wanting to read a particular signal simply loads the data on the bus during the appropriate clock cycle. This system offers unrestricted access to a selection from hundreds of source signals. Thus the need for a cross-point switch is removed, resulting in significant price advantages, especially for systems of increasing size. Parallel bus systems such as that described above have traditionally been preferred over serial transmission systems due to the faster data transfer rates inherent in a parallel link. Although parallel systems require multiple conductors, the number of which increases with the size of the data to be transmitted, serial systems utilising a single conductor have not been able to compete due to a lack of bandwidth and thus transfer rate capability. However, a feasible time-division multiplexing approach to digital audio routing using a serial bus is available in MADI, which is based on the high bit-rates achievable with the computer data standard of FDDI. Where the normal TDM approach uses a local high speed parallel bus with onboard converters acting as a central switching point, the high speed bus of MADI is a single serial signal which can run to 5m on coaxial cable or several kilometres on fibre, with converters located at the 4

12 receiver end of the bus. Thus the addition of new destinations is simply a matter of tapping into the nearest convenient point in the distribution network. Another serial bus method is based upon the ring network topology as used in computer networks. In this approach the serial data bitstream is produced by one node in the network and fed to the next node, which retrieves from the multiplexed bitstream those signals it requires and then passes the entire bitstream to the next node, and so on around the network. The obvious drawback of such an approach is that should one node fail, all subsequent nodes will be affected. While this can be countered by the use of two loops, timing difficulties arise, and it is noted by Cutmore, Crowe and Marsden that no quality audio distribution system is known to use this architecture. The carrying of realtime, high bandwidth audio signals is also not suited to the number of other existing computer data distribution systems. Another architecture, Wavelength Division Multiplexing (WDM), is noted by Caine but he deems it unlikely to be used in preference to current and future TDM methods. 2.2 MADI: Employment History The two published works relating to the use and implementation of MADI have both involved national broadcasting companies, namely the Swiss Broadcasting Corporation (Strassman, [1]) and the British Broadcasting Corporation (Cutmore, Crowe and Marsden, [2]). No doubt other cases exist, but for whatever reasons these have not appeared in the mainstream publications. Strassman does not reveal any details regarding the technical issues of the project to digitise the operations of the radiocentre in Zurich, instead focusing on the training requirements to successfully utilise the new technology. His most informative point is that the principle audio source is a stock of CD s in Jukeboxes, which is, in a grander sense, the crux of this thesis project. The level of technical detail is much higher in the BBC article, and provides some insight into the actual implementation of MADI. In this setup, four MADI signals are 5

13 multiplexed and transmitted at 5Mbits/s along a fibre optic distribution network. Although this requirement for a higher bit rate stream results in more complexity than this thesis is interested in, there are some very relevant issues. Again the actual design considerations and technical niceties are not touched upon; instead the authors have presented some block diagrams of the building blocks of their routeing system. Of these building blocks the AES/EBU to MADI coder and the MADI to AES/EBU decoder are of interest, as these functions are essential for this thesis. The main points arising from these building block descriptions are: hardware complexity is reduced by making use of the BBC s AESIC, an Integrated Circuit they developed for use with the AES/EBU interface; the incoming AES/EBU signals are passed through serial to parallel converters to produce parallel bytes; a two page dual-port RAM, addressed by intelligent counters, is used to arrange these bytes in the correct order for transmission as a MADI signal; transmission of data is accomplished by strobing the data one byte at a time into the TAXI transmitter. Figure 2.1: AES/MADI coder (from [2], figure 3) 6

14 At the receiver end, a similar setup is used, in reverse, to obtain AES/EBU output from the MADI signal. A second RAM is used, together with an intelligent counter, to enable output channel selection from the dual-port RAM containing the data from the 56 channels of the received MADI signal. Figure 2.2: MADI/AES decoder (from [2], figure 5) An alternative arrangement is suggested by Zolzer and Kalff [5] in discussing the hardware complexity associated with routeing 56 channels from a TDM parallel bus system. This has the 32-bit data being written to a dual-port RAM whose output is connected to a routing controller. The controller sends the 32 bits of data to a multiplexer, which separates the channel data into four bytes for feeding to the TAXI transmitter input. 7

15 Figure 2.3: Routing MADI with a TDM parallel bus system (from [5], figure 4) 8

16 Chapter 3 Theory The specifications for the MADI standard and its engineering guidelines are fully covered in two AES documents, AES [6] and AES1id-1995 [7]. A less technical, but equally informative overview of MADI can also be found in The Art of Digital Audio (2nd ed), by John Watkinson [3]. The following information is mostly extracted from [6]. 3.1 Overview of MADI The general structure of MADI, as briefly explained in the introduction, can be represented as in Figure 3.1 below (depicting a co-axial cable transmission medium). The data is transmitted serially by non-return-to-zero inverted (NRZI) polarity-free coding, using a 4-bit to 5-bit (4B/5B) encoding format. In NRZI encoding, a high bit of NRZ data is converted to a transition from the last bit, and a low bit results in no transition. Figure 3.1: Overview diagram of MADI (from [6], figure 1) 9

17 Note the separate master synchronisation signal needed to keep the transmitter and receiver in sync. In the case of master-slave operation, it is permissible to derive a separate synchronisation signal from either machine for use as the master clock generator [7]. 3.2 Frame and Channel Data Formats The serial bitstream transmitted is composed of audio and related sample data from each of the 56 channels. One such sequence of consecutive channel data, from channel to channel 55, is known as a frame (Figure 3.2). Figure 3.2: MADI frame format (from [6], figure 2) The 32 data bits of an individual channel within the frame has the following format: Figure 3.3: MADI channel data format (from [6], figure 3) This format preserves the two-channel format of AES [8], whose subframe format is composed of four sync bits, followed by four auxiliary audio or other data bits, 2 bits of digital audio sample data, and a further four bits for the validity (V), user (U), status (C) and parity (P) information. Although 24 bits are assigned to carry audio data, 1

18 the audio sample does not need to be 24 bits wide; the only constraints here are that the MSB (bit 27) is transmitted last and that any unused audio bits be set to zero. A full description of the channel data bits is as follows: Bit : Channel sync/frame synchronisation bit Used to indicate the start of a frame; its value is 1 for channel and for all other channels. The status of this bit is to remain constant over a program duration. Bit 1: Channel active bit Used to indicate an active channel; its value is 1 for active channels and for inactive channels. All inactive channels should have all channel bits set to zero, and should have a channel number that is greater than that of the highest numbered active channel. The status of this bit is to remain constant over a program duration. Bit 2: Channel A/B bit Used for the indication of AES3 A/B subframes ( for A and 1 for B) ie. Left/Right stereo channels. Can also be used to indicate the grouping of a channel with the previous channel. This bit has no meaning in channel since channel A must precede channel B, and channel has no preceding channels with which it may be grouped; it should therefore be ignored in this case. Bit 3: Block sync bit A value of 1 is used to indicate the start of an AES3 block for channel status data or user data to be decoded as appropriate by the receiver. Each block is 192 bits long, therefore the data forming one such block results from the channel status or user bits of 192 successive frames. More details about the specific organisation of the channel status data and the interpretation of bytes within a block are given in the AES [8] document. 11

19 Bits 4-27 Audio data bits Up to 24 bits of an audio signal that has been periodically sampled, digitally quantised and linearly represented in two s complement form. Bit 27 must be the MSB and any unused audio bits should be set to. Bit 28: Validity bit (V) Used to indicate that the previous sample data bits are valid, ie. secure and error free. If unused the default value of should be transmitted to indicate validity. Bit 29: User bit (U) Used to convey user data in a block as per the channel status bit. If unused the default value of should be transmitted. Bit 3: Channel status bit (C) Used in conjunction with the block sync bit to convey a block of data concerning the channel, as per AES3. Its default value is. Bit 31: Parity bit (P) Used to indicate even parity of bits 4-31 of the subframe, however this offers only limited use as an error detection mechanism. Bits -4 are omitted from the parity calculation to maintain compatibility with the AES3 format. If unused, the default value transmitted for the parity bit shall be. 3.3 Maintaining a Constant Data Bit Rate The MADI link runs at a constant transmission rate of 125 megabits per second regardless of the number of active channels or the sampling rate of the audio sources. The actual data transfer rate is 1 megabits per second, with the difference between the transmission and data transfer rates resulting from the use of the 4B/5B encoding scheme. This scheme separates each byte into two four-bit nibbles, and translates each 12

20 nibble into a five-bit word for transmission. The specific rules used for translation provide for error detection, a low DC offset and Sync, a unique synchronisation character (11 11) that cannot be aliased by any combination of legal data [1]. Accommodation of sampling frequencies ranging from khz ±12.5% means the link is supplied with data at rates ranging from megabits per second. Sufficient synchronisation symbols are inserted as necessary to fill the total link capacity of 1 megabits per second [6]. Bound only by that requirement, the synchronisation symbol can appear anywhere for any number of times between channel boundaries within a frame, including after the last channel of a frame. 3.4 The TAXIchips Consisting of two separate ICs, the TAXI chipset forms the foundation of the MADI link. The particular chipset used is the 125 MHz speed option variety, and the specific chips required are the AM7968 TAXI transmitter and the AM7969 TAXI receiver. Their basic operation can be surmised from figure 3.4 below. Figure 3.4: TAXI chipset overview (from [5], figure 2) 13

21 The data to be transmitted is strobed into the AM7968 one byte at a time, where it is latched and encoded according to the 4B/5B encoding scheme. The resulting bits are then shifted to produce a serial bitstream which is output onto the link. At the receiver end, this serial bitstream is converted back into a parallel 1-bit word which is decoded to produce the original byte. This byte is presented at the output and accompanied by the output strobe signal. The transmission of commands to, for example, control receiving hardware, is also supported by the TAXIchips. A byte-rate clock of frequency 12.5MHz needs to be supplied to the TAXIchips in order for them to operate at the 1 megabits per second data rate. It is not necessary, however, for the transmitting process to supply the TAXI transmitter with data at this rate; if a data strobe is not supplied during a byte, the TAXI transmitter will automatically generate and transmit a synchronisation symbol to maintain link synchronisation. Hence all that is required for transmission is for some process to supply the TAXI transmitter with the required MADI bytes in sequence and accompanied by the raising of the data strobe signal, and the TAXI transmitter will take care of the rest. Block diagrams of the transmitter and receiver chips are given below in figures 3.5 and 3.6. Figure 3.5: Block diagram of Am7968 TAXI transmitter (from [12]) 14

22 Figure 3.6: Block diagram of Am7969 TAXI receiver (from [12]) 15

23 Chapter 4 Design As introduced in the previous chapter, the TAXIchips will form the backbone of the MADI transmission link. The TAXI chipset is an essential component of the MADI solution, since MADI was developed at a time when the TAXI chipset, already a basis for FDDI, was the only one capable of meeting the transmission requirements of MADI. It s widespread availability was expected to allow everyone access to MADI technology. (Hopewell-Smith, [9]). The accompanying circuitry is expected to be quite non-trivial, as can be seen from the BBC s efforts [2]. In order to reduce chip count and the overall size of hardware, Altera PLDs will be used to implement most, if not all, of the remaining hardware requirements. The advantage of using PLDs include high density logic cost effective (single chip, multiple functions) ease of developing and changing designs using the MAX+PLUS II software implementing changes requires only a reprogramming of the PLD Thus the combination will be able to meet the hardware requirements of MADI in a small, low-cost package. The transmission link will use coaxial cables in the first instance, as it is more readily available and at a lower cost compared to fibre optic cables. An independent oscillator will provide the master sync signal. 4.1 Functional Overview The functions provided by the hardware will take digital input from multiple CD sources and multiplex them into a MADI bitstream that is transmitted via the link. At the receiver end, the MADI input is demultiplexed into multiple CD bitstreams, of which one will be selected for playback. The transmitter PLD will be responsible for 16

24 obtaining the CD source and converting the serial data to parallel, then processing it to obtain a valid MADI format. The PLD then outputs 8-bit wide data; that is, the 32 bits of data in a MADI channel are strobed a byte at a time into the TAXI transmitter, which then drives the transmission link. On the receiver side, a TAXI receiver takes this MADI bitstream and outputs the 32 bits one byte a time. The receiving PLD takes the 8- bit wide data as input, reconstructs the 4 bytes into a complete MADI channel data sequence, extracts the audio data from the desired channel and converts it back to a serial CD format. This output from the receiving hardware can then be sent to speakers via a DAC (digital to analogue converter), thus delivering the audio from the selected CD source. This system is depicted in Figure 4.1 below. Altera PLD SIPO conversion of input audio data, formatting for MADI channel and multiplexing TAXIchip Transmission Link (Coaxial Cable) Altera PLD Demultiplexing input byte-stream, extraction of audio data from desired MADI channel From CD Player Figure 4.1: Functional block diagram of system To DAC and speakers The functional blocks within the PLD will be designed and implemented in a modular fashion, so that the initial design need only cater for one input source. When the initial design is completed, the modular input block can be reproduced to cater for additional input sources. The processing of this parallel data will be designed to handle 56 channels, as this is the required number of channels to conform to the MADI standard. 17

25 4.2 Data Acquisition The digital output from a CD player is composed of three signals: a word select or left/right channel select line running at the sample frequency; a bit clock and a corresponding data line for the actual bit values. A typical output timing diagram is shown in figure 4.2, where the audio data is transmitted MSB first and right justified. Note that the 44.1 khz sampling frequency used by CD players is the standard sampling frequency for consumer applications. The bit clock runs at between 32 to 64 times the sampling frequency. Figure 4.2: CD output timing diagram (from [11]) This bitstream carries information for two MADI channels, since the left channel is separate to the right channel. Hence it is necessary to first convert the serial data to parallel format and then to separate the data for the two channels. This can be achieved via the circuit shown in figure 4.3. LSB LSB DI BCKI SIPO register 16 Channel 1 Audio MSB MSB LRCI LSB LSB 16 Left channel register Channel Audio 16 MSB MSB Figure 4.3: Extraction of left and right channel data 18

26 BCKI is used to clock data on DI into the Serial-In, Parallel-Out shift register. Since there are only 16 bits of audio data and these bits are right justified in the bitstream, the shift register only need be 16 bits wide. In this manner, the output of the shift register will hold the required 16 bits of the audio data whenever LRCI makes a transition, allowing the parallel output to be loaded into a register. The data is shifted in from the top of the register, so that on an LRCI transition the topmost output line holds the LSB and the bottom-most output line holds the MSB of the audio data. The source signal provides data for two adjacent MADI channels, but they are presented half a sample period apart in time. To rectify this, the left channel data is first stored in a temporary register on the falling edge of the LRCI signal. When the rising edge of LRCI arrives, the data on the output of the shift register, ie. the right channel audio data, is clocked into the channel 1 register, while the left channel audio data is clocked from the temporary register into the channel register. This presents the audio data for the two subframes simultaneously, so that they may appear on adjacent channels within the one MADI frame. 4.3 Formatting the Channel Data The 16 bits of audio data obtained by the data acquisition stage only forms part of the MADI channel data, which was described in section 3.2. Accordingly, the output from the previous stage, representing bits 12 to 27 of the MADI channel, needs to be fed to another set of registers, which will also include the other necessary data bits to make up a valid MADI channel. As previously discussed, the AES bits for validity, user information, channel status and parity will not be used, so these are preset to the default value of. Similarly, the block sync bit and the 8 remaining unused audio data bits are also preset to. With a single CD player supplying the input data, there will only be two active channels, hence channels 2-31 will contain all zeros. The channel data registers are presented in figure 4.4 below. The output of each channel s register will be enabled in turn by the bus loading logic which uses the LRCI signal as a reference clock. Data from all 56 channels are loaded 19

27 once per sample period. When data is loaded onto the bus, the bus loading logic also issues a STROBE signal. Channel Audio 1 1 : : Channel 1 Audio : : : : : : : : : : : : : : : : : To multiplexer 32 STROBE LRCI Bus loading logic Figure 4.4: MADI channel data registers 4.4 Multiplexing Into the TAXI Transmitter With the 32 bits of the channel data made available from the previous section, it is then necessary to multiplex this into 8 bit wide data for feeding into the input of the TAXI transmitter. The adaptation of a single TAXI transmitter for the task of transmitting data wider than eight bits has already been considered in [12], and the solution presented is readily applicable for this thesis requirements. The schematic of the circuitry involved in given in figure 4.5. It involves a group of buffers with tri-state outputs, a D flip-flop register and some NAND gates. Its operation is as follows: The data to be transmitted is assumed to be simultaneously loaded into the buffers when a strobe pulse is input to the system. The controller for the mux is the 74LS174, which is wired as a shift register. As a (which occurs on strobe) is shifted through the register, each buffer is enabled in turn. The NAND gate at 2

28 the input of D1 ensures that only a single is possible while the registers are being selected. The TAXI CLK signal, which is used to clock the 74LS174, is inverted to provide set-up time to ensure that no false strobes reach the TAXI transmitter. The other four-input NAND gate enabled the two-input NAND gate, so that the transmitter will be strobed while there is data available in the buffers. Figure 4.5: 32-bit multiplexed transmitter circuit (from [12]) 21

29 For a sampling frequency of 44.1 khz, data from a new channel appears on the bus about once every 4ns. It takes 32ns for the multiplexing circuitry to load the four data bytes into the TAXI transmitter since the input STRB signal is synchronous to the oscillator frequency. This ensures that the transmitter will be presented with sufficient byte spaces where no STRB is issued and a Sync symbol can be sent. 4.5 Transmission medium The medium used for the TAXI transmission link can be either coaxial cable or fiber optic cable. For the purposes required in this thesis, coaxial cable wins out due to its lower system cost, widespread availability and ease of use, as well as the added benefit of being able to directly connect the coaxial cable to the TAXI SEROUT pins. A fiber optic connection would require the use of additional optical components for the interface. By using a few resistors and capacitors according to figure 4.6, the coaxial cable connection can be ready for use. Figure 4.6: Coaxial cable interface 22

30 Note that the link comprises two cables, one for each of the differential pseudo ECL (emitter-coupled logic) signals. The maximum cable length specified by MADI is 5m, no equalisation is allowed. For longer transmission lengths, fiber optic cables with run lengths of up to 2km would need to be used. Although the MADI standard specifies that 75Ω cables shall be used, the 5Ω variety is more commonly used for data transmission. Either way, resistor values should be chosen according to the characteristic impedance of the cable, as given in the above figure. For 5Ω cable, the following component values have been used [12] to establish a successful TAXI link: R1 = 68Ω; R2 = 2Ω; RE = 3Ω; C =.1µF. 4.6 Demultiplexing the Received Data The reception of data wider than a single byte requires some processing of the data output by the TAXI receiver. This requirement has again been considered in [12] and a solution based on commercially available components is presented. This is shown in figure 4.7. Its functional description is as follows: Controller circuit: The controller consists of a shift register constructed of four D flip-flops and a 3-input NOR gate. The shifter is loaded with a 1 that progresses through the flip-flops sequentially clocking the first column of four registers which capture the incoming data. When the 1 is shifter through the fourth flip-flop, it raises the PCO signal for the CLKOUT D flip-flop. On the following rising edge of the /CLK signal the bytes of cascaded data are simultaneously clocked out through the second column of four registers that buffer the cascaded data to the outside system. Sync commands: When not receiving blocks of data, Sync Commands (bytes) are received which keeps the TAXI receiver locked onto the correct byte rate and byte boundaries. This ensures proper capture of the data at the beginning of the next block. In addition, before a block of data is to be sent, a Sync Command must be received to reset the counter to the proper byte alignment and initialise the system. The CLR_CNTR signal is generated from the CMND and the CSTRB signal which signify a Sync Command has been received. CLR_CNTR clears the controller and then is latched by the rising edge of the receiver CLK to 23

31 form the Sync signal. The Sync signal then generates an active PCO signal. The CLKOUT is then driven high on the following rising edge of /CLK if CLK4 has not already driven the CLKOUT signal high. The sync Command only clocks out the data when it is received before the fourth byte of data has been received, In all other cases, the data is clocked out by the logic involved with the fourth state of the controller. Figure 4.7: Circuit for cascaded data with one TAXI receiver (from [12]) 24

32 4.7 Extracting the Required Channel s Audio After the 32 bits of data from a MADI channel have been obtained, it needs to be processed to extract the relevant audio and other information. Since only one stereo pair will be selected for playback, only two 16-bit buffers are required to hold the audio data from the left and right stereo channels, as shown in figure 4.8. User's choice - 1 of 28 stereo signals Ch. Active A/B 5 Controller Logic BCKI (32 x LCRI) R.enable CLKOUT R 16 LRCI R.Clk L.enable 16 PISO Shift Register DAC To speakers L L.Clk Figure 4.8: Audio signal extraction circuitry The user selects one of the 28 maximum available stereo signals, and this selection information is fed to a controller block. The controller also takes input from the channel, active and A/B channel bits of the incoming MADI channel data, and is clocked using the CLKOUT signal from the previous stage. When the data from the desired MADI channels become available on the bus, the controller clocks the 16 bits of audio data into the left and right buffers. The controller is also responsible for reconstructing the audio data signal lines (figure 4.2) for playback. This is achieved by first multiplying the 44.1 khz LRCI signal by 32 to obtain the required BCKI frequency, which is used to clock the parallel-in, serial-out 25

33 shift register and also fed to the digital to analog converter. Once per LRCI period, the controller enables the buffers outputs to load the PISO with first the left, then the right channel s audio data. With the PISO output forming the DI signal, all three required signal lines are in place for sending to a DAC, whose output is subsequently connected to stereo speakers for audio playback. 26

34 Chapter 5 Implementation The implementation of the designs presented in chapter 4 entered using the graphic editor of Altera s Max+Plus II program. This is a free time-limited version of the full, commercially available package of the same name; it is also referred to as PLSWEB - version 9.1, and is obtainable from Altera s internet homepage. In the course of entering the designs, some minor modifications and corrections to a number of the circuits discussed in the previous chapter were carried out. These are individually explained later in this chapter. Where possible, the design entry has tried to follow the general structure of signal paths of the respective diagram or schematic on which they are based, in order to more easily identify and follow the work done. The current state of progress has the entry of the designs presented in sections 4, 6 and 7 of the previous chapter completed, with section three s associated circuitry yet to be implemented in full. 5.1 Availability of Design Files All the Altera design files created is included in the floppy disk accompanying the hard copy of this thesis. Alternatively, the files can be downloaded via the World Wide Web at the URL for a limited time. In both cases, the files are contained in a zip file named madi.zip (54KB). The graphic editor filenames (.gdf extension) included in the zip archive and their contents are: casc_cntr controller block for the demultiplexer circuit piso16 16-bit parallel-in, serial-out shift register, used in receiver receiver the complete receiver circuitry, taking input signals from the Am7969 TAXI receiver and outputting the three CD output signals to the DAC 27

35 reg16 16-bit register with tri-state outputs rx_demux the demultiplexing circuit of figure 4.7, used in receiver sipo16 16-bit serial-in, parallel-out shift register tx_mux the multiplexing circuit of figure 4.5 zero_pulse a circuit used to produce a zero pulse (one clock period long) when presented with a zero value input of longer than one clock period, used for clocking the registers in receiver 5.2 Multiplexer Modifications With reference to figure 4.5 and Altera design file tx_mux.gdf, The device used for the group of four buffers with tri-state outputs was the octal D-flipflop, as found in the program s included megafunction libraries. The Am29C821 depicted in the schematic was just used as an example of the type of device required. The role of the 74LS was performed with two inverters and a two-input NAND gate. This is essentially a cosmetic change, which allows for easier reading of the signal paths in the graphical design file. If the circuit was implemented using various discrete logic devices rather than a single PLD, the use of the NAND gate would be preferred as this may help reduce total chip count. The two jumper connections were replaced by direct links between logical pins, as the circuit would only be required to run in auto-repeat ACK1 mode, whereby a SYNC signal is automatically inserted between each group of four data bytes. This will help to ensure that the receiver demultiplexing circuitry is given a sync before each group of channel data bytes, thus resetting the controller block outputs and placing the controller in the correct state from which to correctly distribute the data bytes to the output buffers. This requires that the inverted output of the fifth flipflop in the 74LS174 be connected to the STRB input signal. 28

36 5.3 Demultiplexer Modifications With reference to figure 4.7 and Altera design file rx_demux.gdf, The eight data capture registers were implemented using the 74273, as found in the program s included megafunction libraries. Although the design requires 1-bit devices and these are only 8-bit devices, functionality is not compromised. This is because we are only concerned with the 32 bits of channel data, and will not need to propagate the DSTRB or VLTN signals to subsequent circuits. Errors were detected with the CLR_CNTR and SYNC signals as depicted in the schematic, and corrections incorporated in the design entry. The desired action when a sync signal arrives (as indicated by a logic 1 on CSTRB and logic on CO- CO3) is for a high on SYNC to be generated and the controller block s D-flipflops be cleared. However the original schematic would have the lower AND gate used produce a 1 when a sync signal arrives, resulting in a value of for SYNC and the controller not being cleared. The solution is to either replace the AND with a NAND gate, or equivalently invert the output of the AND gate before it arrives at the controller and connect SYNC to the delayed output of the lone D-flipflop rather than to the complemented output. Although the second alternative seems more complicated, it was employed in this instance because the D-flipflops available in the standard libraries do not have complemented outputs. Not all of the 32 bits of MADI channel data were used for outputting, only the 16 bits (bits 12-27) for the audio data and three preamble bits to assist in audio extraction. 5.4 Audio Data Extractor Modifications With reference to figure 4.8 and Altera design file receiver.gdf, Two signal sources, such as adjustable or crystal oscillators will provide the inputs for LRCI and BCKI, running at 44.1 khz and MHz respectively. In the base scenario where only two channels of audio are transmitted, namely channel and channel 1, it is only necessary to distinguish between active and non- 29

37 active channels, and between channel and any other channel, since there will only be one other channel. This greatly simplifies the design for parts of the controller logic responsible for loading the left and right playback channel registers. The left channel data register, being the first channel of a stereo pair, will thus be loaded when the channel preamble bits correspond to channel zero sync and channel active (i.e. Channel ), while the right channel data register gets loaded when the preamble bits correspond to not channel zero sync and channel active (i.e. Channel 1). These left and right channel data registers have their outputs enabled on the rising and falling edges respectively of the LRCI input. Whenever a transition in LRCI enables output of one of the channel registers, a delayed zero pulse of one BCKI period length is triggered and output by the associated zero pulser circuit. The two zero pulse signals are ANDed to form the PISO load input, so that the data output by either channel data register onto the parallel inputs is loaded for serial shifting. It is necessary for this load input signal to be derived from the zero pulsers rather than the output enable signal, as the latter scenario would have the load signal being constantly low, resulting in the PISO constantly loading the data on its inputs and thus not serial shifting the correct data. The serial output of the PISO, combined with the BCKI and LRCI signals, form the required inputs to the DAC, which will output analog audio signals that can be played back through appropriate speakers. 5.5 Validation of Design Entry As the version of the MAX+plus II software available for use was not the full commercial release, there were limitations placed on the operation of various features of the package. One of these limitations associated with the free licence was the nonavailability of the simulator, used for design validation. Thus no in-program testing of the design could be carried out, and hence no conclusive results are available for presentation. However, the receiver circuitry is in a state which is ready to perform the functions for which it was designed. Were the simulator available for use, it can be shown that the receiver circuit, when given the correctly formatted MADI data stream, 3

38 would output the required audio data which can then be processed by a DAC and speakers. To do this, some sampled audio data would be required for two channels the digital outputs of a CD player would be the actual source in a physical implementation. This data then needs to be formatted according to the theory presented in section 3.2. This would then form the data stream that is fed to the multiplexer circuit. Bypassing this and the two TAXI chips, it would also represent the data stream arriving at the input of the demultiplexer circuit, which is the first half of the receiver circuit. Thus it should then be possible to simulate the inputting of this data stream into the receiver circuit and observing the output signals. Knowing in advance what the audio signals at the output should be, it is then a trivial matter to validate the actual output with the theoretical output. 31

39 Chapter 6 Conclusions It had been hoped that work would have progressed sufficiently to allow at least preliminary implementation of the associated hardware using Altera PLDs and to test its interaction with a set of TAXIchips. However this has not been achieved, hence the lack of results to be presented. There were also some difficulties encountered in obtaining a low quantity supply of the TAXIchips, so the actual transmission link component of the design could also not be constructed and tested. Furthermore, limitations imposed by the free lincece version of Altera s design entry program did not allow for software validation of the design. 6.1 Summary and Conclusions The design and partial implementation of a MADI-based CD audio routing system has been presented in the previous chapters. Functional specifications of all the controlling logic have been given, some of which have been translated into actual implementations, albeit for just a two channel scenario. The final implementation is expected to be moderately involved and non-trivial, but feasible. The design presented, although featuring only a single transmitter and single receiver, can be easily extended to cater for multiple receiver nodes by simply tapping into the transmission link at a convenient point and duplicating the receiving circuitry. Applications for this CD audio router could include: piped music to different rooms in modern smart houses and display homes; venues featuring segregated booths where patrons can choose from a selection of music; delivering the audio (fixed repeating source) to the seats of commercial airline passengers; routing music to remote buildings on a property. 32

40 6.2 Possible Future Work Further work needs to be conducted in completing the implementation of the transmitter bus loading logic. Most of the functionality required can be emulated using a PLD rather than discrete logic components and chips, although some elements such as crystal oscillators require the use of separate dedicated ICs. Future work may extend the design to incorporate multiple stereo signals and multiple receiver nodes to fully demonstrate the power and utility of a MADI-based transmission link. Extending the model to cater for professional or para-professional applications may also be conducted. 33

41 Bibliography [1] Strassman, Hans, "Digital radio studios and computer-based transmission: consequences on training," 2nd Radio Montreux International Radio Symposium and Technical Exhibition. Engineering Symposium Record. European Broadcasting Union, Geneva, Switzerland, pp , June [2] Cutmore, N.A.F., Crowe, G.W. and Marsden, R.P., "Experimental digital audio routeing in the BBC's radio operations," IBC 199. International Broadcasting Convention (Conf. Publ. No.327). IEE, London, UK, pp , September 199. [3] Watkinson, John, The Art of Digital Audio, 2nd ed. Oxford: Focal Press, [4] Caine, C.R., "Digital audio routing-a mature technology," IBC 94. International Broadcasting Convention (Conf. Publ. No.397). IEE, London, pp , September [5] Zolzer, U. and Kalff, N., "FDDI-based digital audio interfaces," Network and Operating System Support for Digital Audio and Video. Second International Workshop Proceedings. Springer-Verlag, Berlin. Germany, pp , November [6] Audio Engineering Society, "AES recommended practice for digital audio engineering-serial multichannel audio digital interface (MADI)," Journal of the Audio Engineering Society, vol. 139, num. 5, pp , May [7] Audio Engineering Society, "AES information document for digital audio engineering - Engineering guidelines for the multichannel audio digital interface (MADI) AES1," Journal of the Audio Engineering Society, vol. 43, num. 9, pp. 7-78, September

42 [8] Audio Engineering Society, "AES recommended practice for digital audio engineering - serial transmission format for linearly represented digital audio data," Journal of the Audio Engineering Society, vol. 33, num. 12, pp , December [9] Hopewell-Smith, N., "The MADI interface-an industry milestone?" International Broadcasting, vol. 11, num. 7, pp , September [1] Scott, Paul, TAXIchip TM 4B/5B Codes, AMD Publication #1417, 199. [11] SM5876AM 3 rd -order Σ, 2-channel D/A Converter Datasheet, Nippon Precision Circuits Inc., [12] Am7968/Am7969 TAXIchip TM Handbook, Advanced Micro Devices,