EE5780 Advanced VLSI CAD
|
|
- Rodger Pope
- 5 years ago
- Views:
Transcription
1 EE5780 Advanced VLSI CAD Lecture 11 SRAM and Yield Analysis Zhuo Feng 11.1
2 Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Outline Serial Access Memories 11.2
3 Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM 11.3
4 2 n words of 2 m bits each Array Architecture If n >> m, fold by 2 k into fewer rows of more columns wordlines bitline conditioning bitlines row decoder memory cells: 2 n-k rows x 2 m+k columns Good regularity easy to design Very high density if good cells are used 11.4 n-k n k column decoder 2 m bits column circuitry
5 12T SRAM Cell Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 unit cell write bit write_b read read_b 11.5
6 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: bit Precharge bit, bit_b Raise wordline word Write: Drive data onto bit, bit_b Raise wordline bit_b 11.6
7 SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip bit bit_b word 1.5 A_b bit_b N2 P1 P2 N4 1.0 word bit A N1 N3 A_b A time (ps) 11.7
8 word Precharge both bitlines high Then turn on wordline SRAM Read One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip bit bit_b 1.5 N1 >> N2 N3 >> N4 A_b bit_b N2 P1 P2 N4 1.0 word bit A N1 N3 A_b A time (ps) 11.8
9 SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter A_b word bit N2 P1 P2 bit_b N bit_b A A N1 N3 A_b 0.5 word time (ps) 11.9
10 SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter A_b N2 >> P1 N4 >> P2 word bit N2 P1 P2 bit_b N bit_b A A N1 N3 A_b 0.5 word time (ps) 11.10
11 SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell bit bit_b word med weak med A A_b strong 11.11
12 SRAM Column Example Bitline Conditioning 2 More Cells Read bit_v1f bit_b_v1f Write word_q1 bit_v1f SRAM Cell bit_b_v1f write_q1 data_s
13 SRAM Layout Cell size is critical: 26 x 45 (even smaller in industry) Tile cells sharing V DD, GND, bitline contacts GND BIT BIT_B GND VDD WORD Cell boundary 11.13
14 In nanometer CMOS Thin Cell Avoid bends in polysilicon and diffusion Orient all transistors in one direction Lithographically friendly or thin cel layout fixes this Also reduces length and capacitance of bitlines 11.14
15 Commercial SRAMs Five generations of Intel SRAM cell micrographs Transition to thin cell at 65 nm Steady scaling of cell area 11.15
16 Decoders n:2 n decoder consists of 2 n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS Pseudo-nMOS A1 A0 A word A1 A0 1/2 A0 A word A0 1 word0 word1 word2 word3 word0 word1 word2 word
17 Decoder Layout Decoders must be pitch-matched to SRAM cell Requires very skinny gates A3 A3 A2 A2 A1 A1 A0 A0 VDD word GND NAND gate buffer inverter 11.17
18 Large Decoders For n > 4, NAND gates become slow Break large gates into multiple smaller gates A3 A2 A1 A0 word0 word1 word2 word3 word
19 Column Circuitry Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing 11.19
20 Bitline Conditioning Precharge bitlines high before reads bit bit_b Equalize bitlines to minimize voltage difference when using sense amplifiers bit bit_b 11.20
21 Sense Amplifiers Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 128 cells on each bitline t pd (C/I) V Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce V) 11.21
22 Differential Pair Amp Differential pair requires no clock But always dissipates static power sense_b bit P1 N1 N2 P2 sense bit_b N
23 Clocked Sense Amp Clocked sense amp saves power Requires sense_clk after enough bitline swing Isolation transistors cut off large bitline capacitance bit bit_b sense_clk isolation transistors regenerative feedback sense sense_b 11.23
24 Twisted Bitlines Sense amplifiers also amplify noise Coupling noise is severe in modern processes Try to couple equally onto bit and bit_b Done by twisting bitlines b0 b0_b b1 b1_b b2 b2_b b3 b3_b 11.24
25 Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2k word x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers 11.25
26 Tree Decoder Mux Column mux can use pass transistors Use nmos only, precharge outputs One design is to use k series transistors for 2 k :1 mux No external decoder logic needed A0 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A1 A2 A2 Y to sense amps and write circuits Y 11.26
27 Single Pass-Gate Mux Or eliminate series transistors with separate decoder A1 A0 B0 B1 B2 B3 Y 11.27
28 Dual-Ported SRAM Simple dual-ported SRAM Two independent single-ended reads Or one differential write bit bit_b worda wordb Do two reads and one write by time multiplexing Read during ph1, write during ph
29 Large SRAMs Large SRAMs are split into subarrays for speed Ex: UltraSparc 512KB cache KB subarrays Each have 16 8KB banks 256 rows x 256 cols / bank 60% subarray area efficiency Also space for tags & control [Shin05] 11.29
30 Yield analysis of embedded memory modules Play a critical role in nanoscale and emerging nonvolatile memory designs for future microprocessor, 3D-IC, and mixed-signal system designs Challenged by a huge number (many millions) of Monte Carlo ICE simulations for relatively small circuit blocks considering parametric (process, voltage, and temperature) variations 3 rd Generation Intel Core Processor: 22nm Process Source:
31 l1 TinyICE Simulator TinyICE: ICE-accurate, fast, massively parallel small nonlinear circuits simulator Accelerates entire ICE simulator on GPU Run independent ICE simulations concurrently Designs GPU-friendly data structures Develops efficient algorithm flow Optimizes GPU memory accesses Newton Raphson Iterations Shared Memory Shared Memory Shared Memory Shared Memory Shared Memory Shared Memory Shared Memory Shared Memory bit bit_b word bit bit_b word bit P1 P2 bit_b N2 N4 word bit P1 P2 bit_b N2 A A_b N4 word P1 P2 N1 N2 A N3 A_b N4 P1 P2 N1 N2 A N3 A_b N4 N1 A N3 A_b N1 N3 1v 1i i 2 i 3 v 2 k i ds gm v gs k k ids Gds v ds k a a a a a a a 1,1 1,4 1,5 a2,2 a2,3 a2,6 a3,2 a3,3 a3,8 4,1 a4,4 5,1 5,5 5,7 a6,2 a6,6 a6,8 a7,5 a7,7 a8,3 a8,6 a8,8 CKT Schematic Model Evaluation Matrix Stamping/Solve Converged? Return GPU Streaming Multiprocessors Massively Parallel ICE Simulations in GPU Shared Memory 11.31
32 Slide 31 l1 lengfei, 5/13/2013
33 TinyICE Flow Chart TinyICE algorithm flow have three key steps CPU-setup phase, GPU-setup phase and GPU-analysis phase CPU Setup TinyICE GPU Analysis Reset G Matrix & Update RHS Setup 3D LUTs Nonlinear Device Parse Netlist Excitation & MOS Terminal Map Index Setup Matrix for Linear Circuit Get Latest Solution Transistor Evaluation Nonlinear Stamp GPU Setup GPU Mem. Map Mem. Map Mem. G Matrix & Mem. G Matrix & Mem. LU Solve Conv. Chec k Return 11.32
34 MNA Matrix Construction Linear element evaluation on CPU due to Corresponding entries are constant value throughout whole ICE simulation Nonlinear element evaluation on GPU due to Need to be re-evaluated in every NR step Nonlinear element evaluation by parametric 3D look-up tables (LUTs) BSIM4 too complicated for GPU Simplify control flow Can capture impact of process variations by introduce parametric LUTs 11.33
35 Parametric 3D LUTs 2 nd order Parametric 3D LUTs evaluation function LUT base LUT LUTV th and LUT Leff LUT LUT VthLeff and Vth LUT L 2 eff 2 LUT V base LUT th Vth 2 L LUT V eff V th 2 th LUT V th LUT VthLeff Leff LUT 2 L eff L 2 eff L : Base LUT based on transistor nominal parameters : First order coefficient LUT for transistor threshold voltage and effective channel length : Second order coefficient LUT for transistor threshold voltage and effective channel length : coefficient LUT derived from the partial derivatives of Vth and Leff eff V th : Variation of transistor threshold voltage L eff : Variation of transistor effective channel length More input parameters and more accurate requirement More costly higher order LUTs
36 LUTs Trilinear Interpolation(1 st Order Demonstration) Parametric 3D LUTs extraction High resolution means high memory and runtime cost One time cost, multiple usage 0.6% of whole simulation time Trilinear interpolation p 0 Base LUT p x, y, z c c c c c c c c (1 x)(1 y)(1 z) x(1 y)(1 z) (1 x) y(1 z) (1 x)(1 y) z x(1 y) z (1 x) yz xy(1 z) x y z LUT LUT P 0 p 1 Threshold Voltage LUT base LUT P V 1 th V th V th P L 2 eff p 2 Effective Channel Length LUT LUT L eff L eff 11.35
37 GPU Friendly Data Structure Design System Matrix Adopt dense structure due to Complicated memory access required by sparse matrix Affordable memory consumption (limited problem size) Store in GPU register due to Frequent read/write memory access Parametric 3D LUTs Store in texture memory due to Read only memory access Gmat Gmat vth Gmat Leff MOSFET 1 n MOSFET 1 n MOSFET 1 n 3D LUTs Texture Memory 11.36
38 GPU Friendly Data Structure Design (cont.) Index-mapping vectors & voltage sources vector Record stamping locations of nonlinear device and sources Record voltage sources value in all time points Store in Share memory due to All threads share this information Data size is affordable Idx Type d g s b Mos_map MOSFET 1 MOSFET n Pseudo PWL Node a Node b VS_map Node P Shared Memory Voltage Source 1 Voltage Source n V_t1 V_t2... V_tn VS_step Voltage Source 1 Voltage Source n 11.37
39 GPU Friendly Data Structure Design (cont.) Solution vector Record solution of each time point Need send back to CPU Store in Global memory due to Low access frequency Satisfy coalesced memory accesses X[0] X1.0 X2.0 Xn.0 X1.n X2.n Xn.n T1 T2 Tn X[n] Solution Global Memory 11.38
40 Newton-Raphson Algorithm on GPU Check convergence after several NR iterations Reduces the GPU thread divergence Leads some overhead Reset G Matrix & Update RHS Reset G Matrix & Update RHS Transistor Evaluation Transistor Evaluation Get Latest Solution Nonlinear Stamp Get Latest Solution Nonlinear Stamp LU Solve LU Solve Time to Check Conv. Check Return Conv. Check Return
41 Linux computing system: C++ & CUDA CPU: Core 2 Quad 2.66GHz + 6GB DRAM GPU: GPU: NVIDIA GTX G Device memory Tested cases Experimental Setups Circuit NL_Num Node_Num Vs_Num Unk_Num 6T-SRAM D-Latch D-Flip-Flop Invertor Chain 4:1 Mux NL_Num : Number of nonlinear devices Node_Num : Number of nodes in the circuit Vs_Num : Number of independent voltage sources Unk_Num : number of unknowns of the nonlinear system 11.40
42 Run 1,536,000 simulations with different excitation and circuit design parameters Speedup LUTs GPU vs. LUTs CPU is up to 138X Speedup LUTs GPU vs. BSIM4 CPU is up to 264X 264 X 138 X DC Simulation Result 211 X 92X 189 X 92X 104 X 45 X 47 X 22 X Runtime (log) 11.41
43 Transient Simulation Result Speedup LUTs GPU vs. LUTs CPU is up to 57X Speedup LUTs GPU vs. BSIM4 CPU is up to 222X Runtime (log) 187 X 46X 222 X 57X 202X 53X 160 X 96 X 54 X 12 X 11.42
44 Memory Consumption vs. Speedup Runtime efficiency decrease with the increase of circuit size Memory usage increase dramatically due to dense MNA structure 11.43
Sequencing. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,
Sequencing ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2013 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Introduction Sequencing
More informationHardware Design I Chap. 5 Memory elements
Hardware Design I Chap. 5 Memory elements E-mail: shimada@is.naist.jp Why memory is required? To hold data which will be processed with designed hardware (for storage) Main memory, cache, register, and
More informationIntroduction to CMOS VLSI Design (E158) Lecture 11: Decoders and Delay Estimation
Harris Introduction to CMOS VLSI Design (E158) Lecture 11: Decoders and Delay Estimation David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University
More informationVLSI Design: 3) Explain the various MOSFET Capacitances & their significance. 4) Draw a CMOS Inverter. Explain its transfer characteristics
1) Explain why & how a MOSFET works VLSI Design: 2) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel
More informationROM MEMORY AND DECODERS
ROM MEMORY AND DECODERS INEL427 - Spring 22 RANDOM ACCESS MEMORY Random Access Memory (RAM) read and write memory volatile Static RAM (SRAM) store information as long as power is applied will not lose
More informationSequential Logic. References:
Sequential Logic Reerences: Adapted rom: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles o CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationCombinational vs Sequential
Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs
More information11. Sequential Elements
11. Sequential Elements Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 11, 2017 ECE Department, University of Texas at Austin
More informationModifying the Scan Chains in Sequential Circuit to Reduce Leakage Current
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 3, Issue 1 (Sep. Oct. 2013), PP 01-09 e-issn: 2319 4200, p-issn No. : 2319 4197 Modifying the Scan Chains in Sequential Circuit to Reduce Leakage
More informationLeakage Current Reduction in Sequential Circuits by Modifying the Scan Chains
eakage Current Reduction in Sequential s by Modifying the Scan Chains Afshin Abdollahi University of Southern California (3) 592-3886 afshin@usc.edu Farzan Fallah Fujitsu aboratories of America (48) 53-4544
More informationDIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITL TECHNICS Dr. álint Pődör Óbuda University, Microelectronics and Technology Institute 10. LECTURE (LOGIC CIRCUITS, PRT 2): MOS DIGITL CIRCUITS II 2016/2017 10. LECTURE: MOS DIGITL CIRCUITS II 1.
More informationEEC 118 Lecture #9: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #9: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Review: Static CMOS Logic Finish Static CMOS transient analysis Sequential
More informationL11/12: Reconfigurable Logic Architectures
L11/12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of California, Berkeley,
More informationDigital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
More informationA NOVEL DESIGN OF COUNTER USING TSPC D FLIP-FLOP FOR HIGH PERFORMANCE AND LOW POWER VLSI DESIGN APPLICATIONS USING 45NM CMOS TECHNOLOGY
A NOVEL DESIGN OF COUNTER USING TSPC D FLIP-FLOP FOR HIGH PERFORMANCE AND LOW POWER VLSI DESIGN APPLICATIONS USING 45NM CMOS TECHNOLOGY Ms. Chaitali V. Matey 1, Ms. Shraddha K. Mendhe 2, Mr. Sandip A.
More informationL12: Reconfigurable Logic Architectures
L12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Frank Honore Prof. Randy Katz (Unified Microelectronics
More informationDesign and Analysis of Custom Clock Buffers and a D Flip-Flop for Low Swing Clock Distribution Networks. A Thesis presented.
Design and Analysis of Custom Clock Buffers and a D Flip-Flop for Low Swing Clock Distribution Networks A Thesis presented by Mallika Rathore to The Graduate School in Partial Fulfillment of the Requirements
More informationEL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP. Due İLKER KALYONCU, 10043
EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP Due 16.05. İLKER KALYONCU, 10043 1. INTRODUCTION: In this project we are going to design a CMOS positive edge triggered master-slave
More informationUse of Low Power DET Address Pointer Circuit for FIFO Memory Design
International Journal of Education and Science Research Review Use of Low Power DET Address Pointer Circuit for FIFO Memory Design Harpreet M.Tech Scholar PPIMT Hisar Supriya Bhutani Assistant Professor
More informationWhy FPGAs? FPGA Overview. Why FPGAs?
Transistor-level Logic Circuits Positive Level-sensitive EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) January 28, 2003 John Wawrzynek Transistor Level clk clk clk Positive
More informationTutorial Outline. Typical Memory Hierarchy
Tutorial Outline 8:30-8:45 8:45-9:05 9:05-9:30 9:30-10:30 10:30-10:50 10:50-12:15 12:15-1:30 1:30-2:30 2:30-3:30 3:30-3:50 3:50-4:30 4:30-4:45 Introduction and motivation Sources of power in CMOS designs
More informationUNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN
UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN Part A (2 Marks) 1. What is a BiCMOS? BiCMOS is a type of integrated circuit that uses both bipolar and CMOS technologies. 2. What are the problems
More informationHigh Performance Microprocessor Design and Automation: Overview, Challenges and Opportunities IBM Corporation
High Performance Microprocessor Design and Automation: Overview, Challenges and Opportunities Introduction About Myself What to expect out of this lecture Understand the current trend in the IC Design
More informationFuture of Analog Design and Upcoming Challenges in Nanometer CMOS
Future of Analog Design and Upcoming Challenges in Nanometer CMOS Greg Taylor VLSI Design 2010 Outline Introduction Logic processing trends Analog design trends Analog design challenge Approaches Conclusion
More informationChapter 7 Memory and Programmable Logic
EEA091 - Digital Logic 數位邏輯 Chapter 7 Memory and Programmable Logic 吳俊興國立高雄大學資訊工程學系 2006 Chapter 7 Memory and Programmable Logic 7-1 Introduction 7-2 Random-Access Memory 7-3 Memory Decoding 7-4 Error
More informationWINTER 14 EXAMINATION
Subject Code: 17320 WINTER 14 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2)
More informationMOS Logic Families. Somayyeh Koohi. Department of Computer Engineering Sharif University of Technology
MOS Logic Families Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Topics Pseudo-nMOS gates DCVS logic Domino gates Modern VLSI Design:
More informationDIFFERENTIAL CONDITIONAL CAPTURING FLIP-FLOP TECHNIQUE USED FOR LOW POWER CONSUMPTION IN CLOCKING SCHEME
DIFFERENTIAL CONDITIONAL CAPTURING FLIP-FLOP TECHNIQUE USED FOR LOW POWER CONSUMPTION IN CLOCKING SCHEME Mr.N.Vetriselvan, Assistant Professor, Dhirajlal Gandhi College of Technology Mr.P.N.Palanisamy,
More informationLFSR Counter Implementation in CMOS VLSI
LFSR Counter Implementation in CMOS VLSI Doshi N. A., Dhobale S. B., and Kakade S. R. Abstract As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size
More informationDESIGN OF NOVEL ADDRESS DECODERS AND SENSE AMPLIFIER FOR SRAM BASED memory
DESIGN OF NOVEL ADDRESS DECODERS AND SENSE AMPLIFIER FOR SRAM BASED memory A Thesis submitted in partial fulfillment of the Requirements for the degree of Master of Technology In Electronics and Communication
More informationSelf-Test and Adaptation for Random Variations in Reliability
Self-Test and Adaptation for Random Variations in Reliability Kenneth M. Zick and John P. Hayes University of Michigan, Ann Arbor, MI USA August 31, 2010 Motivation Physical variation is increasing dramatically
More informationFinFETs & SRAM Design
FinFETs & SRAM Design Raymond Leung VP Engineering, Embedded Memories April 19, 2013 Synopsys 2013 1 Agenda FinFET the Device SRAM Design with FinFETs Reliability in FinFETs Summary Synopsys 2013 2 How
More informationCS 152 Computer Architecture and Engineering
CS 152 Computer Architecture and Engineering Lecture 12 Memory and Interfaces 2006-10-10 John Lazzaro (www.cs.berkeley.edu/~lazzaro) TAs: Udam Saini and Jue Sun www-inst.eecs.berkeley.edu/~cs152/ Last
More informationCS/EE 6710 Digital VLSI Design CAD Assignment #3 Due Thursday September 21 st, 5:00pm
CS/EE 6710 Digital VLSI Design CAD Assignment #3 Due Thursday September 21 st, 5:00pm Overview: In this assignment you will design a register cell. This cell should be a single-bit edge-triggered D-type
More informationnmos transistor Basics of VLSI Design and Test Solution: CMOS pmos transistor CMOS Inverter First-Order DC Analysis CMOS Inverter: Transient Response
nmos transistor asics of VLSI Design and Test If the gate is high, the switch is on If the gate is low, the switch is off Mohammad Tehranipoor Drain ECE495/695: Introduction to Hardware Security & Trust
More informationLecture 10: Sequential Circuits
Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 1 Outline Floorplanning Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time
More informationChapter. Sequential Circuits
Chapter Sequential Circuits Circuits Combinational circuit The output depends only on the input Sequential circuit Has a state The output depends not only on the input but also on the state the circuit
More informationEE 447/547 VLSI Design. Lecture 9: Sequential Circuits. VLSI Design EE 447/547 Sequential circuits 1
EE 447/547 VLSI esign Lecture 9: Sequential Circuits Sequential circuits 1 Outline Floorplanning Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking Sequential
More informationINTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) Proceedings of the 2 nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 ISSN
More informationDigital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
More informationDesign of Fault Coverage Test Pattern Generator Using LFSR
Design of Fault Coverage Test Pattern Generator Using LFSR B.Saritha M.Tech Student, Department of ECE, Dhruva Institue of Engineering & Technology. Abstract: A new fault coverage test pattern generator
More informationLecture 1: Circuits & Layout
Lecture 1: Circuits & Layout Outline A Brief History CMOS Gate esign Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick iagrams 2 A Brief History 1958: First integrated circuit Flip-flop
More informationEECS150 - Digital Design Lecture 2 - CMOS
EECS150 - Digital Design Lecture 2 - CMOS January 23, 2003 John Wawrzynek Spring 2003 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor
More informationEECS150 - Digital Design Lecture 18 - Circuit Timing (2) In General...
EECS150 - Digital Design Lecture 18 - Circuit Timing (2) March 17, 2010 John Wawrzynek Spring 2010 EECS150 - Lec18-timing(2) Page 1 In General... For correct operation: T τ clk Q + τ CL + τ setup for all
More informationDual Slope ADC Design from Power, Speed and Area Perspectives
Dual Slope ADC Design from Power, Speed and Area Perspectives Isaac Macwan, Xingguo Xiong, Lawrence Hmurcik Department of Electrical & Computer Engineering, University of Bridgeport, Bridgeport, CT 06604
More informationVU Mobile Powered by S NO Group
Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register.
More informationA FOUR GAIN READOUT INTEGRATED CIRCUIT : FRIC 96_1
A FOUR GAIN READOUT INTEGRATED CIRCUIT : FRIC 96_1 J. M. Bussat 1, G. Bohner 1, O. Rossetto 2, D. Dzahini 2, J. Lecoq 1, J. Pouxe 2, J. Colas 1, (1) L. A. P. P. Annecy-le-vieux, France (2) I. S. N. Grenoble,
More informationLecture 1: Intro to CMOS Circuits
Introduction to CMOS VLSI esign Lecture : Intro to CMOS Circuits avid Harris Steven Levitan Fall 28 Harvey Mudd College Spring 24 Outline A Brief History CMOS Gate esign Pass Transistors CMOS Latches &
More informationWINTER 15 EXAMINATION Model Answer
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
More informationDigital Integrated Circuits EECS 312. Review. Remember the ENIAC? IC ENIAC. Trend for one company. First microprocessor
14 12 10 8 6 IBM ES9000 Bipolar Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP)
More informationIC TECHNOLOGY Lecture 2.
IC TECHNOLOGY Lecture 2. IC Integrated Circuit Technology Integrated Circuit: An integrated circuit (IC, a chip, or a microchip) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor
More informationPICOSECOND TIMING USING FAST ANALOG SAMPLING
PICOSECOND TIMING USING FAST ANALOG SAMPLING H. Frisch, J-F Genat, F. Tang, EFI Chicago, Tuesday 6 th Nov 2007 INTRODUCTION In the context of picosecond timing, analog detector pulse sampling in the 10
More informationEECS 270 Final Exam Spring 2012
EECS 270 Final Exam Spring 2012 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points 2 /20 3 /12 4 /10 5 /15
More informationFully Static and Compressed Topology Using Power Saving in Digital circuits for Reduced Transistor Flip flop
Fully Static and Compressed Topology Using Power Saving in Digital circuits for Reduced Transistor Flip flop 1 S.Mounika & 2 P.Dhaneef Kumar 1 M.Tech, VLSIES, GVIC college, Madanapalli, mounikarani3333@gmail.com
More informationCOMP2611: Computer Organization. Introduction to Digital Logic
1 COMP2611: Computer Organization Sequential Logic Time 2 Till now, we have essentially ignored the issue of time. We assume digital circuits: Perform their computations instantaneously Stateless: once
More informationTEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC)
1 TEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC) Q.1 The flip-flip circuit is. a) Unstable b) multistable c) Monostable d) bitable Q.2 A digital counter consists of a group of a) Flip-flop b) half adders c)
More informationLow-Power and Area-Efficient Shift Register Using Pulsed Latches
Low-Power and Area-Efficient Shift Register Using Pulsed Latches G.Sunitha M.Tech, TKR CET. P.Venkatlavanya, M.Tech Associate Professor, TKR CET. Abstract: This paper proposes a low-power and area-efficient
More informationSequential Circuit Design: Part 1
Sequential Circuit esign: Part 1 esign of memory elements Static latches Pseudo-static latches ynamic latches Timing parameters Two-phase clocking Clocked inverters James Morizio 1 Sequential Logic FFs
More informationObjectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
More informationIntroduction Actel Logic Modules Xilinx LCA Altera FLEX, Altera MAX Power Dissipation
Outline CPE 528: Session #12 Department of Electrical and Computer Engineering University of Alabama in Huntsville Introduction Actel Logic Modules Xilinx LCA Altera FLEX, Altera MAX Power Dissipation
More informationHigh Performance Dynamic Hybrid Flip-Flop For Pipeline Stages with Methodical Implanted Logic
High Performance Dynamic Hybrid Flip-Flop For Pipeline Stages with Methodical Implanted Logic K.Vajida Tabasum, K.Chandra Shekhar Abstract-In this paper we introduce a new high performance dynamic hybrid
More informationDesign of a Low Power and Area Efficient Flip Flop With Embedded Logic Module
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 10, Issue 6, Ver. II (Nov - Dec.2015), PP 40-50 www.iosrjournals.org Design of a Low Power
More informationAn Introduction to VLSI (Very Large Scale Integrated) Circuit Design
An Introduction to VLSI (Very Large Scale Integrated) Circuit Design Presented at EE1001 Oct. 16th, 2018 By Hua Tang The first electronic computer (1946) 2 First Transistor (Bipolar) First transistor Bell
More informationChapter 3 Evaluated Results of Conventional Pixel Circuit, Other Compensation Circuits and Proposed Pixel Circuits for Active Matrix Organic Light Emitting Diodes (AMOLEDs) -------------------------------------------------------------------------------------------------------
More informationComputer Architecture and Organization
A-1 Appendix A - Digital Logic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Appendix A Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
More informationSequential Circuit Design: Part 1
Sequential ircuit esign: Part 1 esign of memory elements Static latches Pseudo-static latches ynamic latches Timing parameters Two-phase clocking locked inverters Krish hakrabarty 1 Sequential Logic FFs
More informationCombining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Reduction Stephanie Augsburger 1, Borivoje Nikolić 2 1 Intel Corporation, Enterprise Processors Division, Santa Clara, CA, USA. 2 Department
More informationMarch Test Compression Technique on Low Power Programmable Pseudo Random Test Pattern Generator
International Journal of Computational Intelligence Research ISSN 0973-1873 Volume 13, Number 6 (2017), pp. 1493-1498 Research India Publications http://www.ripublication.com March Test Compression Technique
More informationP.Akila 1. P a g e 60
Designing Clock System Using Power Optimization Techniques in Flipflop P.Akila 1 Assistant Professor-I 2 Department of Electronics and Communication Engineering PSR Rengasamy college of engineering for
More informationVLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET476) Lecture 9 (2) Built-In-Self Test (Chapter 5) Said Hamdioui Computer Engineering Lab Delft University of Technology 29-2 Learning aims Describe the concept and
More informationTestability: Lecture 23 Design for Testability (DFT) Slide 1 of 43
Testability: Lecture 23 Design for Testability (DFT) Shaahin hi Hessabi Department of Computer Engineering Sharif University of Technology Adapted, with modifications, from lecture notes prepared p by
More informationLOW POWER LEVEL CONVERTING FLIP-FLOP DESIGN BY USING CONDITIONAL DISCHARGE TECHNIQUE
LOW POWER LEVEL CONVERTING FLIP-FLOP DESIGN BY USING CONDITIONAL DISCHARGE TECHNIQUE Keerthana S Assistant Professor, Department of Electronics and Telecommunication Engineering Karpagam College of Engineering
More informationECE 263 Digital Systems, Fall 2015
ECE 263 Digital Systems, Fall 2015 REVIEW: FINALS MEMORY ROM, PROM, EPROM, EEPROM, FLASH RAM, DRAM, SRAM Design of a memory cell 1. Draw circuits and write 2 differences and 2 similarities between DRAM
More informationHIGH PERFORMANCE AND LOW POWER ASYNCHRONOUS DATA SAMPLING WITH POWER GATED DOUBLE EDGE TRIGGERED FLIP-FLOP
HIGH PERFORMANCE AND LOW POWER ASYNCHRONOUS DATA SAMPLING WITH POWER GATED DOUBLE EDGE TRIGGERED FLIP-FLOP 1 R.Ramya, 2 C.Hamsaveni 1,2 PG Scholar, Department of ECE, Hindusthan Institute Of Technology,
More information12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009
12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009 Project Overview This project was originally titled Fast Fourier Transform Unit, but due to space and time constraints, the
More informationLow Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 29 Minimizing Switched Capacitance-III. (Refer
More informationTopic 8. Sequential Circuits 1
Topic 8 Sequential Circuits 1 Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Rabaey Chapter 7 URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk 1 Based on
More informationEECS150 - Digital Design Lecture 17 - Circuit Timing. Performance, Cost, Power
EECS150 - Digital Design Lecture 17 - Circuit Timing March 10, 2011 John Wawrzynek Spring 2011 EECS150 - Lec16-timing Page 1 Performance, Cost, Power How do we measure performance? operations/sec? cycles/sec?
More informationEFFICIENT POWER REDUCTION OF TOPOLOGICALLY COMPRESSED FLIP-FLOP AND GDI BASED FLIP FLOP
EFFICIENT POWER REDUCTION OF TOPOLOGICALLY COMPRESSED FLIP-FLOP AND GDI BASED FLIP FLOP S.BANUPRIYA 1, R.GOWSALYA 2, M.KALEESWARI 3, B.DHANAM 4 1, 2, 3 UG Scholar, 4 Asst.Professor/ECE 1, 2, 3, 4 P.S.R.RENGASAMY
More informationOptimized Magnetic Flip-Flop Combined With Flash Architecture for Memory Unit Based On Sleep Transistor
International Journal of Electrical Engineering. ISSN 0974-2158 Volume 8, Number 1 (2015), pp. 73-79 International Research Publication House http://www.irphouse.com Optimized Magnetic Flip-Flop Combined
More informationTYPICAL QUESTIONS & ANSWERS
DIGITALS ELECTRONICS TYPICAL QUESTIONS & ANSWERS OBJECTIVE TYPE QUESTIONS Each Question carries 2 marks. Choose correct or the best alternative in the following: Q.1 The NAND gate output will be low if
More informationEFFICIENT DESIGN OF SHIFT REGISTER FOR AREA AND POWER REDUCTION USING PULSED LATCH
EFFICIENT DESIGN OF SHIFT REGISTER FOR AREA AND POWER REDUCTION USING PULSED LATCH 1 Kalaivani.S, 2 Sathyabama.R 1 PG Scholar, 2 Professor/HOD Department of ECE, Government College of Technology Coimbatore,
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 9: TX Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda Next
More informationA Symmetric Differential Clock Generator for Bit-Serial Hardware
A Symmetric Differential Clock Generator for Bit-Serial Hardware Mitchell J. Myjak and José G. Delgado-Frias School of Electrical Engineering and Computer Science Washington State University Pullman, WA,
More informationBased on slides/material by. Topic 14. Testing. Testing. Logic Verification. Recommended Reading:
Based on slides/material by Topic 4 Testing Peter Y. K. Cheung Department of Electrical & Electronic Engineering Imperial College London!! K. Masselos http://cas.ee.ic.ac.uk/~kostas!! J. Rabaey http://bwrc.eecs.berkeley.edu/classes/icbook/instructors.html
More informationA video signal processor for motioncompensated field-rate upconversion in consumer television
A video signal processor for motioncompensated field-rate upconversion in consumer television B. De Loore, P. Lippens, P. Eeckhout, H. Huijgen, A. Löning, B. McSweeney, M. Verstraelen, B. Pham, G. de Haan,
More informationNoise Margin in Low Power SRAM Cells
Noise Margin in Low Power SRAM Cells S. Cserveny, J. -M. Masgonty, C. Piguet CSEM SA, Neuchâtel, CH stefan.cserveny@csem.ch Abstract. Noise margin at read, at write and in stand-by is analyzed for the
More informationDIGITAL ELECTRONICS MCQs
DIGITAL ELECTRONICS MCQs 1. A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8
More informationEE-382M VLSI II FLIP-FLOPS
EE-382M VLSI II FLIP-FLOPS Gian Gerosa, Intel Fall 2008 EE 382M Class Notes Page # 1 / 31 OUTLINE Trends LATCH Operation FLOP Timing Diagrams & Characterization Transfer-Gate Master-Slave FLIP-FLOP Merged
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous)
Subject Code: 17320 Model Answer Page 1 of 32 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the Model answer scheme. 2) The model
More informationdata and is used in digital networks and storage devices. CRC s are easy to implement in binary
Introduction Cyclic redundancy check (CRC) is an error detecting code designed to detect changes in transmitted data and is used in digital networks and storage devices. CRC s are easy to implement in
More informationImprove Performance of Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop
Sumant Kumar et al. 2016, Volume 4 Issue 1 ISSN (Online): 2348-4098 ISSN (Print): 2395-4752 International Journal of Science, Engineering and Technology An Open Access Journal Improve Performance of Low-Power
More informationVLSI System Testing. BIST Motivation
ECE 538 VLSI System Testing Krish Chakrabarty Built-In Self-Test (BIST): ECE 538 Krish Chakrabarty BIST Motivation Useful for field test and diagnosis (less expensive than a local automatic test equipment)
More informationOverview of All Pixel Circuits for Active Matrix Organic Light Emitting Diode (AMOLED)
Chapter 2 Overview of All Pixel Circuits for Active Matrix Organic Light Emitting Diode (AMOLED) ---------------------------------------------------------------------------------------------------------------
More informationReduction of Area and Power of Shift Register Using Pulsed Latches
I J C T A, 9(13) 2016, pp. 6229-6238 International Science Press Reduction of Area and Power of Shift Register Using Pulsed Latches Md Asad Eqbal * & S. Yuvaraj ** ABSTRACT The timing element and clock
More informationFPGA Design. Part I - Hardware Components. Thomas Lenzi
FPGA Design Part I - Hardware Components Thomas Lenzi Approach We believe that having knowledge of the hardware components that compose an FPGA allow for better firmware design. Being able to visualise
More informationLow Power Approach of Clock Gating in Synchronous System like FIFO: A Novel Clock Gating Approach and Comparative Analysis
Low Power Approach of Clock Gating in Synchronous System like FIFO: A Novel Clock Gating Approach and Comparative Analysis Abstract- A new technique of clock is presented to reduce dynamic power consumption.
More informationMemory elements. Topics. Memory element terminology. Variations in memory elements. Clock terminology. Memory element parameters. clock.
Topics! Memory elements.! Basics of sequential machines. Memory elements! Stores a value as controlled by clock.! May have load signal, etc.! In CMOS, memory is created by:! capacitance (dynamic);! feedback
More informationDesign of Low Power D-Flip Flop Using True Single Phase Clock (TSPC)
Design of Low Power D-Flip Flop Using True Single Phase Clock (TSPC) Swetha Kanchimani M.Tech (VLSI Design), Mrs.Syamala Kanchimani Associate Professor, Miss.Godugu Uma Madhuri Assistant Professor, ABSTRACT:
More informationISSCC 2003 / SESSION 19 / PROCESSOR BUILDING BLOCKS / PAPER 19.5
ISSCC 2003 / SESSION 19 / PROCESSOR BUILDING BLOCKS / PAPER 19.5 19.5 A Clock Skew Absorbing Flip-Flop Nikola Nedovic 1,2, Vojin G. Oklobdzija 2, William W. Walker 1 1 Fujitsu Laboratories of America,
More information