Monolithic Optoelectronic Integration of High- Voltage Power FETs and LEDs

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Reginald Anthony
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Paul Chow Smart Lighting Engineering Research Center Rensselaer Polytechnic Institute, Troy, NY

1 Monolithic Optoelectronic Integration of High- Voltage Power FETs and LEDs, Zhongda Li, Robert Karlicek and T. Paul Chow Smart Lighting Engineering Research Center Rensselaer Polytechnic Institute, Troy, NY USA Acknowledgement: This work was supported primarily by the Engineering Research Centers Program (ERC) of the National Science Foundation under NSF Cooperative Agreement No. EEC

2 Outline Introduction Material Properties Motivation Integration Methods for Power FETs and LEDs Advantages and Risks of Different Integration Approaches Experimental Results Summary Slide 2

3 Material Properties of GaN: LEDs: Introduction Direct bandgap of GaN provides a higher efficacy than what is possible with indirect bandgap SiC Bandgap of 3.4eV allows color tunable quantum wells and/or phosphorescence allowing illumination from visible to ultraviolet wavelengths Power Transistors Critical electric field in GaN is 10 times higher than Silicon, improving the limit for specific on resistance (R on,sp ) 100 fold for the same breakdown voltage Three times higher bandgap energy of GaN compared to Silicon allows for much higher operating temperatures Ability to generate 2D Electron Gas (2DEG) with GaN/AlGaN heterojunction Fabrication GaN is more compatible with Silicon IC processes compared to SiC Slide 3

4 Introduction Motivation: Current LED lighting products require dedicated electronic drivers Large and slow Introduce cost and reliability issues Introduce smart lighting features to LED lighting Visible light communication (VLC) Autonomous and adaptive lighting features Goal: Develop a monolithic solution integrating the power converter, control circuitry and LEDs using GaN technologies Reduce parasitic limitations Improve cost and reliability issues with simplified packaging Investigate risks/rewards of integration approaches Slide 4

Introduction Monolithic Integration LEDs and their associated drivers can be

optimally scaled to maximize efficiency and switching speed of the system

which increase the maximum operating frequency: Inductance can be lowered to

5 Introduction Monolithic Integration LEDs and their associated drivers can be placed much closer compared to a discrete approach Transistors and LEDs are optimally scaled to maximize efficiency and switching speed of the system Minimizing the distance between components reduces the parasitic inductance, which increase the maximum operating frequency: Inductance can be lowered to 40pH! With 50V switching at 200mA switching frequencies in the GigaHertz can be realized! Slide 5

Selective Epi Removal Selective Epi Removal (SER): Logic and LED epis are grown atop the HEMT epi LED MESA etch performed Remaining LED epi removed in electronic regions Logic and power FETs

6 Selective Epi Removal Selective Epi Removal (SER): Logic and LED epis are grown atop the HEMT epi LED MESA etch performed Remaining LED epi removed in electronic regions Logic and power FETs processed Advantages Devices share common epi layers No epi regrowth required (shorter fabrication time) Light can be extracted from top and/or bottom of die Risks Control of etch depth is difficult Thermal budget for processing limits device optimization LED epi on top of electronic epi increases thermal resistance between LED and heat sink Slide 6

planar, aiding photolithography alignment Light can be extracted from top and/or bottom of die Risks Separate epi regrowth cycles adds time/cost to

7 Selective Area Growth Selective Area Growth (SAG): MOSC-HEMT epi is patterned, etched for regions of Logic epi regrowth Logic/HEMT epi etched for LED epi regrowth Epi layers regrown sequentially Advantages Better thermal resistance between devices and heat sink compared to SER Devices are more planar, aiding photolithography alignment Light can be extracted from top and/or bottom of die Risks Separate epi regrowth cycles adds time/cost to fabrication Thermal budget for processing limits device optimization Performance may be degraded at vertical interfaces where regrown epis meet Slide 7

Three-Dimensional Integration 3-D integration: FETs and LEDs processed separately, then bonded Bonding can be achieved at wafer or at chip level

of well-established silicon CMOS technologies to drive GaN MOSC- HEMT Can be benchmarked with commercially available FETs and LEDs Risks 3-D nature

8 Three-Dimensional Integration 3-D integration: FETs and LEDs processed separately, then bonded Bonding can be achieved at wafer or at chip level Advantages FETs and LEDs processed separately, therefore fully optimized Chip level integration can improve yield by using only known good die Enables use of well-established silicon CMOS technologies to drive GaN MOSC- HEMT Can be benchmarked with commercially available FETs and LEDs Risks 3-D nature complicates heat and light extraction Parasitic elements are 2-3x higher compared to SAG and SER 3-D interconnects are necessary May require complicated interposer Slide 8

fabricated to measure 2DEG concentration Purpose: Verify functionality of

9 Experimental Results SER: LED epi was grown over epi for MOSC-HEMT LED MESA etch performed Remaining N+ epi over ½ the wafer was removed MOS capacitors fabricated to measure 2DEG concentration Purpose: Verify functionality of LEDs grown on electronic epi Investigate impact of LED epi growth on 2DEG Slide 9

10 Experimental Results LED: Functioning LED before MOS capacitor fabrication 2DEG: MOS capacitors used to extract 2DEG concentration on original epi and epi from integration Concentration of 2DEG not significantly affected Etch depth of LED epi is achievable without etch-stop layer Shift in CV curve attributed to dry etch damage (no wet etch was performed to recover this damage) Slide 10

11 Summary Merits of monolithic integration have been quantified Three distinct approaches to achieve monolithic optoelectronic integration have been investigated Selective epi removal has been experimentally verified to be an effective approach Slide 11

12 Thank You! Slide 12

Wafer Thinning and Thru-Silicon Vias

Wafer Thinning and Thru-Silicon Vias The Path to Wafer Level Packaging jreche@trusi.com Summary A new dry etching technology Atmospheric Downstream Plasma (ADP) Etch Applications to Packaging Wafer Thinning