2 Marks Q&A. Digital Electronics. K. Michael Mahesh M.E.,MIET. Asst. Prof/ECE Dept.

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1 2 Marks Q&A Digital Electronics 3rd SEM CSE & IT ST. JOSEPH COLLEGE OF ENGINEERING (DMI & MMI GROUP OF INSTITUTIONS) CHENNAI K. Michael Mahesh M.E.,MIET. Asst. Prof/ECE Dept. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 1

2 K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 2

3 a) b) Explain why the decimal answer in (b) is 8 times that of (a). To convert from binary to hexadecimal: Each 4 binary digits are equal to 1 hexadecimal digit: a) ( ) 2 = (1.D0) 16 b) ( ) 2 = (E.8) 16 To convert from binary to decimal: a) ( )2 = (1x2 0 ) + (1x2-1 ) + (1x2-2 ) + (0x2-3 ) + (1x2-4 ) + (0x2-5 ) = (1) + ( ) = (1.8125) 10 b) ( ) 2 = (1x2 3 ) + (1x2 2 ) + (1x2 1 ) + (0x2 0 ) + (1x2-1 ) + (0x2-2 ) = (8+4+2) + (0.5) = (14.5) 10 The decimal answer in (b) is 8 times that of (a) because the binary number in (b) is the same as that in (a) except that the point is shifted to the right 3 digits and this means that it is multiplied by Convert (9B2.1A) H to its decimal equivalent. N = (9 x 16 2 ) + (B x 16 1 ) + (2 x 16 0 ) + (1 x 16-1 ) + (A (10) x 16-2 ) = = (2482.1) Find the decimal equivalent of (346)7. (May,2004) (346) 7. = (3x7 2 ) + (4x7 1 ) + (6x7 0 ) = (181) Convert decimal number to its octal equivalent x 8 = x 8 = ( ) 10 = (0.51) 8 7. Convert the ( )10 to octal. (May, 2010) Integer part: K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 3

4 = (231)8 Fractional part: x 8 = x 8 = x 8 = x 8 = x 8 = x 8 = = ( ) 8 (approximate) ( ) 10 = ( ) 8 8. Convert decimal number to its hex equivalent x 16 = x 16 = Ans = (0.21) Convert the following number from one base to other (65.342) 8 = ( ) 7. (May, 2008) (65.342) 8 = (6x8 1 ) + (5x8 0 ) + (3x8-1 ) + (4x8-2 ) + (2x8-3 ) = ( ) 10 Now, convert this number to base 7. Integer part: Fractional part x 7 = x 7 = x 7 = x 7 = = (0.3042) 7 (65.342)8 = ( ) Convert to hexadecimal number. Integer part: Fractional Part: 0.64 x 16 = A 0.24 x 16 = x 16 = D 0.44 x 16 = K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 4

5 Ans = (16. A3D7) Convert (231.3)4 to base 7. (May, 2005) Convert the given number to decimal, (231.3) 4 = (2x4 2 ) + (3x4 1 ) + (1x4 0 ) + (3x4-1 ) = = (45.75)10 Now, convert this number to base 7. Integer part: Fractional part: 0.75x 7 = x 7 = x 7 = x 7 = = (0.5151)7 (231.3) 4 = ( ) Convert (634) 8 to binary Ans = ( ) Convert the following number from one base to other (Nov, 2006) (a) (354.52) 6 = ( ) 10 (b) (100)10 = ( ) 16. (a) (354.52) 6 = (3x6 2 ) + (5x6 1 ) + (4x6 0 ) + (5x6-1 ) + (2x6-2 ) = = ( ) 10 (354.52) 6 = ( ) 10 (b) (100) 10 (100)10 = (64) A hexadecimal counter capable of counting upto atleast (10,000)10 is to be constructed. What is the minimum number of hexadecimal digits that the counter must have? (May, 2004) Soln: K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 5

6 (10,000) 10 = (2710) 16 Complements : 15. What are the different types of number complements? i) r s Complement ii) (r-1) s Complement. 16. What is the range of values that can be represented using n-bit 2 s complement form of representation? What is the corresponding range with n-bit 1 s complement form? (May, 2006) The given number N in the base 2 having n digits. The 2 s complement of N is defined as follows. 2 s complement of N= + (2n-1-1) to (2n-1), Where, n is number of digits. The given number N in the base r= 2 having n digits. The (r-1) s complement of N is defined as follows. 1 s complement of N= + (2n-1-1) to (2n-1-1) Where, N= given number or digit 17. Add ( ) 2 and ( ) (+) Answer = ( ) Substract ( ) 2 from ( ) (-) Answer = (1 1 0) Why complementing a number representation is needed? Complementing a number becomes as in digital computer for simplifying the subtraction operation and for logical manipulation complements are used. 20. Obtain the 1 s and 2 s complement of the following binary numbers: a) b) c) d) e) K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 6

7 Soln: 1 s complement : change every 1 to 0 and vice versa. 2 s complement: change every 1 to 0 and vice versa, then add (1) to the LSB. a) s complement: ( ) 2 2 s complement : (+) ( ) b) s complement: ( ) 2 2 s complement : (+) ( ) c) s complement: ( ) 2 2 s complement : (+) ( ) d) s complement: ( ) 2 2 s complement : (+) ( ) e) s complement: ( ) 2 2 s complement : (+) ( ) Find 2 s complement of ( ) 2 Soln: K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 7

8 s Complement (+) ( ) 2-2 s complement Substract ( ) 2 from ( ) 2 using 2 s complement method. Soln: s Complement of ( ) s complement s comp. of ( ) in 2 s complement form To get the answer in true form, take the 2 s complement and assign negative number to the answer. Answer in true form - ( ) Perform subtraction using 1 s complement (11010) 2 (10000) 2. Y- X = (01010)2 24. Given two binary numbers X = and Y = , perform subtraction. (a) X -Y and (b) Y - X using 2's complements. a) X = (2's complement of Y) Discard end carry Answer: X - Y = ( ) 2 b) Y = (2's complement of X) There is no end carry, So, take 2 s complement again for the above answer. Answer is Y-X = - (2's complement of ) = - ( ) 2 K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 8

9 25. Given two binary numbers X = and Y = , perform subtraction. (a) X -Y and (b) Y - X using 1's complements. a) X - Y = X = (1's complement of Y) Discard end carry = + 1 Answer: X - Y = ( ) 2 b) Y - X = Y = (1's complement of X) There is no end carry. Answer is Y - X = - (1's complement of ) = - ( ) What are the different ways to represent a negative number? (Nov, 2006) The different ways of representing a negative number are i. In ordinary arithmetic, the negative sign is indicated by a minus sign. ii. In signed magnitude representation, in which MSB is indicated as 0 to represent negative number. ii. In signed 1 s complement representation, in which the negative number is indicated by its 1 s complement. iii. In signed 2 s complement representation, in which the negative number is indicated by its 2 s complement. 27. Mention the different type of binary codes? The various types of binary codes are, i. BCD code (Binary Coded decimal). ii. Self-complementing code. iii. The excess-3 (X s-3) code. iv. Gray code. iv. Binary weighted code. v. Alphanumeric code. vi. The ASCII code. viii. Extended binary-coded decimal interchange code (EBCDIC). ix. Error-detecting and error-correcting code. x. Hamming code. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 9

10 28. State the different classification of binary codes? i. Weighted codes ii. Non - weighted codes iii. Reflective codes iv. Sequential codes v. Alphanumeric codes vi. Error Detecting and correcting codes. 29. What is meant by bit? A binary digit is called bit 30. Define byte? Group of 8 bits. 31. State the steps involved in Gray to binary conversion? The MSB of the binary number is the same as the MSB of the gray code number. So write it down. To obtain the next binary digit, perform an exclusive OR operation between the bit just written down and the next gray code bit. Write down the result. 32. What are error detecting codes? (Nov, 2007) When the digital information in the binary form is transmitted from one circuit or system to another circuit or system an error may occur. To maintain the data integrity between transmitter and receiver, extra bit or more than one bit is added in the data. The data along with the extra bit/bits forms the code. Code which allow only error detection are called error detecting codes. 33. Convert gray code into its binary equivalent. Gray Code : Binary Code: State the abbreviations of ASCII and EBCDIC code? ASCII - American Standard Code for Information Interchange. EBCDIC - Extended Binary Coded Decimal Information Code. 35. What is advantage of gray codes over binary number sequence? (May, 2007) The advantage of gray codes over the binary number is that only one bit in the code group changes when going from one number to the next. The gray code is used in applications where the normal sequence of binary number may produce an error or ambiguity during the transition from one number to next. 36. What are basic properties of Boolean algebra? The basic properties of Boolean algebra are commutative property, associative property and distributive property. 37. State the associative property of Boolean algebra. The associative property of Boolean algebra states that the OR ing of several variables results in the same regardless of the grouping of the variables. The associative property is stated as follows: A+ (B+C) = (A+B) +C K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 10

11 38. State the commutative property of Boolean algebra. The commutative property states that the order in which the variables are OR ed makes no difference. The commutative property is: (A+B) = (B+A) 39. State the distributive property of Boolean algebra. The distributive property states that ANDing several variables and ORing the result with a single variable is equivalent to ORing the single variable with each of the several variables and then ANDing the sums. The distributive property is: A+BC= (A+B) (A+C) 40. State De Morgan's theorem. De Morgan suggested two theorems that form important part of Boolean algebra. They are, 1) The complement of a product is equal to the sum of the complements. (A.B)' = A'+B' 2) The complement of a sum term is equal to the product of the complements. (A+B)' = A'.B' 41. State the absorption law of Boolean algebra. The absorption law of Boolean algebra is given by, A+AB=A, A (A+B) =A. 42. Define duality property. Duality property states that, starting with a Boolean relation, you can derive another Boolean relation by 1. Changing each OR sign to an AND sign 2. Changing each AND sign to an OR sign 3. Complementing any 0 or 1 appearing in the expression For Example: A+ A = 1 is A. A = Show that A+A.B = A+B using the theorems of Boolean algebra.(nov, 2005) LHS = A+A.B = A+ AB + A B [ A+AB = A] = A+ B (A+ A ) = A+ B (1) [A+ A = 1] = A+ B 44. What are minterms? (May, 2008) Each individual term in standard SOP form is called minterms 45. What are maxterms? Each individual term in standard POS form is called maxterms. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 11

12 46. Find the minterms of the logical expression Y= A'B'C' +A'B'C +A'BC +ABC' Y = A'B'C' + A'B'C + A'BC + ABC' = m 0 + m 1 +m 3 +m 6 = Σm (0, 1, 3, 6) 47. Convert the given expression in canonical SOP form Y = AC + AB + BC Y = AC + AB + BC = AC (B + B ) + AB (C + C ) + (A + A') BC = ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC = ABC + ABC' +AB'C + AB'C' [A + A =1] = m 7 + m 6 +m 5 +m 4 = Σm (4, 5, 6, 7) 48. Convert the following function into sum of product form (AB+C)(B+C D). (May, 2008) = (AB.B+ B.C+ AB.C D+ C.C D) = AB+ BC+ ABC D [B. B= 1] [C.C = 0] AND each product term having missing literals, by ORing the literals and its complement = AB (C+ C ) (D+ D ) + BC (A+ A ) (D+ D ) + ABC D = (ABC+ ABC ) (D+ D ) + (ABC+ A BC) (D+ D ) + ABC D = ABCD+ ABCD + ABC D+ ABC D + ABCD+ ABCD + A BCD+ A BCD + ABC D = ABCD+ ABCD + ABC D+ ABC D + A BCD+ A BCD. = m 15 + m 14 + m 13 + m 12 + m 7 + m 6 F(A,B,C,D)= Σm( 6,7, 12,13,14,15) 49. Write the maxterms corresponding to the logical expression Y = (A + B + C ) (A + B' + C') (A' + B' + C) = (A + B + C ) (A + B' + C') (A' + B' + C) =M 1.M 3.M 6 = П M (1, 3, 6) 50. Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x (y'z' + yz). By applying De-Morgan's theorem. F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z) (x + y +z') F2' = [x (y'z' + yz)]' = x' + (y'z' + yz)' = x' + (y'z')'(yz)' = x' + (y + z) (y' + z') 51. Find the complements for the following functions (a) F1= xy + x y. (b) F2= (xy + y z + xz) x. (Nov, 2007) K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 12

13 (a) F1= xy + x y F1 = (xy + x y) = (xy ). (x y) = (x +y) (x+y ) = x x+ x y + yx+ yy = x y + xy. (b) F2= (xy + y z + xz) x. F2 = ((xy + y z + xz) x) = (xy + y z + xz) + x = [(xy) (y z) (xz) ] + x = [(x +y ) (y+z ) (x +z )] + x = [(x y+ x z + 0+ y z ) ( x +z )] + x = x x y+ x x z + x y z + x yz + x z z + y z z + x = x y+ x z + x y z + x yz + x z + y z + x [x+ x = x], [x. x = x] = x y+ x z + x z (y + y) + y z + x [x+ x = 1] = x y+ x z + x z (1) + y z + x = x y+ x z + y z + x = x y+ x + x z + y z = x (y+1) + x z+ y z [y+1= 1] = x (1+z) + y z [y+1= 1] = x + y z 52. Obtain the complement of f = wx y + xy + wxz using De Morgan s theorem. (May, 2006) f = (wx y + xy + wxz) = (wx y) (xy ) (wxz) = (w +x+ y ) (x + y) (w + x + z ) = (w x + w y+ xx + xy+ x y + yy ) (w + x + z ) = (w x + w y+ xy+ x y ) (w + x + z ) = w x. w + w y. w + xy. w + x y. w + w x. x +w y. x + xy. x + x y. x +w x. z + w y. z + xy. z + x y.z = w x + w y+ w xy+ w x y + w x + w x y+ 0 + x y + w x z + w yz + xyz + x y z = w x + w y+ w xy+ w x y + w x y+ x y + w x z + w yz + xyz + x y z = w x ( 1+ y + y+ z )+ w y( 1+ x+ z )+ x y (1+ z )+ xyz = w x (1)+ w y(1)+ x y (1)+ xyz = w x + w y+ x y + xyz 53. Simplify the following using De Morgan's theorem [((AB)'C)'' D]' L.H.S. = [((AB)'C)'' D]' K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 13

14 = ((AB)'C)'' + D' [(AB)' = A' + B'] = (AB)' C + D' = (A' + B ) C + D' 54. Reduce A'B'C' + A'BC' + A'BC A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C = A'C' + A'BC [A + A' = 1] = A'(C' + BC) = A'(C' + B) [A + A'B = A + B] 55. Reduce A.A'C A.A'C = 0.C [A.A' = 0] = Reduce AB + (AC)' + AB C (AB + C) AB + (AC)' + AB C (AB + C) = AB + (AC)' + AAB'BC + AB'CC = AB + (AC)' + AB'CC [A.A' = 0] = AB + (AC)' + AB'C [A.A = 1] = AB + A' + C' =AB'C [(AB)' = A' + B'] = A' + B + C' + AB'C [A + AB' = A + B] = A' + B'C + B + C' [A + A'B = A + B] = A' + B + C' + B'C = A' + B + C' + B' = A' + C' + 1 = 1 [A + 1 =1] 57. Simplify the following expression Y = (A + B) (A + C ) (B' + C ) Y = (A + B) (A + C ) (B' + C ) = (AA' + AC +A'B +BC) (B' + C') [A.A' = 0] = (AC + A'B + BC) (B' + C ) = AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC' = AB'C + A'BC' 58. Show that (X + Y' + XY)( X + Y')(X'Y) = 0 (X + Y' + XY)(X + Y')(X'Y) = (X + Y' + X) (X + Y ) (X' + Y) [A + A'B = A + B] = (X + Y ) (X + Y ) (X'Y) [A + A = 1] = (X + Y ) (X'Y) [A.A = 1] = X.X' + Y'.X'.Y = 0 [A.A' = 0] 59. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC ABC + ABC' + AB'C + A'BC = AB(C + C') + AB'C + A'BC = AB + AB'C + A'BC K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 14

15 = A (B + B'C) + A'BC = A (B + C) + A'BC = AB + AC + A'BC = B (A + C) + AC = AB + BC + AC = AB + AC +BC...Proved 60. Reduce A (A + B) A (A + B) = A.A + A.B = A + A.B = A (1 + B) [1 + B = 1] = A. 61. Simplify the following Boolean function: (a) x (x +y) (b) xy + x z + yz. (May, 2007) (a) x (x +y) = xx + xy = xy. [x. x = 0] (b) xy + x z + yz. = xy + x z + yz( x+ x ) = xy + x z + xyz + x yz = xy + xyz + x z +x yz = xy (1+ z) + x z (1+y) [1+y= 1] = xy+ x z. 62. Simplify the following Boolean functions to a minimum number of literals a) (x + y) (x + y ) b) xy + x z + yz (May, 2010) a) (x+ y) (x+ y ) = x.x+ xy + yx+ yy = x+ xy + xy+ 0 [ x. x= x]; [ y. y = 0] = x (1+ y + y) = x (1) [ 1+y= 1 ] = x. b) xy + x z + yz. = xy + x z + yz (1) = xy + x z + yz (x+ x ) [x+ x = 1] = xy + x z + xyz + x yz Re-arranging, = xy + xyz + x z +x yz = xy (1+ z) + x z (1+y) K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 15

16 = xy (1) + x z (1) [1+y= 1]; [1+z= 1] = xy+ x z. 63. Simplify the following expression Y = (A + B) (A + C) (B + C) = (A A + A C + A B + B C) (B + C) = (A C + A B + B C) (B + C) = A B C + A C C + A B B + A B C + B B C + B C C = A B C 64. Find the minterm of xy+yz+xy'z (Nov, 2008) = xy+ yz+ xy z = xy+ z (y+ xy ) = xy+ z (y+ x) [x+ x y = x+ y] 65. Simplify the following Boolean expression to a minimum number of literals: A B + A C D + A B D+ A B CD (May, 2009) = A B (1+D) + A C D + A B CD = A B (1) + A C D + A B CD [1+ x = 1] = A B + A C D + A B CD = A B + A B CD + A C D = A B (1+CD ) + A C D = A B (1) + A C D [1+ x = 1] = A B + A C D = A (B +C D ) Simplification Of Boolean functions using K-map & Tabulation Methods : 66. What are the methods adopted to reduce Boolean function? i) Karnaugh map ii) Tabular method or Quine Mc-Cluskey method iii) Variable entered map technique. 67. What is a Karnaugh map? A Karnaugh map or k map is a pictorial form of truth table, in which the map diagram is made up of squares, with each squares representing one minterm of the function. 68. What is meant by three variable map? Three variable map have 8 minterms for three variables, hence the map consists of 8 squares, one for each minterm. 69. What is a prime implicant? A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map. 70. What is an essential implicant? If a min term is covered by only one prime implicant, the prime implicant is said to be essential. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 16

17 71. What are called don t care conditions? In some logic circuits certain input conditions never occur, therefore the corresponding output never appears. In such cases the output level is not defined, it can be either high or low. These output levels are indicated by X or d in the truth tables and are called don t care conditions or incompletely specified functions. 72. Simplify the following Boolean function by Karnaugh map method: F (A, B, C, D) = Σm (1, 5, 9, 12, 13, 15) (May, 2009) 73. What are the drawbacks of Karnaugh map? (Nov, 2007) The drawbacks of the K-map method are i. Generally it is limited to six variable map (i.e.) more than six variable involving expressions are not reduced. ii. The map method is restricted in its capability since they are useful for simplifying only Boolean expression represented in standard form. iii. It is not suitable for computer reduction. iv. Care must be taken to fill in every cell with the relevant entry, such as a 0, 1 (or) don t care terms. 74. Explain or list out the advantages and disadvantages of K-map method? The advantages of the K-map method are i. It is a fast method for simplifying expression up to four variables. ii. It gives a visual method of logic simplification. iii. Prime implicants and essential prime implicants are identified fast. iv. Suitable for both SOP and POS forms of reduction. v. It is more suitable for class room teachings on logic simplification. The disadvantages of the K-map method are i. It is not suitable for computer reduction. ii. K-maps are not suitable when the number of variables involved exceed four. iii. Care must be taken to fill in every cell with the relevant entry,such as a 0,1 (or) don t care terms. 75. Why we go in for tabulation method? This method can be applied to problems with many variables and has the advantage of being suitable for machine computation. 76. List out the advantages and disadvantages of Quine Mc-Cluskey method? K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 17

18 The advantages are, i. This is suitable when the number of variables exceed four. ii. Digital computers can be used to obtain the solution fast. iii. Essential prime implicants, which are not evident in K-map, can be clearly seen in the final results. The disadvantages are, i. Lengthy procedure than K-map. ii. Requires several grouping and steps as compared to K-map. iii. It is much slower. iv. No visual identification of reduction process. v. The Quine Mc-Cluskey method is essentially a computer reduction method. 77. What is a Logic gate? Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that is able to operate on a number of binary inputs in order to perform a particular logical function. 78. Distinguish between positive logic and negative logic. (Nov, 2003) In binary logic, two voltage levels represent the two binary digits, 1 and 0. If the higher of the two voltages represents a 1 and the lower voltage represents a 0, the system is called positive logic system. On the other hand, if the lower voltage represents a 1 and the higher voltage represents a 0, then it is a negative logic system. 79. What are the basic digital logic gates? The three basic logic gates are AND gate OR gate NOT gate 80. Which gates are called as the universal gates? What are its advantages? The NAND and NOR gates are called as the universal gates. These gates are used to perform any type of logic application. 81. Bubbled OR gate is equal to NAND gate 82. Bubbled AND gate is equal to NOR gate 83. How will you use a 4 input NOR gate as a 2 input NOR gate? (May, 2003) By connecting unused inputs to logic 0, we can use 4-input NOR gate as a 2 input NOR gate. 84. How will you use a 4 input NAND gate as a 2 input NAND gate? (Nov, 2002) By connecting unused inputs to logic 1, we can use 4-input NAND gate as a 2 input NAND gate. 85. What is meant by a functionally complete set of logic gates? (May, 2005) A set of logic gates by which we can implement any logic function is called functionally complete set of logic gates. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 18

19 86. Show that a positive logic NAND gate is the same as a negative logic NOR gate. (May, 2003; Nov, 2004) Logic expression for NAND gate is, Y= (A.B) Y = (A.B) = A +B Y= A + B is the logic expression for negative logic NOR gate. 87. What happens when all the gates is a two level AND-OR gate network are replaced by NOR gate (May, 2004; Nov, 2004, IT) The output will change. We will get complemented output when all applied inputs are complemented. 88. Realize OR gate using NAND gate. (Nov, 2005) 1. Define Combinational circuit. (May 2009) A combinational circuit consists of logic gates whose outputs at any time are determined directly from the present combination of inputs, without regard to previous inputs. 2. What is a half-adder? A half-adder is a combinational circuit that can be used to add two bits. It has two inputs that represent the two bits to be added and two outputs, with one producing the SUM output and the other producing the CARRY. 3. Give the truth table for a half adder. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 19

20 4. From the truth table of a half adder derive the logic equation 5. Draw the logic diagram of a half-adder. (Nov, 05; Nov 09) 6. What is a full adder? (May, 2007) A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of 3 inputs and 2 outputs. Two of the input variables, represent the significant bits to be added. The third input represents the carry from previous lower significant position. The block diagram of full adder is given by, 7. Give the truth table for a full adder. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 20

21 8. From the truth table of a full adder derive the logic equation 9. Draw the circuit of a full-adder. 10. What is half-subtractor? A half-subtractor is a combinational circuit that can be used to subtract one binary digit from another to produce a DIFFERENCE output and a BORROW output. The BORROW output here specifies whether a 1 has been borrowed to perform the subtraction. 11. Give the truth table for a half Subtractor. (Nov, 2005) 12. From the truth table of a half-subtractor derive the logic equation K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 21

22 13. Draw the circuit of a half-subtractor. 14. What is a full-subtractor? A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and also takes into consideration whether a 1 has already been borrowed by the previous adjacent lower minuend bit or not. As a result, there are three bits to be handled at the input of a full subtractor, namely the two bits to be subtracted and a borrow bit designated as Bin. There are two outputs, namely the DIFFERENCE output D and the BORROW output Bo. The BORROW output bit tells whether the minuend bit needs to borrow a 1 from the next possible higher minuend bit. 15. Give the truth table for a full-subtractor. (Nov, 2004) 16. From the truth table of a full-subtractor derive the logic equation 17. Draw the circuit of a full-subtractor. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 22

23 18. What is Binary parallel adder? A binary parallel adder is a digital function that produces the arithmetic sum of two binary numbers in parallel. 19. What is BCD adder? A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD. 20. What are Parity Generator/ Checker? A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included in a binary message to make the number of 1 s either odd or even. The message, including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. 21. Draw the circuit diagram for 3-bit parity generator. (Nov, 2007) 22. Draw the logic diagram of 4 bit even parity checker. (Nov, 2008) 23. What is Magnitude Comparator? A Magnitude Comparator is a combinational circuit designed primarily to compare the relative magnitude of two binary numbers. It receives two n-bit numbers A and B as inputs and the outputs are A>B, A=B and A<B. Depending upon the relative magnitudes of the two numbers, one of the outputs will be high. 24. List out the applications of comparators? The following are the applications of comparator Comparators are used as a part of the address decoding circuitry in computers to select a specific input/output device for the storage of data. They are used to actuate circuitry to drive the physical variable towards the reference value. They are used in control applications. 25. What is the need for code conversion? (May, 2009) If two systems working with different binary codes are to be synchronized in operation, then we need digital circuit which converts one system of codes to the other. The process of conversion is referred to as code conversion. 26. What is code converter? It is a circuit that makes the two systems compatible even though each uses a different binary code. It is a device that converts binary signals from a source code to its output code. One example is a BCD to Xs3 converter. 27. Construct a 4-bit binary to gray code converter circuit and discuss its operation. (May, 2006) The gray code is often used in digital systems because it has the advantage that only bit in the. numerical representation changes between successive K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 23

24 28. What is logic synthesis in HDL? (Nov, 2006; Nov, 2007) Logic Synthesis is the automatic process of transforming a high level language description such as HDL into an optimized netlist of gates that perform the operations specified by the source code. It is the process of deriving a list of components and their interconnections from the model of a digital system described in HDL. 29. List the important features of HDL. (Nov, 2006; May 2010) 1. It is specifically oriented to describe hardware structures and behaviors. 2. It can be used to represent logic diagrams, Boolean expressions and other complex digital circuits. 3. It is used to represent and document digital systems in a form that can be read by both humans and computers. 30. Mention any two uses of HDL. (May, 2006) 1. HDL is a language that describes the hardware of digital systems in textural form. 2. It can be used to represent logic diagrams, Boolean expressions and other more complex digital circuits. 3. It is used to represent and document digital systems in a form that can be read by both humans and computers. 4. The language content can be stored and retrieved easily and processed by computer software in an efficient manner. 1. What do you mean by analyzing a combinational circuit? The reverse process for implementing a Boolean expression is called as analyzing a combinational circuit. (ie) the available logic diagram is analyzed step by step and finding the Boolean function. 2. What is decoder? (May,09) A decoder is a combinational circuit that decodes the binary information on n input lines to a maximum of 2n unique output lines. The general structure of decoder circuit is 3. What is encoder? (May,10) An encoder is a combinational circuit that converts binary information from 2n input lines to a maximum of n unique output lines. The general structure of encoder circuit is K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 24

25 4. List out the applications of decoder? 1. Decoders are used in counter system. 2. They are used in analog to digital converter. 3. Decoder outputs can be used to drive a display system. 5. What are the functions of encoders and decoders? (Nov,2006) An encoder is a combinational circuit that converts binary information from 2n input lines to a maximum of n unique output lines. A decoder is a combinational circuit that decodes the binary information on n input lines to a maximum of 2n unique output lines. 6. Distinguish between decoder and encoder 7. Implement the logic function f= Σm (0, 2, 3, 6) using a decoder (May, 2006) 8. What is priority encoder? (May, 2008, May,2007) A priority encoder is an encoder that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 25

26 9. What is a multiplexer? (Nov, 06;May 10) A multiplexer is a digital switch which allows digital information from several sources to be routed into a single output line. The basic multiplexer has several data-input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input lines and n selection lines. 10. What is the function of the enable input in a Multiplexer? The function of the enable input in a MUX is to control the operation of the unit. 11. Implement the logic function f= AB + A.B using a suitable multiplexer.(nov, 2005) f= AB + A B = Σm (3, 0) 12. How can a multiplexer be used to convert 8-bit parallel data into serial form? Draw the circuit and briefly explain. (May, 2006) K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 26

27 Here, binary counter is used to derive the select inputs of the multiplexer so that as the binary counter increments its count, the next bit is available at the output of the multiplexer. The binary counter counts from 000 to 111, therefore D0 through D7 bits are available at the output of the multiplexer as serial output. 13. Mention the uses of multiplexer. 1. It can be used to realize a Boolean function 2. It can be used in communication systems e.g., time division multiplexing. 14. Mention any two applications of multiplexers. (May, 07; May, 09) 1. Data routing 2. Logic function generator 3. Control sequencer 4. Parallel-to-serial converter. 15. Construct a 16 1 multiplexer with two 8 1 multiplexer and 2 1 multiplexer. (Nov, 2008) 16. What is a demultiplexer? (May 2008) A demultiplexer is a combinational logic circuit with an input line, 2n output lines and n select lines. It routes the information present on the input line to any of the output lines. The output line that gets the information present on the input line is decided by the bit status of the selection lines. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 27

28 17. Mention the uses of Demultiplexer. Demultiplexer is used in computers when a same message has to be sent to different receivers. Not only in computers, but any time information from one source can be fed to several places. 18. How can a decoder be converted into a demultiplexer? (Nov, 2005) Decoder is a circuit which converts one form of code into another. Demultiplexer is a circuit which converts one input to many outputs. If the enable line E is taken as a data input line A and B are taken as selection lines, then it is a demultiplexer. 19. Can a decoder function as a Demultiplexer? Yes. A decoder with enable can function as a Demultiplexer if the enable line E is taken as a data input line A and B are taken as selection lines. 20. Give the applications of Demultiplexer. 1. It finds its application in Data transmission system with error detection. 2. One simple application is binary to Decimal decoder. 21. Give other name for Multiplexer and Demultiplexer. Multiplexer is otherwise called as Data selector. Demultiplexer is otherwise called as Data distributor. 22. Distinguish between decoder and demultiplexer. (May, 04; Nov, 09) 1 multiplexer using two 4:1 multiplexers. 23. Design 8: 24. Design 1: 8 demultiplexer using two 1: 4 demultiplexers. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 28

29 25. Define address and word Each bit combination of the input variable is called on address. Each bit combination that comes out of the output lines is called a word. 26. What is RAM? A memory unit is a collection of storage cells together with associated circuits needed to transfer information in and out of the device. The time it takes to transfer information to or from any desired random location is always the same. Hence, the name random-access memory (RAM). 27. List the types of RAM. 1. Static RAM 2. Dynamic RAM 28. Explain SRAM? 1. Static RAM (SRAM) consists of internal latches that store the binary information. The stored information remains valid as long as the power is applied to the unit. 2. SRAM is easier to use and has shorter read and write cycle. 3. The memory capacity of a static RAM varies from 64 bit to 1 mega bit. 29. Explain DRAM? 1. The dynamic RAM (DRAM) stores the binary information in the form of electric charges on capacitors. The capacitors are provided inside the chip by MOS transistors. Dynamic RAM 2. The stored charges on the capacitors tend to discharge with time and the capacitors must be tending to discharge with time and the capacitors must be periodically recharged by refreshing the dynamic memory. 3. DRAM offers reduced power consumption and larger storage capacity in a single memory chip. 30. Differentiate static RAM and dynamic RAM. 31. Differentiate volatile and non-volatile memory? K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 29

30 32. What are the advantages of RAM? The advantages of RAM are 1. Non-destructive read out 2. Fast operating speed 3. Low power dissipation 4. Compatibility 5. Economy. 33. In what ways memory expansion can be achieved? The memory expansion can be achieved in two ways: 1. By expanding word size, 2. By expanding memory capacity. 34. How memory expansion can be achieved by expanding word size? The word size of the memory IC can be increased by connecting two memory IC s in such a way that their data bus is in series and address bus in parallel. Both memory IC s are selected simultaneously by common chip select signal to access entire expanded word at time. 35. How memory expansion can be achieved by expanding memory capacity? The memory capacity can be increased by connecting two or more memory IC s in parallel ie., the address, data and control lines are connected in parallel to all memory IC s. Each IC is selected by the separate chip select signal generated by the address decoder. 36. What is ROM? A Read-only memory (ROM) is essentially a memory device in which permanent binary information is stored. The binary information must be specified by the designer and is then embedded in the unit to form the required interconnection pattern. Once the pattern is established, it stays within the unit even when power is turned OFF and ON again. 37. List the types of ROM. 1. Masked ROM, 2. Programmable ROM (PROM) 3. Erasable ROM (EPROM) 4. Electrically Erasable ROM (EEROM) 38. Explain masked ROM. In masked ROM, mask programming is done by the manufacturer during the last fabrication process of the unit. The procedure for fabricating a ROM requires that the customer fill out the truth table, the ROM is to satisfy. 39. Explain PROM. The PROM (Programmable Read-only memory), allows user to store data/ program. It uses the fuses with material like nichrome and polycrystalline. The user can blow the fuses by passing around ma of current for a period of 5 20 μsec. The blowing of fuses according to the truth table is called programming of ROM. The PROM programmer selectively burns the fuses according to the bit pattern to be stored. The PROM s are one-time programmable, once programmed, the information stored is permanent. 40. Explain EPROM. The EPROM (Erasable PROM), uses MOS circuitry. They store 1 s and 0 s as packets of charge in a buried layer of IC chip. It can be programmed by the user by a special EPROM programmer. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 30

31 The information stored can be erased by exposing the chip to Ultraviolet through its quartz window for 15 to 20 minutes. In EPROM s, it is not possible to erase selective information, when erased the entire information is lost. The chip can be reprogrammed. It is ideally suited for product development, college laboratories, etc. 41. Explain EEPROM. The EEPROM (Electrically Erasable PROM), also uses MOS circuitry. Data is stored as charge or no charge on an insulating layer, which is made very thin (< 200A). Therefore a voltage as low as 20-25V can be used to move charges across the thin barrier in either direction for programming or erasing ROM. It allows selective erasing at the register level rather than erasing all the information, since the information can be changed by using electrical signals. It has chip erase mode by which the entire chip can be erased in 10 msec. Hence EEPROM s are most expensive. 42. What is a Programmable logic device (PLD)? A Programmable logic device (PLD) is an integrated circuit with internal logic gates that are connected through electronic fuses. Programming the device involves blowing the fuses along the paths that must be disconnected so as to obtain a particular configuration. It is divided into an AND array and an OR array to provide an AND-OR sum of product implementation. 43. List basic types of programmable logic devices. 1. PROM: Programmable Read only memory, 2. PLA: Programmable logic Array, 3. PAL: Programmable Array Logic, 4. FPGAs: Field programmable Gate Arrays, 5. CPLDs: Complex programmable Logic Devices. 44. Explain PROM? The Programmable read-only memory has a fixed AND array constructed as a decoder and programmable OR array. The programmable OR gates implement the Boolean function in sum of minterms. 45. Explain PAL? It has a programmable AND array and a fixed OR array. The AND gates are programmed to provide the product terms for the Boolean functions, which are logically summed in each OR gate. 46. Explain PLA The most flexible PLD is the programmable logic array (PLA), where both the AND and OR arrays can be programmed. The product term in the AND array may be shared by any OR gate to provide the required sum of product implementation. 47. Differentiate ROM & PLD s. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 31

32 48. What are the difference between PLA and PAL? (Nov, 2006) 49. Give differences between PROM, PLA, and PAL. (Nov, 09) 50. What are the terms that determine the size of a PAL? The size of a PAL is specified by the a. Number of inputs b. Number of products terms c. Number of outputs 51. What is meant by memory decoding? The memory IC used in a digital system is selected or enabled only for the range of addresses assigned to it. 52. What is access and cycle time? The access time of the memory is the time to select word and read it. The cycle time of a memory is a time required to complete a write operation. 53. When an overflow condition will encounter in an accumulator register? (Nov, 2007) When the output exceeds the capacity of accumulator. 54. What is the maximum range of a memory that can be accessed using 10 address lines? (May, 2008) Maximum range of memory = 2 address lines. = 210 = 1024 bytes. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 32

33 HDL for Combinational Circuits 55. What is VHDL? VHDL is a hardware description language that can be used to model a digital system at many level of abstraction, ranging from the algorithmic level to the gate level. The VHDL language has a combination of the following language. 1. Sequential language 2. Concurrent language 3. Net-list language 4. Timing specification 5. Waveform generation language. 56. What are the features of VHDL? The features of VHDL are 1. VHDL has powerful constructs. 2. VHDL supports design library. 3. The language is not case sensitive. 57. What is gate level modelling? (Nov, 2007) This technique uses primitive gates and user-defined modules. It describes a schematic diagram in a textural form. 58. What are the modelling techniques available to build HDL module? (May, 2007) 1. Gate level modeling using instantiation of primitive gates and user-defined modules. 2. Data flow modeling, using continuous assignment statements with keyword assign. 3. Behavioral modeling using procedural assignment with keyword always. 59. Define entity? Entity gives the specification of input/output signals to external circuitry. An entity is modeled using an entity declaration and at least one architecture body. Entity gives interfacing between device and others peripherals. 60. List out the different elements of entity declaration? The different elements of entity declaration are: 1. entity_name 2. signal_name 3. mode 4. in: 5. out: 6. input 7. buffer 8. signal_type 61. What do you meant by concurrent statement? Architecture contains only concurrent statements. It specifies behavior, functionality, interconnections or relationship between inputs and outputs. 62. What are operators used in VDHL language? There are different types of operators used in VHDL language Logical operators : AND, OR, NOT, XOR, etc., Relational operator : equal to, <less than etc., Shift operators : SLL- Shift Left Logical, ROR- Rotate Right Logical etc., Arithmetic operators : Addition, subtraction etc., Miscellaneous operators: <= assign to etc., 63. Define VHDL package? A VHDL, package is a file containing definitions of objects which can be used in other programs. A package may include objects such as signals, type, constant, function, procedure and component declarations. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 33

34 1. What is sequential circuit? The circuits in which the output variables depend not only on the present input but they also depend upon the past history of these input variables are known as sequential circuits. Block diagram of sequential circuit The memory elements are connected to the combinational circuit as a feedback path. The present state and the external inputs determine the outputs and the next state of the sequential circuit. 2. What are the differences between sequential and combinational logic circuits? (Nov, 2004; Nov, 2007; May 2010) 3. List the classifications of sequential circuit. 1. Synchronous sequential circuit. 2. Asynchronous sequential circuit. 4. What is Synchronous sequential circuit? A Synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signal at discrete instants of time. 5. Mention one advantage and disadvantage of Asynchronous sequential circuit. (Nov, 2005) Advantage: Because of the absence of clock it can operate faster than synchronous sequential circuits. Disadvantage: The charge in input signal can affect memory elements at any instant of time and it is more difficult to design. 6. Distinguish between synchronous and asynchronous sequential logic circuits. (Nov, 2002; Nov, 2003; May, 2005) K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 34

35 7. What is a clocked sequential circuit? Synchronous sequential circuit that use clock pulses in the inputs of memory elements are called clocked sequential circuit. One advantage as that they don t cause instability problems. 8. What is called latch? Latch is a simple memory element, which consists of a pair of logic gates with their inputs and outputs inter connected in a feedback arrangement, which permits a single bit to be stored. Enable signal is provided with the latch. When enable signal is active, output changes with output. When enable signal is not activated, input changes does not affect output. 9. Draw the internal circuit of a NOR gate latch and derive the truth table. (May, 2006) The SR latch is a digital circuit with two inputs S and R and two cross-coupled NOR gates. Truth table 10. Draw the logic diagram of D-type latch. (Nov, 2007) K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 35

36 11. What is flip-flop? Flip-Flops are synchronous bistable devices (has two outputs Q and Q ). An edge-triggered Flip-Flop changes state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock. 12. Differentiate Flip-flops from Latches. (May, 2010) Latch is a sequential device that checks all of its inputs continuously and changes its outputs according to any time, independent of a clocking signal. Flip-flop is a sequential device that samples its inputs and changes its outputs only at times determined by clocking signal. 13. List different types of flip-flops. i) SR flip-flop ii) JK flip-flop iii) D flip-flop iv) T flip-flop 14. What do you mean by triggering of flip-flop? The state of a flip-flop is switched by a momentary change in the input signal. This momentary change is called a trigger and the transition it causes is said to trigger the flip-flop. 15. Draw the diagram of a clocked SR flip-flop using four NAND gates. (Nov, 2004) 16. Draw the logic diagram for clocked D Flip-Flop. 17. Draw the logic diagram for clocked JK Flip-Flop. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 36

37 18. What is a characteristic table? A characteristic table defines the logical property of the flip-flop by describing its operation in tabular form. 19. Draw the logic diagram for T Flip-Flop. (May, 2008) 20. Draw the logic diagram for Master-slave SR Flip-Flop. 21. What is race around condition? How can it be avoided? (May, 09; Nov, 09) In a JK latch, when J and k are both high, then the output toggles continuously. This condition is called a race around condition. Due to this, in the positive half cycle of the clock pulse (Enable), if J and K both are HIGH, then the output toggles continuously. To avoid this condition, an edge triggered or pulse triggered JK flip-flop is created. In this flip-flop, the output changes only at the positive edge or a negative edge of the clock. 22. Write down the characteristic table of SR flip flop. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 37

38 23. Write down the characteristic table of JK flip flop. (Nov, 2008) 24. Write down the characteristic table of D flip flop. 25. Write down the characteristic table of T flip flop. 26. What is an excitation table? During the design process we usually know the transition from present state to next state and wish to find the flip-flop input conditions that will cause the required transition. A table which lists the required inputs for a given chance of state is called an excitation table. 27. Give the excitation table of a SR flip-flop. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 38

39 28. Give the excitation table of a JK flip-flop. 29. Give the excitation table of a T flip-flop. 30. Give the excitation table of a D flip-flop. 31. Derive the characteristic equation of a JK flip-flop. (May, 2003) Characteristic Equation: Qn+1= JQ + K Q. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 39

40 32. Derive the characteristic equation of a D flip-flop. (Nov, 2002, IT) Characteristic Equation: Qn+1= D. 33. Derive the characteristic equation of a T flip-flop. (May, 2004, IT) Characteristic equation: Qn+1= TQn + T Qn 34. What is the difference between truth table and excitation table? i) An excitation table is a table that lists the required inputs for a given change of state. ii) A truth table is a table indicating the output of a logic circuit for various input states. 35. How will you convert a SR flip-flop into D flip-flop? SR to D Flip-Flop K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 40

41 36. How will you convert a SR flip-flop into JK flip-flop? SR to JK Flip-Flop 37. How will you convert a SR flip-flop into T flip-flop? SR to T Flip-Flop 38. How will you convert a JK flip-flop into T flip-flop? JK to T Flip-Flop K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 41

42 39. How will you convert a JK flip-flop into D flip-flop? 40. How will you convert a D flip-flop into T flip-flop? JK to D Flip-Flop D to T Flip-Flop 41. How will you convert a T flip-flop into D flip-flop? T to D Flip-Flop 42. What are the models used to represent clocked sequential circuits? (Nov, 2006) The clocked sequential circuits are represented by two models as 1. Moore circuit, 2. Mealy circuit. 43. What is the difference between a Mealy machine and Moore machine? (Nov, 2008; May, 2005) K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 42

43 44. Define state of sequential circuit? The binary information stored in the memory elements at any given time defines the state of sequential circuits. 45. Define state diagram. A graphical representation of a state table is called a state diagram. 46. What is the use of state diagram? i) Behavior of a state machine can be analyzed rapidly. ii) It can be used to design a machine from a set of specification. 47. What is state table? A table, which consists time sequence of inputs, outputs and flip-flop states, is called state table. Generally it consists of three section present state, next state and output. 48. A reduced state table has 14 rows. What is the minimum number of flip-flops needed to build the sequential circuit? (Nov, 2004) Therefore, 4 flip-flops. 49. What is a state equation? A state equation also called, as an application equation is an algebraic expression that specifies the condition for a flip-flop state transition. The left side of the equation denotes the next state of the flip-flop and the right side; a Boolean function specifies the present state. 50. What is counter? A counter is used to count pulse and give the output in binary form. 51. What is synchronous counter? In a synchronous counter, the clock pulse is applied simultaneously to all flipflops. The output of the flip-flops changes state at the same instant. The speed of operation is high compared to an asynchronous counter. 52. What is an Asynchronous/ ripple counter? In an Asynchronous counter, the clock pulse is applied to the first flip-flops. The change of state in the output of this flip-flop serves as a clock pulse to the next flip-flop and so on. Here all the flip-flops do not change state at the same instant and hence speed is less. 53. What is the difference between synchronous and asynchronous counter? 54. What is up counter? K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 43

44 A counter that increments the output by one binary number each time a clock pulse is applied. 55. What is down counter? A counter that decrements the output by one binary number each time a clock pulse is applied. 56. What is up/down counter? A counter, which is capable of operating as an up counter or down counter, depending on a control lead (Up/ down). 57. What is a ripple counter? A ripple counter is nothing but an asynchronous counter, in which the output of the flip-flop changes state like a ripple in water. 58. What are the uses of a counter? 1. The digital clock 2. Auto parking control 3. Parallel to serial data conversion. 59. What is meant by modulus of a counter? By the term modulus of a counter we say it is the number of states through which a counter can progress. 60. What is meant by natural count of a counter? By the term natural count of a counter we say that the maximum number of states through which a counter can progress. 61. A ripple counter is a sequential counter. Ans: Asynchronous. 62. What is modulo-n counter? (May, 2008) A modulo-n counter is a counter of that goes through a repeated sequence of N counts. 63. The number of flip-flops required for modulo-18 counter is n N Therefore, five flip-flops are required. 64. What is the minimum number of flip-flops needed to build a counter of modulus- 8? (May, 2004) 2n N 23 8 Therefore, three flip-flops are required. 65. How many flip-flops are required for designing synchronous MOD50 counter? (May, 2009) 2n N 26 8 Therefore, six flip-flops are required. 66. Form the truth table for 3-bit binary down counter. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 44

45 67. What is a ring counter? A counter formed by circulating a bit in a shift register whose serial output has been connected to its serial input. 68. What is BCD counter? A BCD counter counts in binary coded decimal from 0000 to 1001 and back to Because of the return to 0000 after a count of 1001, a BCD counter does not have a regular pattern as in a straight binary counter. 69. What is a binary counter? (Nov, 2006) A counter that follows the binary sequence is called binary counter. An n-bit binary counter consists of n flip-flops and can count in binary from 0 to 2n What are the uses of a ring counter? i) Control section of a digital system. ii) Controlling events, which occur in strict time sequence. 71. State the relative merits of series and parallel counters. (May, 2003) In comparison with parallel counters the serial counters have simple logic circuits; however, serial counters are low speed counters as the clock is propagated through number is flip-flops before it reaches the last flip-flop. 72. What is Johnson counter? It is a ring counter in which the inverted output is fed into the input. It is also known as a twisted ring counter. 73. What is a cycle counter? A cycle counter is a counter that outputs a stated number of counts and then stops. 74. What is a register? Memory elements capable of storing one binary word. It consists of a group of flip-flops, which store the binary information. 75. What is a shift register? (Nov, 2003) A register capable of shifting its binary information in one or both directions is called shift register. The logical configuration of a shift register consists of a chain of flip-flops in cascade, with the output of one flipflop connected to the input of the next flip-flop. All flip-flops receive common clock pulses, which activate the shift from one stage to the next. 76. What is serial shifting? In a shift register, if the data is moved 1 bit at a time in a serial fashion, then the technique is called serial shifting. K. Michael Mahesh M.E.,MIET Asst.Prof/ECE Dept Page 45