On the Design of Three-Valued Asynchronous Modules

Transcription

1 IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 10, OCTOBER 1980 Pierre G. Jansen was born in Blerick, The Netherlands, in He receied the M.Sc. degree in electrical engineering with honors from the Technical Uniersity at Eindhoen, The Netherlands, in In 1970 he joined the Philips Research Laboratories and started to work in the fault diagnostic field. Since 1976 he has been engaged in research on multiprocessor systems. His current field of interest is the architecture of these systems, logic design, and multialued logic. Joep L. W. Kessels was born in Heerlen, The Netherlands, in He receied the M.Sc. degree with honors from the Technological Uniersity of Eindhoen, The Netherlands, in In 1969 he joined the Philips Research Laboratories where he first worked in the field of programming languages. Since 1976 he has been engaged in research on distributed processing. In this area his main interests are architecture, operating systems, and programming languages. On the Design of Three-Valued Asynchronous Modules ANTHONY S. WOJCIK, MEMBER, IEEE, AND KWANG-YA FANG, MEMBER, IEEE Abstract-The use of three-alued signals in the design of asynchronous speed-independent modules is considered. The three-alued Post algebra is used as the mathematical basis for multialued logic design. Asynchronous operation in a three-alued system is defined. Basis data/control signal detectors and control primities are deeloped. It is shown that the design of the nonbinary modules only requires the use of standard binary design techniques and the detectors and logic primities that are deeloped. A general monitoring and control structure that allows the interconnection of both combinational and sequential modules is described. Index Terms-Asynchronous logic, modular design, multiple-alued logic, Post algebra, speed-independent circuit. I. INTRODUCTION THE analysis and synthesis of asynchronous networks is Ta topic that has attracted the attention of a number of researchers [ I ] - [4]. In particular, the study of asynchronous circuits has led to the deelopment of seeral schemes for designing and controlling networks of interconnected asynchronous modules. One crucial factor underlying the different approaches is the nature of the delays that are assumed to occur in the network. Two of the approaches to network design that are particularly useful with respect to current technology are the "speed-independent circuit" [1], [2] and the "propagationlimited network" [3] models. A basic assumption of the Manuscript receied August 15, 1979; reised May 2, This work was supported in part by the National Science Foundation under Grants MCS A0 I and MCS A. S. Wojcik is with the Department of Computer Science, Illinois Institute of Technology, Chicago, IL K. Y. Fang was with the Atlantic Richfield Company, Harey, IL. He is now with the Western Electric Company, Lisle, IL speed-independent model is that network delay is confined to the logic gates and that intergate (line) delay is zero. The propagation-limited approach assumes that delay between modules is significant while delay within a module is negligible. Taken together, the two iews proide a reasonably accurate model of an asynchronous network composed of interconnected logic modules in which a module might be as small as a single LSI chip. In such a network, one recognizes that there is only limited access aailable to each module. In addition to data paths between modules, it is necessary to hae control paths between them to goern the moement of data and to monitor the operation of the modules themseles. Inclusion of control requires the use of access paths to a module, thus reducing the aailable data paths. Hence, although the potential data processing capability of a module is large, it will be restricted if the number of data paths is limited. One remedy to this problem of maximizing the data processing potential of a module with a fixed number of access paths is to increase the capacity of the data paths by permitting more than two signal leels to be transmitted on each path. In this case, the use of multialued logic circuits in the design of the modules is required. Howeer, merely allowing multialued signals to be used neither ensures that the data processing capability is increased nor guarantees that the control structure will not require more access paths. Further, if the logic design of a nonbinary network is considerably more difficult than that of a binary network, the effort to incorporate the multialued signals may outweigh the benefit resulting from their use in a system. The purpose of this paper is to briefly describe one possible approach to the design of networks composed of asynchronous /80/ $ IEEE

2 890 modules incorporating three-alued signals and logic circuits. The key to this approach is the use of logic design techniques that make the existence of three-alued signals in the system almost transparent to the logic designer. The propagationlimited network approach of Elspas et al. [3] and the speedindependent circuit implementation of Armstrong et al. [2] proide the initial basis for the network structure that will be deeloped. The multialued asynchronous circuit structure described in Wojcik [5]- [7] and Sheafor [8] proide the model of nonbinary operation. A complete exposition of this design approach can be found in Wojcik [9], [13] and Fang [12]. II. MULTIVALUED ASYNCHRONOUS OPERATION The approach to asynchronous design using three-alued logic elements is based upon a special interpretation of the three-alued Post algebra [10]. Let us denote the three logic alues as 0, 1, and 2, and let us assume that the alues are linearly ordered as 0 < 1 < 2. The 0 and 2 alues are to be treated as binary information or data alues while the intermediate I alue is to be used as a control leel. The Post algebra operations of MAX, +, and MIN, -, are the same as the two-alued Boolean operations of OR and AND, respectiely, with respect to the logic alues of 0 and 2. Two-alued Boolean complementation is presered by incorporating the threealued strong negation operation defined by X = 2 - X, where X E 10, 1,21. Table I summarizes these operations and also shows the symbols used to represent them, and the constant functions, in logic circuits. Asynchronous operation requires the following signal behaior. Any signal change from 0 to 2 (2 to 0) must pass through the intermediate control leel 1. This form of signal behaior facilitates the design of hazard-free combinational circuits and allows the use of technologically feasible logic elements [5], [6], [8]. Let us analyze the behaior of a combinational logic circuit that is composed MAX, MIN, and NEGATION gates that is initially set to the control leel 1. In this situation, all gate inputs and outputs are at the 1 leel. As circuit inputs are changed from 1 to either 0 or 2, the only signal changes that can occur within the circuit are those from 1 to 0 and 1 to 2. If we then consider, for example, a term of a logic expression composed of the MIN of a set of literals where each literal may be in true or negated form, the corresponding circuit element is a MIN gate with seeral inputs and one output. Setting all literals initially to 1 results in the term haing the logic alue 1. As literals change to the binary information leels 0 or 2, the term will respond by changing alue either to 0 or to 2. If the logic expression is composed of the MAX of a collection of such terms, the expression initially has the alue of 1 and will change alue either to 0 or to 2. Hence, based on the gien interpretation of the logic alues and the characteristics of the three elementary logic gates, logic expressions for combinational networks can be generated using standard binary design considerations. Only the logic alues of 0 and 2 need to be considered in the design process. The imposition of the control leel does not require a nonbinary design process. Logic networks incorporating feedback will be considered in a later section of this paper. IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 10, OCTOBER 1980 TABLE I BASIC LOGIC OPERATIONS, CONSTANT FUNCTIONS, AND LOGICAL SYMBOLS x + V X x MAX x NEGATION X X~ X + V X X MIN YV Ot XV V X x C 0 C I C 2 C CONSTANT FUNlCTIONS C=0, OIt C-1, o0 C=2 It should be noted that the assumed network analyzed does not incorporate the constant functions of Table I. Such functions, specifically with C = 1, will be used later in this paper. At this point, we need only point out that the use of a constant function as an input to a MIN gate (MAX gate) merely puts a restraint on the highest (lowest) output alue that can be generated. III. COMBINATIONAL CIRCUIT CONTROL Gien that we hae a combinational circuit that incorporates three leels of signal, one question that must be answered is how can one determine when the circuit has responded to all of its input changes? Recall that initially all input alues are at the 1 leel, as is the circuit output. Hence, an expression that is composed of the MAX of a set of terms in which each term is the MIN of seeral literals can be monitored as follows. Initially, 1) all the network inputs hae the alue 1; 2) all the MIN gate outputs hae the alue 1; 3) the network output MAX gate has the alue 1. When the network inputs assume the data leels of 0 and 2, the circuit has processed all the data if all the following conditions hold: 1) each network input has the alue 0 or 2; 2) each MIN gate output has the alue 0 or 2; 3) the network output MAX gate has the alue 0 or 2. Similar analysis allows us to be able to monitor the circuit as it changes from a data condition, all lines at 0 and 2, to a control condition, all lines at 1. A key aspect of the monitoring process is the nature of the delay that may be present in the network. Our assumption is that within the module line delay is zero but gate delay, although finite, is unbounded. Further, between modules line C

3 WOJCIK AND FANG: THREE-VALUED ASYNCHRONOUS MODULES 891 delay is finite but unbounded. Hence, although the network inputs can arrie at the module at different times, each input, when it arries, is simultaneously present as an input to all of the MIN gates to which it is attached. Since the inputs are monitored as are the outputs of the MIN and MAX gates, we can be sure that each gate has responded appropriately before we assume that either data hae been processed or that the circuit has been set to the control leel. I N pu T s xi X1Xn 0 u T p U T S IV. MODULE STRUCTURE The basic structure of a module is shown in Fig. 1. This general structure indicates that each module is composed of a data processing component, a storage component, and a control component. Each module is capable of transmitting and receiing control information. It is assumed that module input ariables are proided in both true and negated form. This assumption is reasonable in that if we consider a module input ariable to be the output of another module, we will require that each module output is stored in an appropriate memory deice. In this deelopment, we will use a three-alued ersion of a binary flip-flop [6]; see Fig. 2. We hae seen that it is necessary to be able to monitor the inputs to the data processing component of the module in order to determine when it has processed information and when it has attained the all 1 control leel. Further, monitoring is required in order to control the updating of the module's storage, which seres as an input source for other modules. We will not be concerned with the initial data source for the network. A discussion of this topic can be found in Unger [ 11 ]. The input monitoring approach that will be used is a standard technique to differentiate between a data input and a control input. It will be assumed that between each data input to a module, an all 1 "spacer" or control input will occur. If we consider the input lines to the data processing network as forming an input word, the spacer word consists of all 1's while data words consist only of O's and 2's. A word composed of all three alues is neither control nor data. The control portion of the module must be able to recognize the spacer and data words. To accomplish this, specific three-alued logic operators must be incorporated. Let us define a unary operator as follows: ao f(x) = X(a2al1ao) = a,1 a2 if X= 0 if X= 1 if X = 2 where as E 10,1,21. In this form, the identity operator is X(210) = X, while X(012) = X is the strong-negation operator. The logic gate symbols for unary operators are shown in Fig. 3, while Table II describes fie unary operators that will be used as basic components in the control portion of the module. It is essential to recall that the assumed model of asynchronous operation requires that any ariable, or logic gate output, that is to change from 0 to 2 (2 to 0) must pass through the intermediate 1 leel. For example, in the unary operators in Table II, een though output specifications of 0 changing to 2 are listed, an intermediate alue of 1 must occur. The TO/FROM PREDECESSOR MODULES 0 SR Fig. 1. Y - SRi RY + Si Fig Basic module structure Three-alued flip-flop. TO/FROM SUCCESSOR MODULES generation of the 1 alue during a transition between data leels is required to allow the control portion of the module to function properly. In order to update storage within a module, the control section of the module will be proided with information from successor modules concerning their status. A module can be characterized as being in any one of the three status conditions. 1) The module has processed the spacer word and can accept a data word input. 2) The module has processed a data word and is waiting to update its storage. 3) The module has updated its storage and can accept the spacer word. Hence, gien a network of modules, correct operation of the system requires the presence of a'spacer word in at least one module B that is logically between two modules A and C that are processing data words in which A and B are predecessors of B and C, respectiely. The module status information proides the means for synchronizing the flow of data/spacer words within the network. Within each module, the control section uses three primities. 1) D Primitie: This construct is characterized by the logic equation D(X,Y) = X(020). y(o20) + 1. (X(020) + y(o20)) This primitie is shown in Fig. 4. It generates the alue 2 only when both of its inputs are at 1, and it generates the alue 0 only when both inputs are at binary data leels. 2) M Primitie: This basic operator is characterized by the logic equation M(X,Y)=X- Y+ 1 (X+ Y).

4 892 IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 10, OC'TOBER 1980 x _ X(210) X 3 -( ) O Xo(012s Fig. 3. Logic symbols for unary operators. TABLE II BASIC UNARY OPERATIONS X X(002) X(022) X(2201 X1200) X1020). X(220).X(022) X Fig. 4. y X I Fig. 5. ZV Logic table and logic symbol for the D primitie. 2 M1 V(X,V) M(XVY) Logic table and logic symbol for the M primitie. Fig. 5 shows the M primitie. It generates the alue 0 (2) only when both of its inputs are at 0 (2); otherwise it generates the alue 1. The D primitie determines if its pair of inputs are both at the control leel or at binary data leels. The M primitie merges the outputs of D and M primities to proide a single control signal within the module. Fig. 6 illustrates the use of these primities. 3) CONTROLLER Primitie: This complex element [12] receies an input S which describes the status of the data processing component, an input labeled Cs which specifies the status of successor modules, and an input Z which indicates the status of the module storage element. This control component proides two basic functions: to determine when new data is present on the inputs to the module and to determine when storage may be updated with new information from the primary outputs of the data processing component. Table III shows the transition table for the CONTROLLER with blank entries indicating input conditions that can neer occur. Table IV indicates the possible status of each of the input signals, S, C5, Z. The output signal from the CONTROLLER has only two states, 1 and 0, representing to "update" and to "not update" the storage elements with information from the data processing component.- The logic equation of the CONTROLLER can be obtained easily from the transition table, Q = 1 * Z(220). S (002). Cs (200) + 1 * Z(022). S(200). C (002) This equation is the control signal to the storage component, and its logic circuit is gien in Fig. 7. Notice that because of the simple binary output characteristic, the CONTROLLER primitie is free of operation hazards and static/dynamic hazards. A flow diagram which specifies four key states of the CONTROLLER is shown in Fig. 8. At state A, the module has the spacer passed through its data processing component and has updated the storage elements; the status of the successor modules indicate that the successors are waiting for data words. This is a stable state indicating that the module is ready Fig. 6. Use of D and M primities. to receie data words from preious modules. State C is another stable state with data words in the storage elements and ready for the next spacer words. The transition from A to B occurs when the data words from preious modules hae been processed but the storage elements hae not been updated. Similarly, the module changes from C to D when it has processed the spacer words and has data words still in the storage elements. Notice that both states B and D hae two possible next states. Let us discuss this situation in more detail. As was mentioned preiously, at state B, the module has processed the data words from preious modules and is ready to update its storage elements. After the storage elements are updated, the successor modules receie the data words, and the current module is ready to receie the next spacer. If the successor modules respond to the data words faster than the current module processes the next spacer, which means Cs changes to alue 0 before S responds to the next spacer, the transition from B to C occurs. Otherwise, if S changes before Cs reaches its final alue 0, the current module will moe from B to D. A similar situation exists for data words and is specified

5 WOJCIK AND FANG: THREE-VALUED ASYNCHRONOUS MODULES 893 TABLE III TRANSITION TABLE FOR CONTROLLER sc6' Z s i I O~ Q Q2 -Z(220).S(002).CA (200) + 1*2(022)*S1200) C (002) TABLE IV STATUS OF EACH INPUT SIGNAL 0 - Data hae been paocl6ied in the module S 1 - The module a p4oceae6ixg data/apaee't 2 - SpaceJ ha- been p ocea,ed in the modute 0 - SuCeee-6ou aae waiting sotl 6paceJ C: 1 - Succe^ouo ale puocea4ing data/h pacee 2 - Succeh4Aou axe waiung jo4 data 0 - Data ate in 6toage etemens Z: 1 - Updating.6toAa8e etement6 2 - SpaceA a'e zn htouzqe etementa by the two possible transitions from either D to A or D to B. The transition table describes all the possible behaior sequences of the modules that can occur. The storage element contains a monitoring circuit together with a three-alued flip-flop. For eery storage element, there are two input signals labeledf and Q wheref is the data signal from the primary output of the data processing component and Q is the control signal from the CONTROLLER. All the storage elements in the module remain unchanged until the CON- TROLLER sends the update signal (Q = 1) to the storage component. The state table of the storage element is shown in Table V which indicates that the control signal Q determines whether or not the information fromf will be stored. It should be noted that blank entries in Table V are conditions that cannot occur because the primary inputs alternately carry data and spacer signals. A hazard-free excitation table is gien in Table VI and is characterized by the logic equations S = Q(220).f R = Q(220).7I The logic diagram of the storage element is shown in Fig. 9. The monitoring circuit of the storage element can be proided as part of the flip-flop module so that the logic designers need only be concerned with the input/output behaior of the storage elements. The assumption of unbounded gate delay results in the possibility of delay hazards [2]. Howeer, the monitoring circuit of the storage element is free of any delay hazards because no two gates can be excited at the same time. The flip-flop used does not hae this characteristic [12]. Howeer, it is reasonable to assume that the flip-flop does not hae unbounded gate delay. Fig. 10 shows the general structure of an entire module, illustrating the use of the D, M, and CONTROLLER primities. It illustrates two outputs from the data processing component z Q- I-z220). S(002).C (200), 1.Z1022).s(200).C (002) Fig. 7. Data pjtoceaed B Spaces A4ti&age SucceAhost waiting data Fig. 8. Logic diagram for CONTROLLER primitie. zsc4 000 c Data ptoee*hed Data in StoAaqe SueeAeot kkzt ApaceA Flow diagram for CONTROLLER. SpacetA ptoce4aed Spaces in AtoLaOe SucceAhost waiting data 020) Spacet pjocea6ed Data in 06to0age SucceAo4t waitng 6pacet and the monitoring of the two storage elements by one CON- TROLLER. The use of the D and M primities are also shown in the figure to determine signal leels of a pair of inputs. Notice that the Cs signal is formed within the module by the M primities to handle seeral successor modules. The formation of the module status control signal Cp to its predecessor modules is also shown. As a final point, it should be apparent that the D and M primities were described as functions of two inputs only to simplify the presentation and to emphasize the functions that were to be performed by the primities. Both primities can be expanded to handle larger numbers of inputs. Howeer, the CONTROLLER is designed to require only three inputs regardless of how complex the module is. More importantly, only one CONTROLLER is needed in each module to synchronize the moement of the data/spacer words to an arbitrary number of storage elements in the module. V. SEQUENTIAL CIRCUITS Let us now consider data processing networks within a module which are sequential circuits that incorporate memory elements. As has been shown, the design of combinational data processing networks and the use of the control primities in a module are tasks that really do not require the logic designer to use nonbinary logic design procedures. Combinational network design is, in effect, a binary design process; and the use of the control primities requires an understanding of the logical functions that they perform and not detailed knowledge

6 894 IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 10, OCTOBER 1980 TABLE V STATE TABLE FOR STORAGE ELEMENT Qs Y 00 0X I _ of the logic design of the primities themseles. Although research has been done on the design of nonbinary asynchronous sequential circuits [6], [8], the techniques are truly "multialued" and require the designer to master new and complex design procedures. The approach that is shown in this paper employs a method for designing three-alued sequential circuits using binary asynchronous logic design techniques. Fig. 11 shows the standard description of a sequential data processing network in which the memory elements and feedback loops are separated from the combinational part of the circuit. In the modules that hae been preiously described, the primary inputs alternately carry data and spacer signals. Consequently, in a sequential circuit, the memory elements must retain data alues during the time that the primary inputs are carrying the spacer signal. When the primary inputs attain a new data state, the network's primary and secondary outputs will be functions of the new primary input data and the data alues that had been stored in the memory elements during the immediately preceeding primary input spacer. There are seeral problems with sequential circuits in the three-alued module. 1) If the three-alued flip-flop is used as the memory element, what state assignment technique can be used? 2) Assuming that a three-alued flip-flop is used, and since the spacer word of all l's occurs between data word inputs, how can we preent the occurrence of the logic 1 signal on the flip-flop inputs from forcing the deice to change to the logic 1 state, destroying the data alue that it was to retain (see Fig. 2)? 3) How can it be determined that the flip-flops hae processed a data (spacer) input so that the module can request a spacer (data) input? 4) How can the behaior of the memory elements be monitored so that the CONTROLLER operates correctly? VI. DESIGN OF SEQUENTIAL CIRCUITS To sole the state assignment problem, the binary, restricted single transition time (restricted STT) assignment will be used [2], [1 1]. This scheme allows seeral secondary ariables to change simultaneously during a state transition without causing critical races. An additional important feature of this approach proides that all unstable states which lead to the same stable state in any column of the flow table, and in the corresponding state table itself, hae a subset of secondary ariables in common which distinguishes these states from other such sets of states in the column. Hence, both the primary and secondary outputs of the sequential circuit are uniquely 6 TABLE VI HAZARD-FREE EXCITATION TABLE Q6 V Fig. 9. SR s - Q(220).6 Rd Q(220).fo e Logic diagram for storage element. determined by the primary input ariables and only those secondary ariables which remain fixed during a state transition. These secondary ariables are the ones that the state and all the unstable states leading to this stable state hae in common. Since a binary state assignment is to be used for a threealued sequential circuit, it is necessary to describe how the assignment technique is used in a nonbinary enironment. Fig. 12 shows how the three-alued flip-flops will be used in the sequential circuit. Note that Si and Ri excitation functions for the flip-flops are combinational functions of the primary and secondary ariables. Further, each Si and R, function output is used as the input to a unary function, whose output is then connected to the corresponding Si or Ri input of the flip-flop. These unary functions filter out the control leel 1 signals that are generated by the combinational logic during a spacer input. When 1's are present on the Si and Ri outputs of the combinational logic, O's will be present on the corresponding inputs of the flip-flops allowing the memory elements to retain a binary data alue. To design the sequential circuit, only the binary alues 0 and 2 attained by the primary and secondary inputs need to be considered. Hence, the three-alued flip-flops behae as binary flip-flops with respect to these two logic alues. The following design rules are followed. 1) In forming an excitation table for the Si and Ri excitation alues: a) if in column j and row r of the transition table Yi = 0 (2) and Yi = 0 (2), set SiRi = 02 (20); b) if in column j and row r of the transition table Yi = 0 (2) and Yi = 2 (0), set SiRi = 20 (02); 2) In forming the algebraic equations for the Si and R1 excitation functions and the primary output functions: a) If Ii and Ij are two adjacent primary input ectors, no term in any of the equations can be formed that assumes the alue 2, in a sum-of-products form for the function (0, in a product-of-sums form for the function), for both of the inputs Is and Ij;,y.

7 WOJCIK AND FANG: THREE-VALUED ASYNCHRONOUS MODULES 895 XI x1 X2 Fig. 10. Monitoring and control of a combinational data processing module. PRIMARY INPUTS (PRIMARY VARITABLES) XI X2 COMBINATIONAL I I--4t -*-PIMR LOGIC LOGIC *~ n PRiMARY arrdiferrc.i=f X ul ruiz T --o- I SECONDARY INPUTS (SECONDARY VARIABLES) -YI Yp jiyp SECONDARY OlUTPUTS Fig. 11. MEMORY ELEMENTS Structure of sequential data processing network. b) the design must ensure that each equation attains the alue 1 at the spacer input. Let us consider the ramifications of these design rules. We first note that rule 1 assures that each secondary ariable will be "excited," either Si = 2 or Ri = 2, for each data alue attained by the primary inputs regardless of whether or not the secondary ariable is to change its binary data alue. Howeer, since the excitation SiRi = 22 is prohibited, the process of determining when the circuit has responded to a data alue is simplified since there cannot be any races or delay hazard problems. Further, the second design rule assures that all the Fig ~~~~~~~~~~~~~~~~~~~~~~~~~~~ F1 I2 U VI RI Use of three-alued flip-flop in sequential circuit. functions attain the control signal alue at the spacer, facilitating the monitoring and control of the sequential circuit. Finally, the second rule also guarantees that the primary and secondary outputs are neer solely dependent on only the secondary ariables, and that the excitation and output functions hae only one term in them that can attain the alue 2(0) at a data input. These latter considerations further simplify the circuit monitoring and control process.

8 896 TABLE VII a) FLOW TABLE. b) TRANSITION TABLE. c) EXCITATION TABLE. PS I1 i2 13 (Do0 2 0 (DJ,2 4,2 (0),0 3,o I,0 2, (),0 GQ2 G),2,2 NS, Z I' Y2Y3 YIY2Y3 VY V2V3, Z x1x SIRI,S2R2,S3R3 cl x1x ,0 202,0 000, ,2 202,0 002, ,0 202,0 002, ,2 220,2 000, ,02,20 02,02,02 02,02, ,02,20 02,02,02 02,02, ,02,20 20,20,02 02,02, ,20,02 20,20,02 02,02,02 b) IEEE TRANSACTIONS ON COMPUTERS, VOL. C-29, NO. 10, OCTOBER 1980 TABLE VIII MAPPING FOR PRIMARY OUTPUT FUNCTION OF TABLE VII 'iy2y3 A1A _ Y2X1X2Y2X1X2 3X1 2 ' (V2+X1+X2) (VYI+X1+X2) ( Y34j1) 9 ' M(91 92) ' (91+92) 9 TABLE IX DERIVATION OF FLIP-FLOP EXCITATION EQUATIONS x x2 x x2 x x X1X2 X1X2 X1X V1Y23 * [i 2 [11O lo 0 0 The second rule imposes certain restrictions on the algebraic forms of the equations. We will employ the Karnaugh map concept to illustrate this rule, assuming that the columns of the map correspond to the primary inputs and the rows to the secondary inputs. Part a) of the second rule implies two things: first, that no loop on the map can contain cells from eery column, and second, that minimization is confined to single columns or to a group of columns consisting of one data input and one or more "don't care" data inputs-unused data input combinations. In this regard, Part b) prohibits a loop that is independent of the primary inputs. The reason for this is that since the secondary ariables will only hae the alues 0 or 2 when the sequential circuit is in a stable condition, a term consisting only of secondary ariables might remain at the alue 2 during the input spacer, preenting the equation from attaining the control leel 1 signal. It can be shown that the requirements of design rule 2b) can always be satisfied [131. To illustrate the sequential circuit design process, the flow table shown in Table VII(a) will be used. Table VII(b) shows the excitation table formed by using a restricted STT state assignment. Finally, Table VII(c) shows the excitation table formed by using the sequential design rules. The mapping of the primary output function is shown in Table VIII. This function, fully described in [13], requires a special logic equation implementation, as shown in Table VIII, in order to satisfy design rule 2b). Table IX describes the deriation of the flip-flop excitation equations. Intermediate transition alues hae been entered into the maps to ensure that they l l LL...i _a SI S1 ' XIX2 + V1X2 R1 X 1x1x2 a S2 ' XI(VI + X 2) 1 (2 + XI+ X2) x1x2 x x2 x1x2 V,Y2Y3 1o o0 - T i2A ] jl _o R2 S3 R3 R2 ' + YIX1X2 + Y2X1X2 S3 a (X I+X2)HY3+1)(Y2+X1+X2) b R3 XJX2 Y3X1 V2X. X2 S2

9 WOJCIK AND FANG: THREE-VALUED ASYNCHRONOUS MODULES 897 TO SECONDARY INPIJTS se RE TO S INJP( OF CONTOLLER Fig. 13. V Logic circuit and symbol for three-alued flip-flop used as a memory element. represent single output change (SOC) [11] functions. The mappings shown in Table IX result in the static, dynamic, and operation hazard-free functions that are shown. For simplification purposes, it can be obsered that if the 0 entries for function SI are mapped instead of the 2 entries, then we obtain the result that Ji = K1, J2 = K2, J3 = K3. VII. SEQUENTIAL CIRCUIT CONTROL It has been pointed out that the secondary inputs to the combinational part of the data processing network only take on the logic alues of 0 and 2 when the circuit is in a stable condition. Hence, when the spacer input arries at the module ia the primary inputs, these secondary inputs cannot be monitored by the D primities to determine if they hae responded to the spacer input. Hence, control of the module requires us to augment the basic flip-flop configuration as is shown originally in Fig. 12. Fig. 13 illustrates the logic circuit configuration and the logic symbol for the flip-flop as it will be used as a memory element in sequential circuits. SE and RE represent the flipflop excitation equations that are deried using the sequential design rules, while SA and RA refer to the actual excitation inputs of the flip-flop. The figure indicates that the monitoring circuitry should be proided as part of the flip-flop module so that the logic designer need only be concerned with the input/output behaior of the mernory module. The output of the M control primitie is used as an input to the CON- TROLLER. Now we can consider the monitoring and control of the entire sequential data processing module. The general structure is depicted in Fig. 14. This structure is similar to the Cp ~ p Fig. 14. FROM SUCCESSORS Monitoring and control of a sequential data processing module. monitoring and control structure described for combinational modules (Fig. 10). Howeer, there are two noteworthy differences. 1) The primary inputs to the sequential module are monitored, as before, by D primities. The secondary inputs are not monitored in this manner since they neer are stable at the logic alue 1. The Q output of the flip-flop module is used to monitor these inputs. (Recall that line delay within the sequential module is assumed to be zero so that changes in the secondary ariables reflected in the Q outputs affect the combinational logic at the same time.) 2) The functionsf, SE, and RE are designed using the sequential design rules. The indiidual terms comprising these functions are not monitored by D primities as in the combinational modules. The terms are not monitored because although each of these functions must attain the alue 1 at the spacer, there is no assurance that each term in an equation must attain the alue 1. Howeer, the monitoring process will still operate correctly. Finally, it can be shown [13], that een though the primary inputs and the excitation functions of the sequential module are subject to certain potentially disruptie delays, the monitoring and control structure will not malfunction. Proiding that the sequential design rules are used, networks composed of the interconnection of sequential (and combinational) modules will operate correctly under the assumed delay restrictions. VIII. SUMMARY This paper has described the feasibility of designing threealued asynchronous modules using essentially standard binary design techniques. Although a number of three-alued com-

10 898 IEEE TRANSACTIONS ON COMPUTERS, VOL. c-29, NO. ponents are also used in the modules (the control primities and the flip-flop module), these components are used to implement the monitoring and control structure and not to design the logic functions that are implemented in the data processing network within each module. It is important to note that this deelopment was based on the goal of implementing speed-independent asynchronous circuits using binary design procedures. Only three-alued systems were considered. The potential for further research into the design of modular multialued systems is irtually unlimited. Such systems should proe to be an important area for the use of multialued logic. REFERENCES [1] D. E. Muller, "Asynchronous logics and application to information processing," in Proc. Symp. Application of Switching Theory in Space Technol., Aiken and Main, Eds. Stanford, CA: Stanford Uni. Press, 1963, pp [2] D. B. Armstrong, A. D. Friedman, and P. R. Menon, "Design of asynchronous circuits assuming unbounded gate delays," IEEE Trans. Comput., ol. C-1 8, pp , Dec [3] B. Elspas et al., "Inestigation of propagation-limited computer networks," Final Reps.-Phases 1, II, III, Stanford Res. Inst., Apr. 1964, July 1965, June [41 R. M. Keller, "Towards a theory of uniersal speed-independent modules," IEEE Trans. Comput., ol. C-23, pp , Jan [5] A. S. Wojcik, "Multi-alued asynchronous circuits," in Proc Int. Symp. Multiple-Valued Logic, Uni. Toronto, May [6], "Multi-alued asynchronous sequential circuits," in Proc Int. Symp. Multiple- Valued Logic, West Virginia Uni., May [7] -, "Multialued asynchronous sequential modules," in Proc. 14th Annu. Allerton Conf. Circuit Syst. Theory, Sept [8] S. J. Sheafor, "The design of multiple-alued asynchronous sequential circuits," Coordinated Sci. Lab., Uni. Illinois, Urbana-Champaign, Rep. R-63, Sept [91 A. S. Wojcik, "On the design of three-alued asynchronous modules," in Proc. 7th Int. Symp. Multiple- Valued Logic, Uni. North Carolina, Charlotte, May [10] A. S. Wojcik and G. Metze, "An analysis of some relationships between Post and Boolean algebras," J. Ass. Comput. Mach., ol. 21, pp , Oct [11] S. H. Unger, Asynchronous Sequential Switching Circuits. New York: Wiley-Interscience, , OCTOBER 1980 [12] K. Y. Fang, "A control priihitie for three-alued asynchronous circuits," Dept. Comput. Sci., Illinois Instit. of Technol., Rep. 79-4, June [13] A. S. Wojcik, "The design of multialued asynchronous modules," Dep. Comput. Sci., Illinois Inst. Technol., Rep. 76-1, No ff Anthony S. Wojcik (S'67-M'7 1) receied the B.S. and M.S. degrees in mathematics and the Ph.D. degree in computer science from the Uniersity of Illinois, Urbana, in 1967, 1968, and 1971, respeche is currently an Associate Professor of Com- puter Science and Chairman of the Department of Computer Science at the Illinois Institute of Tech- nology, Chicago. His research interests include the design of and application of multiple-alued logic systems, switching theory, and computer architecture. He was General Chairman of the 8th International Symposium on Multiple-Valued Logic in 1978, Technical Program Chairman of the 10th Symposium in 1980, and is presently an Assistant Program Chairman for the NCC. He has also sered as Midwestern Area Chairman for the IEEE Computer Society. Dr. Wojcik is a member of Sigma Xi and the Association for Computing Machinery. Kwang-Ya Fang (S'75-M'76) was born in Taiwan, Republic-of China, on September 27, He receied the B.S. degree in electronic engineering in 1971 from the Chung-Yuan Christian College, Taiwan, and the M.S. degree in computer science from the Illinois Institute of Technology, Chcgo, in From 1976 to 1979, he was a System Analyst at the Harey Technical Center, Atlantic Richfield Company, Harey, IL. He is currently an Information System Staff member at the Switching Software Center, Western Electric Company, Lisle, IL. He is also a part-time student at the Department of Computer Science, Illinois Institute of Technology. His research interests are in the areas of multiple-alued logic and switching theory. Mr. Fang is a member of the Association for Computing Machinery.