CHW 261: Logic Design
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1 CHW 26: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby Slide
2 Digital Fundamentals CHAPTER 7 Latches, Flip-Flops and Timers Slide 2
3 Latches S-R (Set-Reset) latch Gated S-R latch Gated D latch Slide 3
4 Latches Latches A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory. The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates. With NOR gates, the latch responds to active-high inputs. With NAND gates, the latch responds to active-low inputs. R S S NOR Active-HIGH Latch R NAND Active-LOW Latch Slide 4
5 Active-HIGH S-R Latch Latches The active-high S-R latch is in a stable (latched) condition when both inputs are LOW. Assume the latch is initially RESET ( = 0) and the inputs are at their inactive level (0). To SET the latch ( = ), a momentary HIGH signal is applied to the S input while the R remains LOW. To RESET the latch ( = 0), a momentary HIGH signal is applied to the R input while the S remains LOW. Never apply an active set and reset at the same time (invalid). Slide 5 0 R 0 0 S R S Latch initially RESET Latch initially SET
6 Active-HIGH S-R Latch Latches Slide 6
7 Latches Active-LOW S-R Latch The active-low S-R latch is in a stable (latched) condition when both inputs are HIGH. Assume the latch is initially RESET ( = 0) and the inputs are at their inactive level (). To SET the latch ( = ), a momentary LOW signal is applied to the S input while the R remains HIGH. To RESET the latch a momentary LOW is applied to the R input while S is HIGH. Never apply an active set and reset at the same time (invalid). 0 S 0 0 R S R Latch initially RESET Latch initially SET Slide 7
8 Active-LOW S-R Latch Latches Slide 8
9 Latches Latches The active-low S-R latch is available as the 74LS279A IC. S-R latches are frequently used for switch debounce circuits as shown: (2) (3) () (6) (5) S S2 R 2S 2R (4) (7) 2 V CC () (2) (0) 3S 3S2 3R (9) 3 2 S R S R Position to 2 Position 2 to (5) (4) 4S 4R 74LS279A (3) 4 Slide 9
10 Latches Latches A gated latch is a variation on the basic latch. The gated latch has an additional input, called enable (EN) that must be HIGH in order for the latch to respond to the S and R inputs. S EN R 0 Show the output with relation to the input signals. Assume starts LOW. Keep in mind that S and R are only active when EN is HIGH. S R EN Slide 0
11 Latches Latches The D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown: D D EN EN A simple rule for the D latch is: follows D when the Enable is active. Slide
12 Latches Latches The truth table for the D latch summarizes its operation. If EN is LOW, then there is no change in the output and it is latched. D 0 X Inputs EN 0 Outputs Comments RESET SET No change Slide 2
13 Latches Latches Determine the output for the D latch, given the inputs shown. D EN Notice that the Enable is not active during these times, so the output is latched. Slide 3
14 Edge-Triggered Flip-Flops Edge-triggered D flip-flop Edge-triggered J-K flip-flop Slide 4
15 Flip-flops Edge-Triggered Flip-Flops A flip-flop differs from a latch in the manner it changes states. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered. The active edge can be positive or negative. D D C C Dynamic input indicator (a) Positive edge-triggered (b) Negative edge-triggered Slide 5
16 Edge-Triggered Flip-Flops Flip-flops The truth table for a positive-edge triggered D flip-flop shows an up arrow to remind you that it is sensitive to its D input only on the rising edge of the clock; otherwise it is latched. The truth table for a negative-edge triggered D flip-flop is identical except for the direction of the arrow. Inputs Outputs Inputs Outputs D CLK Comments D CLK Comments 0 SET 0 0 RESET 0 SET 0 0 RESET (a) Positive-edge triggered (b) Negative-edge triggered Slide 6
17 Edge-triggered D flip-flop Edge-Triggered Flip-Flops Slide 7
18 Edge-Triggered Flip-Flops Flip-flops The J-K flip-flop is more versatile than the D flip flop. In addition to the clock input, it has two inputs, labeled J and K. When both J and K =, the output changes states (toggles) on the active clock edge (in this case, the rising edge). Inputs Outputs J K CLK Comments No change 0 0 RESET 0 0 SET Toggle 0 0 Slide 8
19 Edge-Triggered Flip-Flops Edge-triggered J-K flip-flop J Determine the output for the J-K flip-flop, given the inputs shown. CLK Notice that the outputs change on the leading edge of the clock. K Set Toggle Set Latch CLK J K Slide 9
20 Flip-flops Edge-Triggered Flip-Flops A D-flip-flop does not have a toggle mode like the J-K flipflop, but you can hardwire a toggle mode by connecting back to D as shown. This is useful in some counters as you will see in Chapter 8. For example, if is LOW, is HIGH and the flip-flop will toggle on the next clock edge. Because the flip-flop only changes on the active edge, the output will only change once for each clock pulse. D Inputs CLK Outputs Comments 0 SET 0 0 RESET CLK Inputs D CLK Outputs D Dflip-flop CLK hardwired for a toggle mode 0 SET Comments 0 0 RESET Slide 20
21 Flip-flop Applications Edge-Triggered Flip-Flops Principal flip-flop applications are for temporary data storage, as frequency dividers, and in Counters (which are covered in detail in Chapter 8). Slide 2
22 Flip-flop Applications Edge-Triggered Flip-Flops Typically, for data storage applications, a group of flip-flops are connected to parallel data lines and clocked together. Data is stored until the next clock pulse. Slide 22
23 Flip-flop Applications Edge-Triggered Flip-Flops For frequency division, it is simple to use a flip-flop in the toggle mode or to chain a series of toggle flip flops to continue to divide by two. HIGH HIGH One flip-flop will divide f in by 2, two flip-flops will divide f in by 4 (and so on). A side benefit of frequency division is that the output has an exact 50% duty cycle. f in f in J A CLK K J B CLK K f out Waveforms: f out Slide 23
24 Multivibrator Monostable (One-Shot) Astable. Slide 24
25 Multivibrator Monostable The monostable or one-shot multivibrator is a device with only one stable state. When triggered, it goes to its unstable state for a predetermined length of time, then returns to its stable state. +V For most one-shots, the length of time in the unstable state (t W ) is determined by an external RC circuit. R EXT Trigger C EXT CX RX/CX Slide 25
26 Multivibrator Astable An astable multivibrator is a device that has no stable states; it changes back and forth (oscillates) between two unstable states without any external triggering. The resulting output is typically a square wave that is used as a clock signal in many types of sequential logic circuits. Slide 26
27 Multivibrator The 555 timer The 555 timer can be configured in various ways. A basic monostable is shown. The pulse width is determined by R C and is approximately t W =.R C. +V CC (4) (8) R (7) RESET DISCH V CC The trigger is a negative-going pulse. (6) (2) C THRES () OUT TRIG CONT GND (3) (5) t W =.R C Slide 27
28 The 555 timer Multivibrator The 555 can be configured as a basic astable multivibrator with the circuit shown. In this circuit C charges through R and R 2 and discharges through only R 2. The output frequency is given by: f.44 R R C R 2 2 (7) R 2 C (6) (2) RESET DISCH THRES +V CC (4) (8) TRIG CONT GND () V CC OUT (3) (5) Slide 28
29 C (mf) The 555 timer Multivibrator Given the components, you can read the frequency from the chart. Alternatively, you can use the chart to pick components for a desired frequency. 00 +V CC MW MW 00 kw 0 kw kw R (7) RESET DISCH (4) (8) V CC 0. R 2 (6) THRES OUT (3) k 0k 00k C (2) TRIG CONT GND () (5) f (Hz) Slide 29
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