Novel Power Supply Independent Ring Oscillator

Transcription

1 Novel Power Supply Independen Ring Oscillaor MOHAMMAD HASSAN MONTASERI, HOSSEIN MIAR NAIMI ECE Deparmen Babol Universiy of Technology Shariay S, Babol, Mazandaran IRAN Absrac: - A novel power supply independen archiecure is proposed for ring oscillaors. The proposed archiecure explois he advanages of he sae- of- ars like isolaion and self-biasing echniques. In he proposed archiecure he sages of oscillaor are no he same and each sage is designed o implemen one of he above echniques. Many experimens were performed o evaluae he proposed archiecure and compare i o he las compeiive archiecures. The proposed archiecure was simulaed in 0.5µm CMOS echnology where he power supply were changed from 4V o 6V resuling in only 1% deviaion in frequency in he wors case; a record beer han all previous archiecures. Key-Words: - Volage Conrolled Ring Oscillaor, Power Supply Variaion, Frequency Sabiliy. 1 Inroducion A Volage conrolled ring oscillaor (VCO) is one of he mos imporan basic building blocks in analog and digial circuis [1-4]. There are many differen implemenaions of VCOs. The main reason of ring oscillaor populariy is a direc consequence of is easy inegraion. Due o his, ring oscillaors have become inegral par of many digial and communicaion sysems [1]. These building blocks are used in applicaions such as disk drive channels [], clock recovery circuis for serial daa communicaions [3], on-chip clock disribuion [4]. The performance of he menioned sysems highly depends on he robusness of he oscillaion frequency [5]. So he oscillaion frequency should no be sensiive o variaion of power supply and emperaure; a problem ha oscillaors naurally suffer from. I has been shown ha he oscillaion frequency of simple CMOS inverers is varying in direc proporion o supply variaions [6, 7]. These all show he necessiy for designing new robus archiecures. To his end several works have been performed on making oscillaors more robus agains variaions of power supply. To increase frequency sabiliy of simple ring oscillaor, Jovanović and Sojčev have proposed o use a combinaion of he simple inverer and curren sarved delay cell. The repored resuls show 4.% variaion of oscillaion frequency [6]. Maneais has used he concep of self-biasing in combinaion wih negaive feedback wih a 3% variaion of oscillaion frequency [8]. Lee and Kim proposed high speed delay cells and deduce ha his decreases he oscillaion frequency dependency upon power supply. They repored a 6% variaion in oscillaion frequency [9]. However, high performance sysems need more robus oscillaors han proposed above menioned [5]. In his paper, combining he previous echniques, we ry o reach more robus oscillaors. In he proposed archiecure in some sages only one of he menioned echniques is implemened and in some oher anoher, so delay sages of he proposed archiecure are no he same. The res of he paper is organised as follows. In secion a brief descripion of ring oscillaors is given. Aferwards, some MOS VCO implemenaions are reviewed. The proposed archiecure is presened in secion 3. In secion 4, performances of differen srucures are compared. Finally conclusions and some offers are given in secion 5. CMOS Ring VCO and Supply Independen Archiecures; A Brief Review A ring oscillaor is composed of a number of delay sages, wih he oupu of he las sage fed back o he inpu of he firs. To achieve oscillaion, he ring mus provide a phase shif of π and have uniy volage gain a he oscillaion frequency. Each delay sage mus provide a phase shif of π/n, where N is he number of delay sages. The remaining π phase shif is provided by a dc inversion [6]. This means ha for an oscillaor wih single-ended delay sages, an odd number of sages are necessary for he dc inversion. If differenial delay sages are used, he ISSN: ISBN:

2 ring can have an even number of sages if he feedback lines are swapped. Examples of hese wo circuis are shown in fig.1. Fig.1 Single- and differenial-ended ring oscillaors There are several ypes of inverer sages by which a ring oscillaor can be realized [10]. Some of he mos widely used srucures are Simple CMOS inverer, Curren Sarved delay cell, Maneais cell, and Lee-Kim cell. In he following subsecions hese fundamenal srucures will be briefly explained. Please, leave wo blank lines beween successive secions as here. Mahemaical Equaions mus be numbered as follows: (1), (),, (99) and no (1.1), (1.),, (.1), (.), depending on your various Secions..1 Simple CMOS Inverer The firs pracical opology used as RO is CMOS inverer. Is schemaic is drawn in fig.aa and is frequency vs. power supply is shown in fig.. Since i direcly is coupled wih power supply, oscillaion frequency deviaes in direc proporion o he variaions of power supply volage [6, 7]. deviaions as easily as possible, he device is approximaely assumed o be in sauraion region while discharging, hough i is no correc in general. Therefore In( ) = kn( Vin Vn) () The key simplificaion o solve he above equaion is uni sep funcion i.e., V in = U(). To work ou he propagaion delay, an ideal square wave is supposed o simulae he inpu. Due o capaciive characerisic of he oupu node, i akes some ime for his node o reach he bounds. Fig.3 shows he inpu and oupu waveforms. As menioned in fig. above, he delay ime is composed of wo oher delay imes, phl and plh, each of which is due o one of he MOS ransisors. When he inpu swiches o high he oupu ravels from he high level o low level. This means he NMOS device is on, where PMOS device is off. This means phl depends on he characerisics of he n-channel device. On he oher hand, when he inpu swiches from high o low, he oupu sars o increase from he low level o high level. This means ha, plh is dependen upon p-channel device characerisics. Fig.3 inpu and pu waveforms of simple CMOS inverer Wih he above informaion, i seems logical o separae he circui for each par of delay ime. Hence, o calculae he phl, he following circui will help. Fig. Simple CMOS inverer Having a glance a propagaion delay of his delay cell will give furher informaion for laer comparison. Alhough propagaion delay is compued in differen manner, we have jus considered one par of a whole. To sar wih, le us assume ha he circui oupu is in he ransien from high o low. I is obvious ha he n-channel device is on while p-channel one is off. Wriing KCL for he oupu node yields: dvou CL + In( ) = 0 (1) d where C L can boh be effecive parasiic and/or exernal capaciance. Subscrip n refers o n- channel device. Since i helps o gain an insigh ino he effec of power supply variaions on frequency Fig.4 o calculae he phl his par of he circui is required o be analysed. Now i is sufficien o solve he oupu differenial equaion for he sauraion region. C V dv DD o C V n p = = (3) HL k V DD Vn n ( VDD Vn) kn ( VDD Vn) 1 W kn = μ n Cox (4) L By he same oken, charging C L is done hrough p- channel device. Then ISSN: ISBN:

3 p C V L p =. (5) k ( V V ) p DD According o he menion erminologies, oscillaion frequency is 1 fosc = (6) d p + n d = (7) As seen from (3) and (5) one implies ha power supply effecs delay ime direcly. i.e., any change in power supply volage will affec he propagaion delay and, in urn, oscillaion frequency is affeced. Below is skeched oscillaion frequency vs. power supply for simple inverer based ring oscillaor. As is apparen sensiiviy of oupu frequency wih respec o power supply variaions is which is considerably high. This value has he meaning of a 6.81 percen deviaion of frequency in case of 10 percen of power supply variaion. Simulaions showed ha in case of device scaling, sensiiviy may change slighly. Bu variaions were small enough o be ignored. Fig.5 frequency deviaions vs. power supply deviaions for CMOS inverer p supply. In fac hese ransisors operae as sink and source currens, respecively, for he inverer sage. For push pull ype elemens such as inverers, he delay can be changed by changing he rae a which he oupu capaciance, C L, is charged. Adjusing sink curren one can vary he delay. The capacior C L is charged during he rising and is discharged during he falling edge of he pulse generaed a he oupu of he menioned sage. Conrol volages V BP and V BN define currens of ransisors M 3 and M 4, respecively. Fig.6 curren sarved delay cell As for simple CMOS inverer i is worhy o menion delay ime; i gives a good insigh. Following he same rule as before, we have: C VDD dv o C Vn n = V V k n ( VDD Vn ) = (8) DD n kn ( VBN Vn ) And C Vp p = (9) k V V ) p ( BP p Now from (8) wih (9) one deduces ha curren sarved delay cell wih oupu swich is less sensiive o power supply compared o simple inverer. Fig.7 shows he frequency vs. power supply variaions for a sarved delay cell.. Curren Sarved Delay Cell Shown in fig.6 is one of he mos ineresing delay sages for supply independen ROs called Curren Sarved delay cell. In his ype, he curren of oupu capacior is limied by a bias circui. As can be seen from figure 6, he volage conrolled delay elemen is implemened as a one-sage inverer. MOSFETs M 1 and M are consiuens of he invering propery, while ransisors M 3 and M 4 form he bias circui which is independen of power fig.7 frequency deviaion in erms of power supply variaions for ISSN: ISBN:

4 curren sarved cell I is shown ha in ROs based on sarved delay cell, he sensiiviy of oupu frequency wih respec o power supply variaions is Compared o he simple CMOS inverer, an improvemen has been achieved using curren sarved cell. I can be implied ha if power supply varies by 10 percen, he frequency deviaion would be as much as 3.95 percen of is nominal value. Simulaions showed ha in case of device scaling, sensiiviy may change slighly. Bu variaions were small enough o be ignored..3 Maneais Cell Maneais proposed o use differenial Ring wih symmerical load like he one shown in fig.8. Using symmerical load wih replica feedback biasing, decreases he sensiiviy of he oscillaor o supply and subsrae noise [6, kojo]. Apar from being compleely symmeric, Maneais used self-biasing concep. This way isolaion from power supply and any oher deviaions from desired frequency make he circui back o he quiescen frequency. This is achieved hrough a combinaion of hree bias circuis; a volage reference, a curren reference, and he replica bias. These building blocks are described in more deail in references [109], [111] and [113]. Fig.8 Maneais delay cell The replica bias circui and volage reference also ensure a swing which is relaively independen of process variaions, anoher imporan consideraion. Fig.9 Volage reference generaor The volage reference develops a ΔV BE mismach across a fixed resisance o generae a PTAT curren. This curren is hen drawn hrough anoher resisor aached o he supply o give a reference volage of KT R Vref = VDD.ln( X ). (10) q R1 where X is he raio of he PNP device sizes. This reference volage is used in he replica bias circui o se he nominal DC oupu swing. The swing is herefore proporional o absolue emperaure and is insensiive o he power supply variaions. I depends on a raio of resisances, which mach reasonably well over process variaions, and o a raio of device areas. KT R V SW =.ln( X ). (11) q R1 The curren reference uses a feedback loop mach ΔV be a mismach in pair of bipolar devices o a Δ(V GS V h ) mismach in a pair of MOS devices. The end resul is a curren ha depends on he hermal volage kt/q, device sizes, and device mobiliy. This curren is supply independen, so he ime delay per sage is independen of supply volage, o firs order, as well. There are some second order effecs, such as he variaion in some of he load capaciance parasiics wih supply volage, bu he ne effec is a circui which is resilien o variaions in supply and emperaure. The replica bias circui and volage reference also insure a swing which is relaively independen of process variaions, anoher imporan consideraion. ISSN: ISBN:

5 fig.10 Replica bias circui Shown below is he frequency deviaion of maneais cell in erms of power supply deviaions. To our surprise, his mehod proposes a sensiiviy of almos nearly A 10 percen power supply variaion leads o a -3 percen frequency variaion. fig.1 Lee-Kim cell This srucure shows a sensiiviy of nearly 0.6, expressing 6 percen ou of nominal working condiions wih respec o 10 percen of power supply variaion. Fig.1 visualises wha was menioned above. fig.11 frequency deviaions vs. power supply variaions for he case of Maneais cell.3 Lee-Kim Cell Lee-Kim Cell is he same as Maneais, excep for ha a posiive feedback has been applied o improve he oupu swing. Fig.aa shows he Lee-Kim cell. The basic delay cell consiss of six ransisors. The cross-coupled PMOS ransisors, M3 and M4, guaranee he differenial operaion of he delay cell wihou a ail-curren bias. Auxiliary PMOS ransisors, M5 and M6, conrol he oscillaion frequency. 3 The Proposed supply independen Volage Conrolled Ring Oscillaor In previous secion, i was shown ha how supply deviaions affec he performance of each sysem. CMOS inverer sages suffer mosly due o direc coupling o supply. (3) emphasises his. I shows ha frequency changes in direc proporion o power supply. Due o his, as an isolaion mechanism, in Fig. 6, one ransisor is embedded beween he main inverer and he supply. To achieve more robusness in erms of power supply insabiliy, anoher MOS device has been embedded beween main inverer and ground [6]. By he help fig 7 and eq (8) i can be deduced ha frequency deviaion decrease by nearly %. In fac, wha makes such improvemen is high oupu impedance of load and ail ransisors, creaing a power supply isolaion impression. Maneais used he isolaion mechanism which ineracs wih self biasing mechanism [8]. In he self biasing mechanism, as shown in Fig. 14, we direcly cancel he supply variaions o keep oscillaion frequency fixed. Here a srucure wih negaive feedback is used o reproduce new robus supply for inverers. As menioned above, Lee and Kim made he delay cells swing rapidly. Maneais sraegy made he cell a bi slow. This was compensaed for in Lee-Kim by posiive feedback. Fig 11 shows, Maneais archiecure has he bes behavior agains variaions of supply volage. Curren sarved is he second in his respec, and Lee-Kim and simple inverer have he weakes behavior. ISSN: ISBN:

6 (a) fig.13 Lee-Kim s frequency deviaions vs. power supply variaions As menioned above self-biasing is used o produce a robus supply. Self-bias consiss of wo sages. As shown in Fig. 14, a circui replica of curren source is equipped wih negaive feedback mechanism. In case of any supply deviaion, negaive loop changes in indirec proporion o he occurred variaion. As a resul self-bias mechanism compensaes for supply variaions. (b) Fig. 14: Self-bias circui As Fig. 11 shows, in Maneais archiecure frequency varies wih supply wih a negaive slope while for he res, frequency varies wih posiive slope. I is reasonable o conclude ha a ring oscillaor which is composed of cascade chain of differen inverers can be designed o build a more robus oscillaor. This way, he relaive frequency deviaion in erm of supply volage can be efficienly reduced. A soluion of 3-sage ring oscillaor wih reduced sensiiviy is given in Fig. 5. (c) Fig. 15: Propose RO srucure, a) firs las sage of proposed RO, b) middle sage of proposed RO, c) complee srucure of he proposed archiecure composed of self-bias block, combinaion of Maneais and Lee-Kim, and curren sarved delay sages. To describe he circui, i should be noed ha, Maneais delay cell is combined wih Lee-Kim delay cell srucured as fig.15.a. This way, in addiion o power supply rejecion, high frequency compensaion is achieved. Then, i is followed by curren sarved delay cell (Fig. 15.b) o compensae for decreased deviaion slope. Self-biasing can be added o he circui opionally. Shown in Fig. 16 is simulaion resul of proposed Ring oscillaor. From figure 16, i can be seen ha for he wors case sensiiviy is 0.1. While power supply changes by 10 percen he proposed srucure changes only by 1. percen. As fig 11 shows, Maneais cell has a negaive characerisic wih respec o power supply variaions. On he oher hand oher srucures show a posiive propery in erms of power supply deviaions. Using Maneais cell wih one of oher srucures in he chain of ring oscillaor makes he archiecure robus agains power supply variaion. To achieve simpliciy as well as robusness, Curren sarved delay cell were used as he complemenary mechanism. ISSN: ISBN:

7 As far as descripive equaions of ring oscillaors are concerned, V DD affecs curren sarved cell and Maneais cell in an indirec manner. Indeed power supply variaions affec such srucures hrough bias mechanism, eq (8). Addiion of self bias mechanism will lead o a beer performance. This is due o he way such a sysem provides bias, eq(10). Therefore, high supply rejecion is achieved by proposed archiecure. fig.17 sensiiviy of proposed srucure compared o previous works Fig. 16: Relaive frequency deviaion in erms of supply volage variaion for proposed ring oscillaor 4 Comparison of Proposed Archiecure wih Previous Works To make comparison, frequency deviaions of all menion srucures are shown in one coordinae plane. In represening he resuls, frequency variaions were normalized o he cener frequency of each ring oscillaor o make comparison easier. By analysis, i is apparen ha he sensiiviy of ring oscillaor from Fig. 5 is less han 1.% while for he bes case, i.e. Maneais, i is abou 3%. Simulaions were performed in HSpice BSMI4 model. As menioned above Maneais cell has he propery of reduced oscillaion frequency characerisic. We have used (0.5/5) μm channel lengh/widh for Maneais cell o achieve higher frequencies. For he case of Lee-Kim cell he same dimensions as Maneais cell were used. For oher circuis (0.35/35) μm channel lengh/widh has been used. During simulaion, device dimensions kep consan, or else differen characerisics would have been achieved. 5 Conclusions A Volage Conrolled Ring oscillaor was designed in his paper ha was robus o supply volage variaions. I has been shown ha compared o Maneais and Lee-Kim delay cells, is relaive frequency deviaions in erms of supply volage deviaions is improved, i.e. 1.% whereas for he Maneais, i is abou 3%. For more research one can derive analyical equaions relaing frequency o supply and consequenly opimize he menioned srucures. References: [1] A. Hajimiri, S. Limoyrakis, and T. H. Lee, Jier and Phase Noise in Ring Oscillaors, IEEE J. solid-sae circuis, vol. 34, NO. 6, JUNE [] M. Negahban, R. Behrasi, G.Tsang, H. Abouhossein, and G. Bouchaya, A wo-chip CMOS read channel for hard-disk drivers, in ISSCC Dig. Tech. papers, pp.16-17, Feb [3] L. DeVio, J. Newon, R. Croughwell, J. Bulzacchelli, and F. Benkley, A 5 and 155 MHz clock-recovery PLL, in ISSCC Dig. Tech. papers, pp , Feb [4] C. K. K. Yang, R. Farjad, and M. A. Horowiz, A 0.5-μm CMOS 4.0-Gbi/s serial link ransceiver wih daa recovery using oversampling, IEEE J. Solid-Sae Circuis, vol. 33, pp , May [5] G. Colavolpe, and R. Raheli, Deecion of linear modulaions in he presence of srong phase noise and frequency insabiliies, IEEE Trans. Commuinicaions, vol. 50, NO. 10, Oc. 00. [6] G. S. Jovanović, M. Sojčev, A mehod for improvemen sabiliy of a CMOS Volage Conrolled Ring Oscillaor, published on he web. [7] B. Razavi, Analysis and Design of Analog CMOS Inegraed Circuis, New York: McGraw-Hill, 001. [8] J. G. Maneais, Low-Jier processindependen DLL and PLL based on self- ISSN: ISBN:

8 biased echniques, IEEE JSSC, vol. 31, pp , Nov [9] J. Lee, and B. Kim, A Low Noise Fas-Lock Phase-Locked Loop wih adapive Bandwih Conrol, IEEE J. Solid-Sae Circuis, vol. 35, NO.8, Aug [10] G. S. Jovanović, and M. Sojčev, Curren sarved delay elemen wih symmeric load, IEEE J. Elecronics, vol. 93, No. 3, pp , March 006. [11] B. Kim, High Speed Clock Recovery in VLSI Using Hybrid Analog/Digial Techniques, Ph.D. Thesis, Memorandum No. UCB/ERL M90/50, Elecronics Research Lab, U.C. Berkeley, [1] D. Helman, A Muli-phase clock generaor/parallel-phase sampler in 1 micron CMOS: research projec. MS Repor, Deparmen of Elecrical Engineering and Compuer Sciences, U.C. Berkeley, May [13] S. Meha, Design of GigaHerz CMOS Prescalars, MS Thesis, U.C. Berkeley, May, ISSN: ISBN: