Positive Feedback: Bi-Stability. EECS 141 F01 Sequential Logic. Meta-Stability. Latch versus Flip-Flop. Mux-Based Latches
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1 Posiive Feedback: i-abiliy Vo=Vi2 V i V o2 EEC 4 F equenial V o V i2 = Vo V i V o2 V i2 = Vo A C V i = V o2 equenial Mea-abiliy FF s V i2 = Vo V i2 = Vo LOGIC C p,comb 2 sorage mechanisms posiive feedback charge-based δ V i = V o2 δ V i = V o2 Gain should be larger han in he ransiion region Lach versus Flip-Flop Mux-ased Laches Lach sores daa when clock is low Flip-Flop sores daa when clock rises Negaive lach (ransparen when CLK= ) Posiive lach (ransparen when CLK= )
2 Mux-ased Lach Lach: Transisor izing 4. (7.2/.2) (3.6/.2) (.8/.2) V (b) Non-overlapping clocks 2. (a) chemaic diagram Pseudo-saic Lach Lach 6 Transisor CMO Lach M5 M2 M4 M M3 CMO Clocked Lach ace Problem V loop M2 M4 M6 M M3 M8 M5 M7 ignal can race around during = 2
3 Lach-ased esign 2-phase dynamic flip-flop N lach is ransparen when = P lach is ransparen when = 2 N Lach P Lach pu ampled 2 pu Enable Maser-lave Lach Pair Maser-lave Flip-Flop Mux based A Overlapping Clocks Can Cause ace Condiions Undefined ignals Maser-lave Flip-Flop 2 phase non-overlapping clocks
4 2 phase non-overlapping clocks elay vs. eup/hold Times 35 2 N Lach 2 P Lach N Lach P Lach -pu [ps] 3 Minimum aa-pu eup 5 Hold aa- [ps] Flip-flop insensiive o clock overlap Pulse-Triggered Laches M2 M6 Flip-flops: M4 M3 M C L M8 M7 M5 C L2 Maser-lave Laches aa Pulse-Triggered Lach L L2 L aa secion secion C 2 MO LATCH Flip-Flop: Timing efiniions Propagaion elay ased Edge-Triggered seup hold ATA TALE N N2 plh pff ATA TALE = Mono-able Muli-Vibraor 4
5 Pulse-Triggered Laches Maximum Clock Frequency Hybrid Lach Flip-flop (HLFF), AM K-6 and K-7 : Vdd FF s Also: cdreg + cdlogic > hold LOGIC cd : conaminaion delay = minimum delay p,comb Pulse-Triggered Laches Pipelining 7474, lach as a second sage a EG a EG. log EG EG. EG log EG b EG b EG Non-pipelined version Pipelined version Pulse-Triggered Laches Pipelined using C 2 MO ense-amplifier-based flip-flop, EC Alpha 2264, rongam Firs sage is a sense amplifier, precharged o high, when = Afer rising edge of he clock sense amplifier generaes he pulse on or The pulse is capured in - lach Cross-coupled NAN has differen propagaion delays of rising and falling edges F G C C 2 C 3 NOA CMO Wha are he consrains on F and G? 5
6 Example TPC - True ingle Phase Clock PUN aic PN Number of a saic inversions should be even cluding logic ino he lach sering logic beween laches NOA CMO Modules oubled TPC Laches 2 3 PUN PN Combinaional logic Lach (a) -module PN oubled n-tpc lach oubled p-tpc lach 4 (b) -module TPC - True ingle Phase Clock TPC - True ingle Phase Clock M M M M PUN aic PN Precharged N Precharged P Non-precharged N Non-precharged P cluding logic ino he lach sering logic beween laches 6
7 Maser-lave TPC Flip-flops CMO chmi Trigger V V V Y (a) Posiive edge-riggered flip-flop (b) Negaive edge-riggered flip-flop V in M 4 V ou M (c) Posiive edge-riggered flip-flop using spli-oupu laches Moves swiching hreshold of firs inverer chmi Trigger chmi Trigger imulaed VTC Ou V ou V OH VTC wih hyseresis V OL V (V) V ou (V) V M- V M+ esores signal slopes V M V M+ V in V in (V) V in (V) Noise uppression using chmi Trigger CMO chmi Trigger (2) V in V ou M 4 V M+ M 6 V M M 5 + p M 7
8 Mulivibraor Circuis Asable Mulivibraors (Oscillaors) isable Mulivibraor flip-flop, chmi Trigger 2 N- ing Oscillaor T 5. Monosable Mulivibraor one-sho V (Vol) 3.. V V 3 V 5 Asable Mulivibraor oscillaor (nsec) simulaed response of 5-sage oscillaor Transiion-Triggered Monosable Volage Conroller Oscillaor (VCO) V V chmi Trigger resores signal slopes M6 M4 ELAY d d V conr M5 I ref M2 M M3 I ref Curren sarved inverer 6 phl (nsec) V conr (V) propagaion delay as a funcion of conrol volage Monosable Trigger (C-based) elaxaion Oscillaor A I I2 2 C (a) Trigger circui. C V M (b) Waveforms. T = 2 (log3) C 2 8
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