USB TRANSCEIVER MACROCELL INTERFACE WITH USB 3.0 APPLICATIONS USING FPGA IMPLEMENTATION

Transcription

1 USB TRANSCEIVER MACROCELL INTERFACE WITH USB 3.0 APPLICATIONS USING FPGA IMPLEMENTATION T Mahendra 1, N Mohan Raju 2, K Paramesh 3 Absrac The Universal Serial Bus(USB) Transceiver Macro cell Inerface (UTMI) could be a 2 wire, bi-direcional serial bus inerface. The USB3.0 specificaions ouline 3 forms of UTMI implemenaions depends on knowledge ransmission raes, hose area uni Low Speed (1.5MHz) solely (LS), Full Speed (12MHz) solely (FS) and High Speed (480MHz)/Full speed (12MHz) (HS). UTMI consiss of ransmission and Receiving secions, during which he Transmier of he UTMI sends knowledge o oally differen USB devices hrough D+ and D- lines whereas he Receiver ges knowledge on a similar lines. This presenaion reveals he FPGA implemenaion of UTMI wih HS/FS ransmission rae providing wih USB wo.0 specificaions. more UTMI has been designed by exploiaion VHDL code and simulaed, synhesized and programmed o he argeed Sparan2 family of FPGA wihin he Xilinx surroundings. Index Terms USB 3.0 Transceiver Macro Cell,Full Speed,Low Speed, Serial Inerface Engine,Device Specific Logic,Bi Suff,Bi Un Suff,Encoder,Decoder I. INTRODUCTION The Universal Serial Bus (USB) Transceiver Macrocell Inerface (UTMI) may be a 2 wire, bi-direcional serial bus inerface beween USB devices hrough D+ and D- lines. his can be one among he necessary useful blocks of USB conroller, which migh ransmi and receive knowledge o or from USB devices. There square measure 3 useful blocks gif in USB conroller; hose square measure Serial Inerface Engine (SIE), UTMI and Device Specific Logic (DSL). Figure one shows he diagram of UTMI. The parallel knowledge from SIE is aken ino he ransmi regiser and his knowledge is shipped o ransmi regiser from wherever he informaion is reborn serially. This serial knowledge is bi suffed o perform knowledge ransiions for clock recovery and (1) encrypion. Then he encoded knowledge is shipped on o he serial bus. once he informaion is received on he serial bus, i's decoded, bi unsuffed and is shipped o receive regiser. once he regiser is full, he informaion is shipped o receive regiser. This knowledge are besowed on he por wherever i's sampled by he SIE. The inen of he UTMI is o accelerae USB wo.0 peripheral developmen. T.MAHENDRA, PG Scholar, Deparmen Of ECE, Koam College Of Engineering, JNTUA, Kurnool, A.P,INDIA, N.MOHAN RAJU, Assisan Professor, Deparmen Of ECE, Koam College Of Engineering,, JNTUA, Kurnool, A.P,INDIA, K.Paramesh, Head, Assisan Professor, Deparmen Of ECE, Koam College Of Engineering, JNTUA, Kurnool, A.P,INDIA, Encode Shif Rx shif Decoder Bi suff Bi unsuff Rx Figure 1: Block diagram of UTMI. Feaures of he UTMI: Suppors 480 Mbi/s High Speed (HS)/ welve Mbi/s Full Speed (FS), FS solely knowledge ransmission raes. Uilizes 8-bi parallel por o ransmi and receive USB wo.0 cable knowledge. SYNC/EOP generaion and checking. Daa and clock recovery from serial sream on he USB. Bi-suffing/unsuffing and bi suff error deecion. Holding regisers o sage ransmi and receive knowledge. Abiliy o modify beween FS and HS erminaions/signaling II. Design Aspecs The presen UTMI has been designed consisen wih he subsequen specificaions provided by he USB wo.0 proocol. correc and finish of Packe (EOP) generaion by he ransmier. Correc and EOP deecion by he receiver receive error reporage. enabling or disabling he bi suffer and encoder depends on he operaional mode. Suspension of he ransceiver by he SIE. Furher he UTMI is spli ino 2 necessary modules ha ar he Transmier module and also he Receiver module. during his secion he look issues of hose modules are explained individually and inegraed o urge prime level Transceiver (UTMI) module. ISSN: X All Righs Reserved 2014 IJARECE 1210

2 A. The Transmier Module The diagram of he UTMI ransmier is shown in Figure2. The ransmier module has been enforced by considering he subsequen specificaions. The synchronise paern should be ransmied like a sho once he ransmier is iniiaed by he SIE. once six consecuive 1 s occur wihin he knowledge sream a zero o be insered. he informaion ough o be encoded vicimizaion Non come o Zero Inver on one ( -1) crypography echnique. The EOP paern 2 single over zeroes(d+ and D-lines ar carrying zero for 2 clock cycles) and somewha one ough o be ransmied once every packe or once SIE suspends he ransmier informaion and EOP ransmission on o he serial bus. B. The Receiver Module The diagram of he UTMI receiver is shown in Figure hree. The receiver module has been enforced by considering he subsequen specificaions. When correc paern is deeced ha ough o be inimaed o he SIE. If a zero isn' deeced when six consecuive 1 s a slip-up ough o be repored o he SIE. When EOP paern is deeced ha ough o be inimaed o he SIE. The ransmier logic faciliaes synchronise ransmission, ing parallel 8- bi knowledge from SIE, parallel o serial conversion of informaion, bi suffing, crypography, ransmission of he Encoder shif Bi suff logic Figure 2: Block diagram of UTMI Transmier. The receiver logic faciliaes correc deecion, decrypion, bi unsuffing, serial o parallel conversion of knowledge, receive error reporage and EOP deecion C. The Transceiver Module The ransmier and herefore he receiver modules area uni combined along o syle he ransceiver (UTMI) module. This ransceiver me all he USB3.0 specificaions hough-abou on op of. The ransceiver logic faciliaes he oupu of he ransmier o feed o he inpu of he receiver for purposeful verificaion. The Transceiver module has been designed wih he issues of individual modules of he ransmier and herefore he receiver Specificaions. Any he specified Transceiver module logic has been verified wih he purposeful simulaion followed by necessary Synhesis and perform Programming o he argeed FPGA Device. shif Decoder Bi un suff logic Figure 3: Block diagram of UTMI Receiver. ISSN: X All Righs Reserved 2014 IJARECE 1211

3 III SIMULATION RESULTS The individual modules of he UTMI are designed using VHDL as saed above and hey are simulaed wihin he Xilinx based Model Sim 6.0 environmen. A. The Transmier Module The Figure 4 shows he Simulaion resuls of UTMI ransmier. When TX valid signal goes high, encoded SYNC paern is ransmied and he signal x ready is assered. The daa presen on he daaln bus is encoded and ransmied on o he xdp, xdm lines. The signal x ready goes low when he daa is sampled by he TX regiser. C. The Transceiver Module The Figure 6 shows he Simulaion resuls of he Transceiver module ha ransmis and receives knowledge. once xvalid goes high, synchronize is ransmied. he informaion gif on he daa_busx is encoded and ransmied on o he DP, dm lines. When synchronize is deeced by he receiver rxacive is declared by he UTMI. he informaion gif on he DP, dm lines is decoded and sen o he SIE hrough rxdaa_bus by declaraive rxvalid signal. Rxdaa_bus conains since he ransmied knowledge is fed back o he receiver. Figure 4: UTMI Transmier Module B. The Receiver Module The Figure 5 shows he Simulaion resuls of UTMI receiver. once correc is deeced rxacive is declared. he info gif on rxdp, rxdm lines is decoded, serial o parallel born-again and sen o he SIE hrough knowledge ou bus by declaraive rxvalid signal. Figure 6: Transceiver (UTMI) Module. IV FPGA IMPLEMENTATION The op order module, UTMI is synhesized inside he Xilinx 8.1 ISE sofware package ool and i's programmed o he argeed SPARTAN 2 a pair of family of FPGA Device. he assored levels pf implemenaion like Synhesis repor, RTL View, Place and Roue Repor and Device Programming has been explained and unreal wihin he following sub secions. ISSN: X All Righs Reserved 2014 IJARECE 1212

4 h e Table 1: Synhesis Summary T a b l e 1 h A. RTL View This secion provides he image of Resiser elecronic ransisor Logic (RTL) views wihin he ype of schemaic and Nelis diagrams ha area uni shown in Figure seven and Figure eigh severally. Figure seven which provides RTL schemaic diagram reveals he pin diagram of prime order module wih such ha he desired} specified noes whereas Figure eigh reveals he Gae level logical diagram of prime order module wih he desired inpu and oupu pors(nelis view). B. Place and Roue Repor Figure 8: RTL nelis view This secion concenraes on course righ direcion no off course} FPGA device uilizaion ouline ha reveals he knowledge needed for correc layou a he exen of producing in he variey of Place and Roue repor. addiional i offers he emporal arrangemen synchronizaion of elecronic equipmen wih he imporan ime environmen. Device Uilizaion Summary: Number of GCLKs 1 ou of 4 25% Number of Exernal GCLKIOBs 1 ou of 4 25% Number of LOCed GCLKIOBs 0 ou of 1 0% Number of Exernal IOBs 29 ou of 86 33% Number of LOCed IOBs 0 ou of 29 0% Number of SLICEs 70 ou of % Toal REAL ime o Placer compleion: 2 secs Toal CPU ime o Placer compleion: 2 secs Figure 7: RTL Schemaic diagram C. Device Programming Afer successful process of synhesis he Targe device xc2s15 of Sparan2 is conneced o he sysem hrough priner por. The pin assignmen is specified in he User Consrain File (UCF). The funcional verificaion is carried ou by using a paern generaor. ISSN: X All Righs Reserved 2014 IJARECE 1213

5 Synhesis Repor: The below synhesis repor is generaed by Xilinx nine.2i ISE. Release 9.2i - xs J.36 Copyrigh (c) Xilinx, Inc. righs reserved. All Parameer TMPDIR se o./xs/projnav.mp CPU : 0.00 / 0.15 s pass on : zero.00 / 0.00 s Parameer xshdpdir se o./xs CPU : 0.00 / 0.15 s pass on : zero.00 / 0.00 s Reading design: umi_op.prj V. CONCLUSION The individual modules of UTMI are designed vicimisaion VHDL and verified funcionally wih he Model Sim 6.0. The UTMI Transmier is capable of changing parallel knowledge ino serial bis, playing bi suffing and secre wriing. The UTMI Receiver is capable of playing crypography biunsuffing and changing serial bis ino parallel knowledge. The purposeful simulaion has been wih success disbursed. he planning has been synhesized vicimisaion FPGA echnology from Xilinx. This syle is argeed o he device family_sparan2, device_xc2s15, and package_cs144 and speed ranked vi. The device belongs o he Verex-E cluser of FPGAs from Xilinx. The UTMI is mean o suppor HS/FS, FS solely and LS solely UTM implemenaions. The 3 choices permi one SIE implemenaion o be used wih any speed USB ransceiver. A vender will selec he ransceiver performance ha bes mees heir wans. VII. APPLICATIONS The UTMI has been developed ino a sandard code (Generalized USB Transceiver) which migh be used for developing he whole USB device sack. a number of he Low speed and High speed USB devices, ha square measure presenly accessible wihin he marke are: 1. Opical Mouse 2. Key Board 3. Priner 4. Scanner 5. Joy Sick 6. Memory Sick 7. Flash Memory 8. Mobiles 9. Video cameras. REFERENCES [1] Charles H Roh Digial sysem using VHDL.2 nd ediion, Thomson publicaion [2] Jayaram Bhasker A VHDL Primer 2 nd ediion, Prenice Hall publicaions [3] Sephen Brown, Zvonko Vranesic Fundamenals Digial logic wih VHDL design. 2 nd ediion, McGraw-Hill, Hardcover, Published July 2004 [4] Zainalabedin Navabi Vhdl Analysis and Modeling of Digial Sysems 2 nd ediion, McGraw- Hill, Hardcover, Published January 1998 [5] William Sallings, Daa and Compuer Communicaions,McGraw-Hill Publicaions. [6] Andrew S.Tannenbaum, Compuer Neworks, Pearson publicaions. [7] Z.Kohavi, Swiching and finie Auomaa Theory, Taa Mcgraw-Hill Publicaions [8] N.N.Biswas, Logic design heory, Prinice Hall of India Publicaions. [9] Morris Mano, digial design, Taa McGraw-Hill Publicaions. [10] Lala, Digial sysem Design Using PLDs, BSP Publicaions. VI. FUTURE SCOPE The UTMI has been enforced for 8-bi, however i may also be exended o 16- bi UTMI. I may also be designed o come up wih CRCs for managemen and knowledge packes. If AN SIE and Device specific logic square measure designed, he mixure of UTMI, SIE and Device specific logic may be used as a conroller of any USB device. ISSN: X All Righs Reserved 2014 IJARECE 1214