Freescale SPC5604BF1CLL6 Embedded NOR Flash with M27V Die Markings 32 Bit Power Architecture Automotive Microcontroller 90 nm Logic Process

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1 Freescale SPC5604BF1CLL6 Embedded NOR Flash with M27V Die Markings 32 Bit Power Architecture Automotive Microcontroller 90 nm Logic Process Process Review 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:

2 Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. PPR CYJM Revision 1.0 Published: July 18, 2011

3 Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process 3.1 General Device Structure 3.2 Metallization and Contacts 3.3 Logic transistors 4 Planar Analysis of NOR Flash 4.1 Overview 4.2 NOR Flash Planar Analysis 5 Cross-Sectional Analysis of NOR Flash 5.1 Cross-Sectional Analysis Horizontal Section P1AS1 Parallel to WL 5.2 Cross-Sectional Analysis Vertical Section P1AS2 Parallel to BL 6 Critical Dimensions 7 References 8 Statement of Measurement Uncertainty and Scope Variation About Chipworks

4 Overview Overview 1.1 List of Figures 2 Device Overview Package Top Package Bottom Package X-Ray Package X-Ray Detail Package Cross Section Die Photograph Die Markings Corner B Die Corner A Die Corner B Die Corner C Die Corner D Minimum Pitch Bond Pads Bond Pad NOR Logic Gate SEM Die at Poly with NOR Flash Shown 3 Process General Device Structure Section P2AS1 SEM Die Thickness Section P1AS1 SEM Die Edge Seals of Packaged Device Section P2S1 SEM Die Edge Seals of Deprocessed Die Section P1AS1 SEM Minimum Pitch Metal 1 Section P1AS2 SEM Minimum Pitch Metal 2 Section P1AS2 SEM Minimum Pitch Metal 3 Section P1AS2 SEM Minimum Pitch Metal 4 and Metal 5 Section P1AS1 SEM Contact Pitch Section P1AS1 SEM Contacted Gate Pitch Section P1AS1 SEM Logic FETs and PMD TEM Detail of Logic FET TEM Logic FET Dimensions TEM Logic FET Dielectric TEM Lattice Image Source/Drain Contact TEM 4 Planar Analysis of NOR Flash NOR Flash Array Metal 1 and Via 1 SEM NOR Flash Array Corner Poly 2 and Contacts SEM NOR Flash Cell Metal 3 SEM NOR Flash Cell Metal 2 SEM NOR Flash Cell Metal 1 SEM NOR Flash Cell Poly 2 SEM NOR Flash Cell Poly 1 SEM NOR Flash Cell Diffusion SEM

5 Overview Cross-Sectional Analysis of NOR Flash NOR Flash Overview Horizontal Section P1AS1 SEM WL Stacked Vias Horizontal Section P1AS1 SEM Detail of Flash Gates Horizontal Section P1AS1 SEM NOR Flash Overview Vertical Section P1AS2 SEM NOR Flash Substrate Doping Vertical Section P1AS2 SCM Substrate Doping at Margin of NOR Flash SCM NOR Flash Cells TEM Adjacent NOR Flash Cells Etched Sample P1AS2 SEM Single NOR Flash Cell TEM NOR Flash CG Interpoly Dielectric TEM NOR Flash Floating Gate Dielectric TEM 1.2 List of Tables 1 Overview Device Identification Device Summary Process Summary 2 Device Overview Package and Die Dimensions 3 Process Metallization Minimum Vertical Dimensions Metallization Minimum Horizontal Dimensions 4 Planar Analysis of NOR Flash Summary of Code Flash Block Summary of Data Flash Block Likely Organization of Code Flash Likely Organization of Data Flash Summary of Embedded Flash Memory Cell Structure Embedded Flash Memory Critical Dimensions 6 Critical Dimensions Embedded NOR Flash Cell Critical Dimensions

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