STMicroelectronics NAND128W3A2BN6E 128 Mbit NAND Flash Memory Structural Analysis

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1 July 6, 2006 STMicroelectronics NAND128W3A2BN6E Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.

2 STMicroelectronics NAND128W3A2BN6E Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Transistors and Poly 3.7 High Voltage Transistors 3.8 Isolation 3.9 Wells and Substrate 4 Flash Cell Analysis 4.1 Flash Cell in Plan-View 4.2 Cross-Sectional Analysis (Parallel to Bit Line) 4.3 Cross-Sectional Analysis (Parallel to Word Line) 5 Materials Analysis 5.1 TEM-EDS Analysis of the Dielectrics 5.2 TEM-EDS Analysis of the Metal 2 and Metal TEM-EDS Flash Array Transistors 6 References 7 Critical Dimensions 7.1 Horizontal Dimensions 7.2 Vertical Dimensions Report Evaluation

3 STMicroelectronics NAND128W3A2BN6E Overview Overview 1.1 List of Figures 2 Device Overview Package Top Package Bottom Package Pin-Out View Package X-Ray Die Photograph Die Markings Die Corner Die Corner Die Corner Die Corner Minimum Pitch Bond Pads Fuse Array Blown Fuses 3 Process Analysis General View of NAND128W3A2BN6E Die Edge Die Seal Bond Pad Right End Bond Pad Passivation Passivation Over Closely Spaced Metal 2 Lines TEM Silicon Nitride Passivation Layer IMD Pre-Metal Dielectric Minimum Pitch Metal TEM Metal 2 Barrier Layers TEM Minimum Pitch Metal Minimum Pitch Vias Minimum Pitch Contacts to Diffusion Contacts to Poly Contacts to Poly W/TiN/Ti Butted Contact Poly 4 Contact to Diffusion TEM Poly 3 Contact to Diffusion Poly 4 Bit Line Contacts TEM Poly 4 Contact Top TEM Poly 4 Contact Bottom

4 STMicroelectronics NAND128W3A2BN6E Overview Minimum Gate Length NMOS Transistor Minimum Gate Length Peripheral PMOS Transistors Peripheral Transistor Glass Etch Gate Contact High Voltage Transistor Polycide Over STI Minimum Width STI SCM Peripheral N-Well and P-Well SCM Embedded P-Well SRP Shallow Peripheral N-Well SRP Peripheral P-Well Embedded Array P-Well 4 Flash Cell Analysis NAND Architecture Metal Metal 1 Bit Lines and Source Line Straps Polycide Word Lines (poly 2) Contacts to Bit line and Source Select Lines Poly 1 Floating Gates Flash Cell in Cross-Section TEM Flash Cells TEM Interpoly Dielectric TEM Tunnel Oxide TEM Source Line and Source Select Gate Bit Line Contact TEM Bit Line Contact and Bit Line Select TEM Word Line and Floating Gates TEM Floating Gate TEM Tunnel Oxide and Gate Width Bit Line Contacts 5 Materials Analysis TEM-EDS Spectra of Oxynitride and Oxide Passivation TEM-EDS Spectra of IMD Layers TEM-EDS Spectra of PMD Layers TEM-EDS Metal 2 TiN Barrier and Adhesion Layers TEM-EDS Metal TEM-EDS Gate Silicide and Cap Oxide

5 STMicroelectronics NAND128W3A2BN6ENAND128W3A2BN6E Overview List of Tables 1 Overview Device Summary Process Summary 3 Process Analysis Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor and Polycide Dimensions 4 Flash Cell Analysis Flash Cell Dimensions 7 Critical Dimensions Minimum Pitch Metals Contacts and Vias Die, Transistors, Poly and Isolation Vertical Dimensions

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