Lucent ORCA OR2C15A-2S208 FPGA Circuit Analysis

Transcription

1 August 12, 1999 Lucent ORCA OR2C15A-2S208 FPGA Circuit Analysis Table of Contents List of Figures...Page 1 Device Summary Sheet...Page 4 Introduction...Page 6 PLC Architecture...Tab 1 Programmable Function Unit...Tab 2 PLC Routing Resources...Tab 3 Programmable I/O Cell...Tab 4 PIC Routing Resources...Tab 5 ORCA Internal Oscillator...Tab 6 Signal Naming Conventions...Tab 7 Signal Cross-Reference...Tab 8 For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call a Sales Representative at Chipworks. Telephone (613) Facsimile (613) Rev F2.2

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3 Lucent OR2C15A-2S208 ORCA FPGA Page 1 List of Figures Package Markings Package X-Ray Pin Configuration Die Markings Die Photograph Annotated Die Photograph Die Architecture Programmable Logic Cell Architecture Programmable I/O Cell Architecture Top Level Diagram PLC Architecture PIC Architecture Programmable Function Unit x2 Synchronous Dual Port Memory LUT : Look-up Table x1 SRAM SRAM Cell Read Address Decoder Write Address Decoder Write Address Decoder I Write Address Decoder II Write Address Decoder III PFU 4x1 Multiplier Multiplier Control Address Switch Write Enable Write Pulse Generator Write Port Enable Latch Write Data Register Address Register Program Control Logic PFU Latches/Flip-Flops Latch/Flip-Flop FEMUX: Front End MUX PFU Output MUX Clock Polarity C0/CIN MUX SSPM/SDPM Clocks Latch/FF Clocks CL: Configuration Latch

4 Lucent OR2C15A-2S208 ORCA FPGA Page 2 PLC Routing Resources Input CIP Auxiliary Routing Resources Input Routing Resources Input MUX Output Routing Resources C0-RR : C0 Routing Resources CMUX: CIN and COUT Routing Resource MUX Clock R-nodes VCK: Vertical Clock Input Routing Resources HCK: Horizontal Clock Input Routing Resources PLC_BIDI BIDI: 3-Statable Bidirectional Buffer TRI Input R-nodes Address Buffer Programmable I/O Cell PIC Input Buffer Output Buffer Boundary Scan Cell Flip-Flop I Flip-Flop II Boundary Scan MUX I Boundary Scan MUX II PIC Routing Resources PIC BIDI PIC_BIDI: 3-Statable Bidirectional Buffer State Enable Signal MUX LLDRV: Long Line Driver PIC-OUT MUX IN-Buffer PIC x1 R-nodes PIC-Clock R-nodes ORCA Internal Oscillator Internal Oscillator Oscillator Divider of Oscillator Reset D Flip-Flop Frequency Divider D Flip-Flop Internal Oscillator MUX

5 Lucent OR2C15A-2S208 ORCA FPGA Page Oscillator R-nodes A.1.0 Symbol Conventions A.2.0 Symbol Definitions - 1 A.2.1 Symbol Definitions - 2 A.2.2 Symbol Definitions - 3 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation A.6.0 FPGA Symbol Definitions - 1 A.6.1 FPGA Symbol Definitions - 2 A.6.2 FPGA Symbol Definitions - 3 A.6.3 FPGA Symbol Definitions - 4 A.6.4 FPGA Symbol Definitions - 5 A.6.5 FPGA Symbol Definitions - 6 A.6.6 FPGA Symbol Definitions - 7 A.6.7 FPGA Symbol Definitions - 8 A.6.8 FPGA Symbol Definitions - 9