Learning Outcomes. Unit 13. Sequential Logic BISTABLES, LATCHES, AND FLIP- FLOPS. I understand the difference between levelsensitive

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1 Learning Outcomes Unit 1 I understand the difference between levelsensitive and edge-sensitive I understand how to create an edge-triggered FF from latches Sequential Logic onstructs Sequential Logic Suppose we have a sequence of input numbers on X[:] that are entered over that we want to sum up Possible solution: Route the outputs so we can add the current sum to the input X How sequential building blocks work BISTABLES, LATHES, AN FLIP- FLOPS X[:] 9,, A A B B S S 14,5, [:]

2 Sequential Logic 1.5 Sequential Logic 1.6 Suppose we have a sequence of input numbers on X[:] that are entered over that we want to sum up Possible solution: Route the outputs back to the inputs so we can add the current sum to the input X Problem 1: No way to Problem : Outputs can to inputs and be added more than once per input number 9,, Outputs can feedback to inputs and update them sum more than once per input X X Possible Solution A A B B S S Add logic at outputs to just capture and remember the new sum until we re ready to input the next number in the sequence This logic should remember (i.e. sequential logic) the sum and only update it when the next number arrives 9,, X X A A B B S S The data can still loop around and add up again (+=4) but if we just hold our output = then the feedback loop will be broken We remember initial sum of until input arrives at which point we d capture & remember the sum 5. Sequence 1.7 Sequence 1. If X changes then should also change once per cycle That is why we will use a to ensure the outputs can only update once per cycle X X A A B B 4 S S 1 lock lear The on lear will cause to be initialized to, but then can t change until the next positive edge That means we will just keep adding + = X X A A B B 4 S S 1 lock lear lock lear X 9

3 Sequence Sequence At the edge the flip-flops will sample the inputs and then remember until the next positive edge That means we will just keep adding + = 5 Finally, at the positive edge the flip-flops will sample the inputs and then remember 14 X X A A B B S S lock lear X 9 X X A A B B S S lock lear X 9 lock lear 5 lock lear Sequential Logic -Latches But how do flip-flops work? Our first goal will be to design a circuit that can remember one bit of information Easiest approach The primary building block of sequential logic is a -Latch -Latches (ata latches) store/remember/hold data when the clock is and data when the clock is (LK= ) -Latch losed when LK=1 But how do you change the input? A signal should only have one driver LK losed when LK= These "switches" which can be closed or open are really transistors that can be on or off

4 Transparent & Hold Mode of -Latches -Latches Hold Mode The -Latch operates in either or mode based on the clock value x Latch x Hold Mode Transparent Mode Function Table escription of -Latch When lock = 1 When lock = LK LK Transparent Mode (= when LK=1) Hold Mode (= when LK=) When =1, outputs change based on inputs When =, outputs don t change no matter what the inputs do LK Latch -Latches Hold Mode x Hold Mode Transparent Mode 1.15 Notation To show that remembers its value we can put it in the past tense: = (urrent Value of = Old Value of ) OR put it in the future tense * = (Next Value of = urrent Value of ) Indicates next-value of x urrent Value = Old Value * * x Next Value = urrent Value 1.16

5 What if we put -Latches at the outputs We ll change X on every clock period X X A A B B S S 1 lock X X A A B B S S 1 lock X lock When = => * = When =1 => * = Since the clock starts off low, the outputs of the latches can t change and just hold at When the clock goes high the goes through to and is free to loop back around X X A A B B S S 1 lock X X X A A B B S S 1 lock X lock lock When = => * = When =1 => * = When = => * = When =1 => * =

6 Once it loops back around it will be added again, change the value and go through to and loop back around again This feedback loop continues until the clock goes low again 4 X X A A B B S S lock X 4 6 X X A A B B S S 1 6 lock X 4 6 lock 4 lock 4 6 When = => * = When =1 => * = When = => * = When =1 => * = When the clock goes low again, the outputs will hold at their current value until the clock goes high When the clock goes high, the outputs will be free to change and we will get the feedback problem X X A A B B S S 11 1 lock X X X A A B B S S 11 1 lock X lock 4 6 lock When = => * = When =1 => * = When = => * = When =1 => * =

7 Latches clearly don t work The goal should be to get one changeof the outputs per clock period X X A A B B S S 11 1 lock X FLIP-FLOPS lock When = => * = When =1 => * = Flip-Flops vs. Latches Flip-Flops Latches Asynchronous lock/enable input Level Sensitive Outputs can change any lock = 1 Flip-Flops Synchronous lock Input Edge-Sensitive Outputs change only on the positive (negative) edges hange Latches to Flip-Flops -Latch -FF LK Triangle at clock input indicates edgesensitive FF -Latch -FF LK LK

8 Flip-Flops Positive-Edge Triggered -FF To indicate negative-edge triggered use a bubble in front of the clock input Positive-Edge Triggered -FF Negative-Edge Triggered -FF looks at only at the positive-edge LK * * x 1 x FF LK -FF LK LK No bubble indicates positive-edge triggered Bubble indicates negative-edge triggered only samples at the positive edges and then holds that value until the next edge Negative-Edge Triggered -FF FF Example looks at only at the negative-edge LK * * x 1 x Assume positive edge-triggered FF LK only samples at the negative edges and then holds that value until the next edge

9 Shift Register Shift Register A shift register is a device that acts as a queue or FIFO (First-in, First-Out). It can store n bits and each bit moves one step forward each clock cycle One bit comes in the overall input per clock One bit falls out the output per clock Shift Register BUILING A FLIP FLOP When we want to ensure an output updates only ONE per clock, we need to use flip-flops (not latches or bistables)!

10 Building an Edge-Triggered evice Master-Slave -FF We generally build FFs from latches To build a device that can only change at 1 instant (clock edge) we can: Try to only enable 1 latch for a small in Use two latches running on clock phases To build an edge-triggered-ff we can use two -Latches Master Slave lock Input ueue oor opening and closing almost instantly Two door system (when 1 is open the other is closed) These latches form a flip-flop omplete the Waveform Master-Slave -FF lock Master Slave To implement a positive edge-triggered -FF change the clock inversion lock Master Slave Negative-Edge Triggered Positive-Edge Triggered

11 1.41 Initializing Outputs 1.4 Need to be able to initialize to a value ( or 1) FF inputs are often connected to logic that will produce values after initialization Two are often included: (PRE)SET and LEAR INITIALIING OUTPUTS Logic SET LK LR When LEAR = active *= When SET = active *= When NEITHER = active FF operation Note: LR and SET have over normal FF inputs Initializing Outputs Initializing Outputs To help us initialize our FF s use a signal Generally produced for us and given along with LK It starts at Active (1)when power and then goes to Inactive ()for the When it s active use it to initialize the FF s and then it will go inactive for the rest of and the FF s will work based on their inputs Active (1) at = Inactive () for the rest of Need to be able to initialize to a known value ( or 1) Logic SET LK LR 1 * = When = 1, LR is active and is forced to regardless of Logic SET LK LR * = When =, LR is inactive and looks at at each clock edge

12 Implementing an Initial State Synchronous vs. Asynchronous When is activated s initialize to and then when it goes back to 1 the s look at the inputs Forces s to because it s connected to the LR inputs The new preset and clear inputs can be built to be synchronous or asynchronous These terms refer to when the initialization takes place Asynchronous initialize when signal is activated Synchronous initialize at clock edge... Once goes to, the FF s look at the inputs lock LR Synchronous lock LR Asynchronous 1... s s Synchronous SET or LR means the signal must be active at a clock edge before will initialize Asynchronous SET or LR means will initialize as soon as the SET or LR signal is activated Set / lear Example Exercise omplete the waveform for a -FF with asynchronous SET and LR X 1 SET LR SET 1 F LK LR LK LR SET LK X 1 1 F

13 Register Resets/lears Using muxes to control when register save data REGISTER WITH ENABLES When the power turns on the bit stored in a flip-flop will initialize to a random value Better to initialize it to a known value (usually 's) Use a special signal called "reset" to force the flip-flops to 's LK i i * 1 LR LR LR 1 1, X X i LR 1 X LK bit Register Register Problem Solution Whatever the value is at the clock edge is sampled and passed to the output until the next clock edge Problem: Register will save data on EVER edge LK Often we want the ability to save on one edge and then keep that value for many more cycles Registers (-FF s) will sample the bit every clock edge and pass it to Somes we may want to hold the value of and ignore even at a clock edge We can add an enable input and some logic in front of the -FF to accomplish this LK EN i i * EN LK 1 S FF with ata Enable (Always clocks, but selectively chooses old value,, or new value ) LR [:] 1 [:]? ,1 X X X i 1 X X X i 4-bit Register On clock edge, is passed to

14 Registers w/ Enables 4-bit Register w/ ata (Load) Enable When EN=, value is passed back to the input and thus will maintain its value at the next clock edge When EN=1, value is passed to the input and thus will change at the edge based on EN LK 1 EN LK When EN=, is recycled back to the input 1 S 1 S LR When EN=1, input is passed to FF input LR Registers (-FF s) will sample the bit every clock edge and pass it to Somes we may want to hold the value of and ignore even at a clock edge We can add an enable input and some logic in front of the -FF to accomplish this LK EN i i *,1 X X X i 1 X X X i EN LK 1 S 1 S 1 S 1 S 4-bit register with 4-bit wide -to-1 mux in front of the inputs LR LR LR LR 1 Registers w/ Enables The value is sampled at the clock edge only if the enable is active Otherwise the current value is maintained LK EN OUNTERS [:] [:]

15 ounters ount (Add 1 to ) at each clock edge Up ounter: * = + 1 an also build a down counter as well (* = 1) Standard counter components include other features Resets: Reset count to Enables: Will not count at edge if EN= Parallel Load Inputs: an initialize count to a value P (i.e. * = P rather than +1) LK 1 (+) Register Sample 4-bit ounter 4-bit Up ounter : a synchronous reset input PE and P i inputs: loads with P when PE is active E: ount Enable Must be active for the counter to count up T (Terminal ount) output Active when =1111 AN counter is enabled T = EN 1 Mealy output Indicates that on the next edge it will roll over to E P P1 P P PE LK 4-bit NTR 1 T LK PE E *,1 X X X 1 X X 1 X P ounters ounter Exercise LK LK E PE PE P-P 111 E P[:] T [:] SR=active at clock edge, thus = *=+1 Enable = off, thus holds *=+1 *=+1 PE = active, thus *=+1 *=+1 =P Mealy T output: EN 1

16 ounter esign 1.61 Sketch the design of the 4-bit counter presented on the previous slides E + 1 P[:] PE 1 [:] [:] Reg [:] LR LK LK T