ASYNCHRONOUS SEQUENTIAL CIRCUIT CONCEPTS
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1 ASYNHRONOUS SEQUENTIAL IRUIT ONEPTS Synchronous ircuit Asynchronous ircuit (a) Synchronous to Asynchronous Asynchronous ircuit Asynchronous Signals Synchronous ircuit (b) Asynchronous to Synchronous Synchronous ircuit Asynchronous Signals Synchronous ircuit lock X lock Y (c) Synchronous ircuits with Unrelated locks /7/98 4/4/98
2 AN ASYNHRONOUS BINARY OUNTER Illustrates the nature of asynchronous behavior Serves as the receiving circuit in the synchronous to asynchronous interface case. NT ASYNHRONOUS BINARY OUNTER LEAR 0 (a) NT LEAR 0 2 /7/98 4/4/
3 OMBINATIONAL HAZARS efinitions Note that this has the same behavior as a synchronous counter with NT as the clock. But the realization is quite different. There are no flip-flops in the design, for example. ombinational Hazard efinitions A combinational hazard occurs if an output signal changes twice when it should not change at all or changes three or more times when it should change only once. A logic hazard is characterized by the fact that it can be eliminated by proper combinational design methods. Function hazards come with the function and cannot be dealt with by basic design techniques, but instead require manipulation of circuit delay. 3 /7/98 4/4/98
4 OMBINATIONAL HAZARS Logic Hazards A single-input change static hazard (SIS hazard) is a momentary change in an output that occurs as the result of the change of a single input variable when the value of the output is to remain fixed. If the fixed value is a, then an SIS -hazard. If the fixed value is a 0, then an SIS 0-hazard. If the input is to change once and changes an odd number of times (three or more), then a dynamic hazard. X A B (a) static -hazard (b) static 0-hazard (c) dynamic hazard 4 /7/98 4/4/98
5 OMBINATIONAL HAZARS Logic Hazards Suppose that signals A, B, and feed the NT input of the asynchronous binary counter. Then in all cases, the counter will advance by one or more counts too many if the hazard is present compared to when it is not present. Thus, the presence of a logic hazard on the output of the circuit driving NT will cause malfunction whether that circuit is synchronous or asynchronous. Suppose that the circuit is synchronous and has the following form: X K Y Q Q 0 S -> 0 a b NT K Z K Q (a) c 5 /7/98 4/4/98
6 OMBINATIONAL HAZARS Logic Hazards The waveforms for the flip-flop values and change shown: 0 = S a 5 ns b c NT 6 /7/98 4/4/98
7 OMBINATIONAL HAZARS Logic Hazards Thus, this SIS -hazard causes an extra count. There are many situations in which SIS hazards cause such malfunctions at interfaces, but most particularly within asynchronous circuits. Static Hazard Prevention an we prevent such a static hazard? Looking at the combinational circuit and its K-map, S S 0 (b) NT (a) 7 /7/98 4/4/98
8 OMBINATIONAL HAZARS Logic Hazards Note that in the location of the hazard, two adjacent s appear on the K-map and that these ones are in different terms in the function implementation. When S changes from to 0, one of the terms goes to 0 (NAN output to ) before the other becomes (NAN output becomes 0), thereby causing the hazard. If these two adjacent s are in the same term, then the output will remain fixed as S changes. Thus, add term O to eliminate the hazard. This approach can be used for all logic hazards including multiple-input change static hazards (see supplement 3). A cookbook solution is to use ALL prime implicants to eliminate all static hazards in a sum of products implementation. 8 /7/98 4/4/98
9 OMBINATIONAL HAZARS Function Hazards A function hazard is a static hazard that occurs for multiple input changes to a combinational circuit that cannot be eliminated by logical means. Location of function hazards: S /7/98 4/4/98
10 OMBINATIONAL HAZARS ealing with Function Hazards Add delays so that the terms are activated in an order that prevents the output from changing (delay dependent solutions are risky, but are used). esign the circuit so that the combinational logic with the function hazards has only single-input changes on its inputs (may be impossible). If the circuit is synchronous and all inputs to the combinational circuit come from flip-flops, move the circuit inputs to the flip-flop inputs and add a flipflop on the output. A flip-flop due to its design will have a hazard free output. 0(t+) 0(t) S(t+) S(t) NT (t+) (t) 0 /7/98 4/4/98
11 SYNHRONIZATION The Problem Asynchronous circuits or asynchronous signals driving a synchronous circuit. The problem: RY = 0 RY = S0/ S/0 RY = 0, S2/0 (a) State diagram RY = 0, Reset Set y0 y y2 lock lear lear Z RY (b) Logic diagram /7/98 4/4/98
12 SYNHRONIZATION The Problem lock RY y0 y y2 (a) orrect circuit response to RY lock RY y0 y0 resets y y fails to set y2 (b) Incorrect circuit response to RY: invalid state (0,0,0) results. lock RY y0 y0 fails to reset y y sets y2 2 /7/98 4/4/98 (c) Incorrect circuit response to RY: invalid states (,,0), (0,,) and (,0,) result.
13 SYNHRONIZATION The Solution The problem occurs because due to delays and other complex factors, multiple flip-flops perceive the RY input as having different values which RY changes in the setup time-hold time interval. Solution: Make sure RY enter the circuit via a single flip-flop: Reset Set y0 y y2 lock lear lear RY lear RY_S 3 /7/98 4/4/98
14 SYNHRONIZATION The Solution The added flip-flop synchronizes RY with the local clock and is called a synchronizing flip-flop. lock RY RY_S y0 y y2 lock (a) ircuit response to RY with sensing at the lock edge where RY changes RY RY_S y0 y y2 (b) ircuit response to RY with sensing at the next lock edge where RY changes 4 /7/98 4/4/98
15 METASTABILITY The Problem But what happens when RY changes during the synchronizing flip-flop setup time-hold time interval? Usually, its output either changes or it doesn t which is acceptable behavior. But sometimes not! Latches in flip-flops have three states represented by the following mechanical analogy: M 0 5 /7/98 4/4/98
16 METASTABILITY The Problem If the input to the flip-flop changes in a very tiny window 0 s of picoseconds wide, the metastable state can be entered. This has the effect having an output which is between and 0 or of significantly delaying the output. Other flip-flops see Q here which brings back synchronization problem! LOK 30 ns 45 ns 3 ns Q 6 /7/98 4/4/98
17 METASTABILITY The Solution Use a series of synchronizing flip-flops. This can be done if the added delay is not a problem. Typically use two to three flip-flops in series; some commercial design use as many as six. 7 /7/98 4/4/98
18 SYNHRONOUS IRUIT PITFALLS Examples Just because a circuit has a clock input does not mean it is a synchronous circuit. Examples that are not: Ripple counters Suicide counters lock ount Binary ounter Asynchronous lear A 3 A 2 A A 0 8 /7/98 4/4/98
19 SYNHRONOUS IRUIT PITFALLS Prevention on t use direct inputs, clear or preset to a flip-flop or register for anything but power-up reset or overall system reset. If you need a reset build it into your logic. on t put anything input clock inputs except for clocks or gated clocks. o use synchronization flip-flops and do deal with metastability. There will be design situations in which you simply cannot do the above; but such situations are far more infrequent than many designers believe! 9 /7/98 4/4/98
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