Practical Generalizations of Asynchronous State Machines æ

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1 Practical Generalizations of Asynchronous State Machines æ Kenneth Y. Yun David L. Dill Steven M. Nowick Computer Systems Laboratory Departments of Electrical Engineering and Computer Science Stanford University Stanford, CA 9435 Abstract Based on a study of systems requirements, we propose to extend burst-mode specifications, a class of asynchronous finite-state machine specifications that allows multiple-input changes. The proposed extensions allow concurrent transitions of inputs and outputs and input choices based on level conditional signals. We present an example that features the proposed extensions and point out the deficiencies of existing specification styles, in particular, STG and original burst-mode. We analyze the impact of these extensions on the hazard-free implementation of the 3D machine andits synthesis procedure. We present the results of experiments using the modified 3D synthesis tool and show that the performance numbers are consistent with examples of comparable complexity not requiring the extensions. Introduction Recently, many well-known advantages of asynchronous designs have been reaffirmed partly due to the advancement of VLSI technology and partly due to the recognition of the possibility that the CAD tools can be used to to alleviate the designers from being overwhelmed by complex tasks, such as hazard-free implementation and critical-race-free state assignment. As a result, a flurry of new asynchronous design styles and automatic synthesis tools [, 4, 5, 6, 9,, 3, 4, 7,, ] have been introduced to exploit these advantages in system design. There are roughly three distinct categories of asynchronoussynthesis methods available today: Transformations from HDL descriptions [, 4,, 5], STG (Signal Transition Graph) / SG (State Graph) synthesis [, 5, 9, 3, 4, ], and multiple-input change AFSM synthesis [6, 7, 3]. Although asynchronous designs have been applied both to data path and control circuits, we believe that the highest payoff will come from applications to interface circuits and controllers. There are two questions we must consider: What is required in a class of specifications to describe the signalling and timing constraints of most interfaces and controllers? and What specifications can be implemented efficiently and correctly by automatic synthesis tools? In answering these questions, we have examined a number of interfaces and controllers in particular, the examples from the HP Post Office [7] and industry-standard backplane and local bus controllers. We have determined that mechanisms to handle a moderate degree of concurrency and to select alternative responses based on conditional signal levels as well as signal transitions (events) are essential, and that I/O-mode operation [, 5, 6, 9,, 3] is not necessary in most applications. Then we examined existing specification styles, in particular, STG and burst-mode. The currently accepted form of STG is an interpreted free-choice Petri net [5, 9, 3, 4, ]. The strong suit of the STG is its ability to express concurrency. Its main weakness is the awkwardness in specifying choices. In a free-choice STG specification, the environment can steer the future behavior of the machine only by selecting an input transition among a number of conflicting choices. It cannot æ This work was supported by the Semiconductor Research Corporation, Contract no. 9-DJ-5,and by the Stanford Center for Integrated Systems, Research Thrust in Synthesis and Verification of Multi-ModuleSystems. handle choices based on a sequence of events or choices based on signal levels. A burst-mode specification is a variation of a Mealy machine that allows multiple-input changes in a burst fashion in a given state, when all of a specified set of input transitions arrive, the machine generates a set of output changes and moves to a new state. The specified input transitions can arrive in arbitrary order (thus allowing input concurrency), and the outputs are generated concurrently. The advantages of a burst-mode specification over STG specifications are that it is similar to the synchronous Mealy machine designers are familiar with, that the input choice is more flexible than that of the STG, and that the state encoding is more flexible in the implementations. Burst-mode specifications have been very useful in specifying large, practical controllers, such as a SCSI data transfer protocol controller [9] and an asynchronous high performance cache controller [6]. The main practical disadvantage is that it does not allow input transitions to be concurrent with output transitions. The input choice mechanism, albeit more flexible than the STG, is still primitive. For example, it cannot handle choices between two sets of concurrent events if one set is a subset of the other the subset restriction. Therefore, we propose to extend the burst-mode specification (much of the formalism used both in the original burst-mode and in the proposed extensions is derived from the asynchronous state machine specification style and the examples from the Post Office by Davis et al. currently with HP Labs) in two ways: to allow concurrent transitions of inputs and outputs and to allow input choices based on level conditional signals. The results are a design style that better supports real-life systems design requirements and incorporation of these generalizations in a hazard-free implementation (called the 3D asynchronous state machine). Extending Burst-mode Specifications A burst-mode asynchronous finite state machine is specified by a state diagram [7, 3, ], which consists of a finite number of states, a set of labelled arcs connecting pairs of states, and a start state. Each arc is labelled with a set of possible signal transitions. Each transition consists of an input burst (a non-empty set of input transitions) and an output burst (a set of output transitions). In a given state, when all the inputs in the specified input burst have changed value, the machine generates the corresponding output burst and moves to a new state. Only specified input changes may occur, and input transitions may arrive in arbitrary order. We propose two extensions to burst-mode specifications: æ Directed-don t-care transitions of inputs in input bursts are allowed provided that at least one input transition in the input burst is guaranteed to fire. æ Input choices based on level conditional signals as well as events (transitions) are allowed.

2 . Allowing Directed-don t-care in InputBurst Definition Signal transitions: æ s + denotes that s changes monotonically from to (if s initially ) or remains (if s initially ); s, denotes that s changesmonotonicallyfrom to (if s initially ) orremains (if s initially ). A signal transition s + or s, is said to be terminating. æ s æ denotes that s remains, monotonically changes from to, or remains if the next terminating transition of s is s +, and that s remains, monotonically changes from to, or remains if the next terminating transition of s is s,. A signal transition s æ is said to be a directed-don t-care. æ A terminating transition is compulsory if there is no directeddon t-care transition of the same signal in the states immediately preceding the current state. Informally, the terminating transition of a signal means that the signal changes to the specified level, if it is not already at the specified level, and the directed-don t-care transition of a signal means that the signal eventually changes to the level specified by the next terminating transition. Note that the directed-don t-care does not mean that the signal can oscillate freely between and (as in a true don t care). In an extended-burst-mode specification, the polarities of terminating transitions of a signal must alternate. For example, the firing sequences,a + a,, a + a æ a, and a, a æ a æ a +, are valid, but a + a + is not. In extended-burst-mode specifications, an input burst is a nonempty set of input transitions (terminating or directed-don t-care), at least one of which must be a compulsory transition. In the original burst-mode specifications, the output burst must not be generated until all the specified inputs in the input burst have changed value. In extended-burst-mode specifications, the output burst must not be generated until all the terminating transitions in the input burst have fired. In the original burst-mode specifications, every state has a unique entry point described by input and output values. In extended-burst-mode specifications, certain states may have multiple valid entry points due to the directed-don t-cares in the predecessor states input bursts. We require that the set of possible entry points into a state from every predecessorstate be identical the common-entry-set requirement. For example, the set of valid entry points to S from S in figure a is f; g, but from S to S it is fg. Thus this specification is illegal. A legal specification illustrating a common-entry-set is shown in figure b. a c / abcxy = b+c* / a+c+ / x y (a) no common entry set abcxy = b+c* / a+c+ / y a c* / c / x 3 (b) common entry set Figure : Example (Common-entry-set).. Conditional Input Burst In the original burst-mode specifications, the input choices are limited to the distinguishable set of events (signal transitions) the selection based on the input signal level is not supported. We propose to eliminate this restriction incorporating conditional input bursts described below as well as the unconditional ones (the input burst defined in the previous section) to make input choices more flexible. A conditional input burst consists of a conditional clause, which restricts the validity of the input burst, and an input burst (as defined previously). Conditional clauses hs + i and hs, i denote if input signal s = and if input signal s = respectively. Thus, æ hs + ia + =x + denotes if s = whena + fires, then x + is enabled to fire. æ hs, ia + =y, denotes if s = whena + fires, then y, is enabled to fire. The signals specified in the conditional clause (called conditional signals) must be set up (environmental constraint)beforeany compulsory transition in the input burst fires in the same spirit as the data must be set up before the rising transition of the clock in the rising edge triggered D flip-flop. The setup time depends on the implementation. The hold time is satisfied by the fundamental mode environmental constraint. Unlike data signals in synchronous systems, conditional signals in the extended-burst-mode specifications must be set up monotonically. The conditional signals are treated as event signals elsewhere in the specification. We require that if an input burst in a state is conditional, all other input bursts in the same state are also conditional. Furthermore, we restrict the number of conditional signals per conditional clause to one. Recall that in the previous section we required that the polarities of the terminating transitions of a signal alternate. This alternating sequence is reset by a conditional clause containing the signal; thus the sequence starts anew following the conditional clause. A conditional signal may be specified as a directed-don t-care in the states immediately precedingthe conditional clause (the Done signal in figure 3 is an example of a directed-don t-care terminated by a conditional clause). In the original burst-mode specifications, we disallowed any input burst in a state from being a subset of another input burst in the same state to avoid ambiguity the subset restriction. A similar restriction called the distinguishability constraint exists for the extended-burst-mode. Let T min i be the set of compulsory transitions in the input burst T i and T max i be the set of all possible transitions in T i. The distinguishability constraint for the extendedburst-mode is: for every pair of input bursts i and j from the same state, either the conditional clauses are mutually exclusive, or T min i 6ç T max j. For instance, the input bursts from S in figure a are legal because s + and s, are mutually exclusive. However, the input bursts from S in figure c are illegal because the conditional clauses are not mutually exclusive and fb + gçfa + ;b + g. Likewise, the input bursts from S in figure b are illegal because the set of all possible transitions for the unconditional input burst a + b æ is fa + ;b + gand fb + gçfa + ;b + g. abxy = <s+> a+b+ / abxy = <s > b+ / a+b* / b+ /.3 Example abxy = <s+> a+b+ / (a) (b) (c) Figure : Distinguishability Constraints. <s+> b+ / We demonstrate the usefulness of the conditional input burst coupled with the directed-don t-cares, using the core of a controller

3 from the HP Post Office benchmark suite [7], sbuf-send-pkt, that manages the packet send protocol (see figure 3). First, we describe the protocol. Initially, the receiver requests the packet transfer by asserting Req. The sender then places a line of data on the bus and asserts SendLine. When the receiver receives the line, it acknowledges the sender by asserting AckLine; the sender, in turn, negates SendLine. The receiver normally negatesackline, terminating a line transfer cycle. This four-phase handshaking protocol continues until the receiver decides to terminate the packet transfer by asserting Done and negating AckLine concurrently after the sender negates SendLine. When the sender detects AckLine being negated, it placesa line on the bus and asserts SendLine. After the receiver acknowledges the final line transfer by asserting AckLine, the sender, having detected Done signal asserted (stable by this time), acknowledges the completion of packet transfer by asserting Ack and negating SendLine. The packet transfer is complete when the receiver negates Req, AckLine and Done and the sender, in turn, negates Ack. Req Ack SendLine AckLine Done Req AckLine Done / Ack Req+ Done* / SendLine+ <Done+> AckLine+ / SendLine Ack+ <Done > AckLine+ / SendLine 3 AckLine Done* / SendLine+ setup time Figure 3: Example (sbuf-send-pkt-core). It is impossible or awkward at best to specify the controller managing this protocol using existing specifications that can be automatically synthesized: burst-mode and free-choice STG. The difficulty stems from having to distinguish the concurrent transitions Done + AckLine, from AckLine, alone (note that fackline, gç fdone + ; AckLine, g). This controller cannot be specified in burst-mode without violating the subset restriction. The free-choice STG cannot model this behavior for the same reason. Although it is possible to specify this type of behavior using variations of currently accepted form of STG (free-choice STG), the resulting specification is difficult to understand and not always synthesizable. Chu suggested in chapter 8 of his thesis [5] the possibility of a structural extension of the free-choice STG called a controlled-choice STG. So far, there is no known synthesis tool that handles controlled-choice STGs. Moon et al. [4] proposed to allow a null or dummy transition to enhance the syntactic power of free-choice STGs. Here again, the existing synthesis tools have difficulty coping with a certain class of specifications with null transitions. SIS, for example, cannot handle the state encoding (for the specifications without the complete state coding property such as this controller) if the fanout of a null transition is a subset of the fanout of another null transition from the same place [8, ]. The extended-burst-mode specification handles this by treating Done as a conditional signal to be sampled by AckLine +. Since Done + may fire at any time (or not at all) after SendLine, fires, Done is specified as a directed-don t-care in S D Implementation A 3D asynchronous finite state machine [3, ] is a 4-tuple èx; Y; Z; æè where X is a set of primary input symbols, Y aset of primary output symbols, Z a (possibly empty) set of internal state variable symbols, and æ : X æ Y æ Z! Y æ Z a next-state function. The hardware implementation of the 3D state machine is a twolevel AND-OR network where outputs (and additional state variables when necessary) are fed back as inputs to the network. There are no explicit storage elements such as latches, flip-flops or C- elements in a 3D machine; only static feedback is used to maintain memory. The 3D implementation of the burst-mode specification is obtained from the 3-dimensional function map called the next-state table, a 3-dimensional tabular representation of the next-state function æ. The next-state of every reachable state must be specified; the remaining entries of the next-state table are considered don t-cares. The operation of the 3D state machine is similar to a Mealymode synchronous state machine. A machine cycle consists of 3 phases: input burst followed by output burst followed by state burst. During the idle state, the machine waits for an input burst to occur. The input burst may be conditional or unconditional. The conditional signal must be set up by some implementation dependent mininum delay before the first compulsory transition arrives. When the last terminating transition of the input burst arrives, an output burst takes place. The state burst, if required, immediately follows the output burst, completing the 3-phase machine cycle. The next set of compulsory transitions may not arrive until the machine is stabilized (fundamental-mode environmental assumption). 3. Next-state Table Generation We build the next-state table by assigning a next-state to each reachable state. If the (extended) burst-mode specification does not have a unique next-state code for each reachable state, new layers of the next-state table are added so that the final construction has the unique next-state codes. abc xy 3 abc = Req AckLine Done xy = SendLine Ack q = q = Figure 4: Next-state Table (sbuf-send-pkt-core). Example (sbuf-send-pkt-core) In S, the machine is idle waiting for the input burst a + c æ ; once a becomes (regardless of c), the output x changesmonotonically to. Thus the next xy entries for abcxy = x and xxare specified to be and respectively. When x stabilizes to, the machine is in S, where it awaits the conditional input burst hc, ib + or hc + ib +.Ifc remains until b + fires, the output x changes to, and the machine goes to S 3 (we defer discussing this path until later). On the other hand, if c goes to some setup time before b + fires, the outputs xy change to after b becomes, and the machine goes to S. The next xy for abcxy = is specified so that the outputs remain unchanged while the conditional signal is being set up; the next xy

4 for abcxy = xx are specified so that the outputs xy change monotonically to once enabled. The machine, in S, awaits the input burst a, b, c,.whenall the inputs change to, the output y changes to, and the machine is back in S. The next xy for abcxy = xx, xx and xx are specified to be because the outputs must remain unchanged until the final terminating transition of the input burst fires. The next xy for abcxy = is. Alternatively, supposec remains at when b + fires (the machine in S ). Once b goes to, x changes to, and the machine goes to S 3, and wait for the input burst b, c æ. The outputs xy must remain until the compulsory transition b, occurs. Attempting to specify the next xy for abcxy = to be, we run into a conflict because the next xy for abcxy = had already been specified (during S! S ). In this case, we back up to the state following the last output burst (abcxy = ) and change the internal state (state burst q + ) as shown in figure 4. When the state variable q stabilizes to, the machine is in state S 3. In S 3, the machine waits for the input burst b, c æ. becomes (regardless of the state of c), x goes to. When b Once x becomes, state variable q goes to, and the machine returns to S. The next xy for abcxy = x (in layer q = ) are specified so that the outputs xy remain unchanged until the compulsory transition b, fires. The next xy for abcxy = xx are specified so that x changes monotonically to once enabled. Note that c + may fire at any time before b + fires in S or may not fire at all. 3. Eliminating Hazards 3.. Eliminating Sequential Hazards If a transition between layers (state burst) requires multiple state bit changes, the machine traverses intermediate layers before it settles down at the final layer. In 3D machines, a critical race is present if the transient states during a layer transition have different nextstates from the final-stable-state. We insure that the machine is free of critical races by encoding layers so that no input or output burst intersects the transient states of layer transitions and by forcing all transient states during a layer transition to have the same next-states as the final-stable-state. 3.. Eliminating Combinational Hazards We can classify all hazards in combinational circuits into two categories: function hazards and logic hazards. Function hazards are due to an incorrectly specified function during multiple-input changes. Logic hazards arise due to delay variations of the physical gates and wires [3, 7, 8, ] despite the correct function. In 3D machines, we preclude the presence of function hazards by correctly specifying the next-state of every reachable state [3]. The requirements to insure hazard-free combinational logic are presented in [3, 8]. Initially, we assume that all input bursts are unconditional. In 3D machines, the outputs change in response to the input bursts and remain constant while the fed-back outputs and state variables change. Likewise, the state variables change due to the output bursts and remain constant while the fed-back state variables change. Assuming sufficient delays in the feedback paths for outputs and state variables, we can disregard the interactions between inputs and feedback variables (i.e., there are no essential hazards [3]). 3 We can then view each burst (input, output or state) as a multiple-input change to the output combinational logic. The outputs are assumed to be stable before and after each burst. The (extended) burst-mode specifications mandate that outputs remain unchanged until the last (terminating) input transitions of the input burst. The 3D implementation enforces the same rule on In a sequential network, feedback variables as well as primary inputs must be considered as inputs to the network. In some cases, due to the input burst if the trailing output burst is an empty set. 3 In 3D machines, we minimize the feedback delays with a simple set of one-sided timing constraints [3]. the state variables the state variables remain unchanged until the last output transition of the output burst (note that every output and state variable transition is compulsory). The set of states (defined by input, output and state bit vectors) before and after the final terminating transition are called the initial-region and final-region. The outputs remain at the levels before the burst in the initial-region and change to the levels specified by the output burst in the finalregion. The on-set and off-set of an output are then unions of some initial-regions and final-regions. To avoid static logic hazards during multiple-input changes in the two-level AND-OR network implementing an output function [3, 8, 3], we require that: æ If the output is specified to be in both the initial- and finalregion, a single cube must contain both the initial- and finalregion. æ If the output is specified to be only in the initial-region or only in the final-region, the on-set region must be covered by a set of maximal cubes, which in effect forces a single input change going from the initial-region to the final-region. In order to discuss eliminating dynamic logic hazards, we need to define some terminology. Definition Stable-states: æ The initial-stable-state of a burst is the state of the machine before the burst with each input, output and state variable at the level following the last terminating transition before the currentburst (directed-don t-caresare assumed not changed). æ The final-stable-state of a burst is the state of the machine after all the terminating transitions in the burst have fired, with every directed-don t-care input at the level following the ensuing terminating transition. Definition 3 Transient-states: æ The initial-transient-states of a burst are the states traversed during the burst preceding the last terminating transition of the burst (excluding the initial-stable-state). æ The final-transient-states of a burst are the states traversed during the burst following the last terminating transition of the burst (excluding the final-stable-state). a+b* / Final transient state a+ b+ b+ a+ Initial Initial Final stable transient stable state state state Input Burst Initial stable state b+ Final transient state Figure 5: Stable / Transient States. Initial transient states Final stable state Consider an input burst a + b æ in figure 5. The last terminating transition of b preceding this input burst and the next terminating transition of b following this input burst are assumed to be b, and b + respectively. In this example, the initial-stable-state and final-stable-state of the input burst are ab = and ab = ; the Output Burst

5 initial-transient-state and final-transient-state of the input burst are ab = and ab =. Even if the requirements to avoid static logic hazards were met, the output logic may still exhibit glitches during dynamic transitions, in particular, if a stray on-set cube intersects an initialtransient-state during the, transition of an output. This is because the stray cube may glitch (,,) and the glitch may propagate to the output (,,, dynamic hazard) [3, 7]. Likewise, if a stray on-set cube intersects a final-transient-state during the, transition of an output, the stray cube may glitch (,,) and the glitch may propagate to the output (,,, dynamic hazard) [8]. The following is a summary of the on-set covering requirements for output logic during the unconditional input bursts.. For a, transition of output: The input burst must be covered by a single cube; the output burst must be covered by a single cube.. For a, transition of output: The output burst must be covered by a single cube. Any on-set cube that intersects any final-transient-state of an input burst must also include the final-stable-state of the input burst if the input burst enables a, transition of the output. 3. For a, transition of output: The input burst containing n c terminating transitions must be covered by n c cubes each of which contains exactly one literal corresponding to a unique terminating input in the input burst and does not contain any literal corresponding to a directeddon t-care. Any on-set cube that intersects the initial-transient-states of an input burst must also include the initial-stable-state of the input burst if the input burst enables a, transition of an output. The on-set covering requirements for output logic during the output and state bursts is the same as the requirement above. A similar set of on-set covering requirements exist for state logic. The covering requirements for the example (sbuf-send-pkt-core) is shown in figure 6. abc = Req AckLine Done xy = SendLine Ack abc xy abc xy q = q = Next x = a b y Next y = a y + b y + c y + q b c Figure 6: Covering Requirements (sbuf-send-pkt-core). Now let us consider conditional input bursts, hs + it and hs, it, emanating from a state. Recall that the conditional signal s must be set up before every compulsory transition of both T and T. For the path in which the conditional signal requires no transition, say hs, it with no loss of generality, the covering requirement is the same as that of the unconditional one. For the path hs + it, we can divide the burst into two parts (or bursts): () the set of all non-compulsory transitions (including s + )and()the unconditional part of the burst, T in this case. In the first burst, the outputs remain constant (, or, transition). In the second burst, the outputs change to the specified values after the last terminating transition of T. Since the first burst always includes the transition of a conditional signal and the conditional signal is set up before the compulsory transitions of T and T, the product terms that cover the second burst always turn on before the first burst cover turns off for a, transition of an output no,, static hazard. Figure 7 shows the covering requirements. The smallest on-set cubes used to satisfy the hazard-free covering requirements discussed above are called required cubes [8]. An on-set cover for a logic function is a set of cubes such that every cube covers a minterm but not off-set vertex and every minterm is covered by at least one cube in the cover. A logic hazard is present in an implementation if there exists a required cube not contained in any cube in the cover. The required cover for a logic function is a set of required cubes D Automatic Synthesis 3.3. Definitions A 3D next-state table is said to have the unique next-state code (UNC) property iff every entry in the table has a unique next-state. A next-state table with the UNC property has the proper unique next-state code (PUNC) property iff every required cube for every output or state variable logic, that intersects an initial-transientstate of a burst enabling a, transition of an output or a state variable, also contains the initial-stable-state of the burst. Note the asymmetry between the, and, transition of outputs. It is impossible for a required cube to intersect a finaltransient-state of an input burst enabling a, transition of an output without actually being a subset of the required cube covering the output burst. However, it is entirely possible for a required cube to intersect an initial-transient-state of an input burst. This is because the next-states of final-transient-states (for the, transition of output) are different from the current states, but the next-states of initial-transient-states are the same as the current states Procedure The synthesis procedure is described in []. We build a nextstate table from a specification so that the final 3D construction satisfies the PUNC property and assign codes to the layers of the next-state table in a critical-race-free manner. We then generate an unminimized hazard-free cover for each output and state variable function by ORing required on-set cover of every burst. Logic minimization is performed using exact algorithms for hazard-free logic, implemented in an automated logic minimizer [8]. 4 Experimental Results The synthesis procedure is completely automated (coded in C). We have conducted numerous experiments for both the original burstmode and the extended-burst-mode specifications. The synthesis tool produces efficient results in terms of both the area and the latency. The latency is a delay from the last input transition of an input burst to the last transition of the resultant output burst. The cycle time is the minimum delay (environmental constraint) from the last input transition of an input burst to the first input transition of the next input burst. Experimental results for some extendedburst-mode specifications are shown in table. The latencies and the cycle times are evaluated using a.8çm CMOS standard cell library, developed for the Verilog simulator by the Torch group at Stanford University []. The library cells were characterized using the SPICE simulator under military worst-case conditions (4.5V power supply, 5 æ C) and derated for the nominal case (5V, 5 æ C). 5 Conclusions We described two extensions to the burst-mode specifications to allow more concurrency and to make input choices more flexible. The notions of directed-don t-care and conditional input burst were introduced. We analyzed the impacts of these extensions on the hazard-free implementation of the 3D machine and its synthesis

6 abx = <s+> a+b+ / <s > a+ / x abx = <s+> a+b* / <s > a*b+ / x abx = <s+> a+b+ / <s > a+b+ / x s = s = xab S S S S (a) ab s = s = x S S S S (b) Figure 7: Covering Requirements (Conditional Input Bursts). ab s = s = x S S S S (c) Specification Implementation States / Primary State Product Terms Literals Cycle Transitions In Out Vars Output Total Output Total Latency Time D-FF ns.3ns pe-rcv-ifc ns 3.8ns ram-read-sbuf ns.7ns sbuf-ram-write ns 3.ns sbuf-send-pkt ns 3.5ns Table : Experimental Results. procedure. Finally, we performed experiments on 5 new examples (4 from HP Post Office suite), all of which feature one or both of the extensions, using the modified 3D synthesis tool. The performance numbers are consistent with the examples of comparable complexity (not requiring the extensions). In the future, we plan to develop major examples featuring these extensions. Acknowledgement The authors would like to thank Bill Coates of HP Labs and Luciano Lavagno of UC Berkeley for many stimulating discussions. References [] V. Akella and G. Gopalakrishnan. SHILPA: A high-level synthesis system for self-timed circuits. In ICCAD-9. [] P. Beerel and T. Meng. Automatic gate-level synthesis of speed-independent circuits. In ICCAD-9. [3] Jon G. Bredeson and Paul T. Hulina. Elimination of static and dynamic hazards for multiple inputchanges in combinationalswitching circuits. Information and Control, :4 4, 97. [4] E. Brunvand and R. F. Sproull. Translating concurrent programs into delayinsensitive circuits. In ICCAD-89. [5] T.-A. Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. Technical Report MIT-LCS-TR-393, 987. [6] T.-A. Chu. Automatic synthesis and verification of hazard-free control circuits from asynchronousfinite state machines. In ICCD-9. [7] A. Davis, W. Coates, and K. Stevens. The Post Office experience: designing a large asynchronous chip. In 993 Hawaii International Conference on Systems Science. [8] Luciano Lavagno, 99. Private communication. [] A. J. Martin. Programming in VLSI: From communicating processes to delayinsensitive VLSI circuits. In C. A. R. Hoare, editor, UT Year of Programming Institute on Concurrent Programming, Addison-Wesley, 99. [3] Teresa H.-Y. Meng. Synchronization Design for Digital Systems. Kluwer Academic, 99. [4] C. W. Moon, P. R. Stephan, and R. K. Brayton. Specification, synthesis, and verification of hazard-free asynchronous circuits. In ICCAD-9. [5] C. Myers and T. Meng. Synthesis of timed asynchronouscircuits. In ICCD-9. [6] S. Nowick, M. Dean, D. Dill, and M. Horowitz.The design of a high-performance cache controller: a case study in asynchronous synthesis. In 993 Hawaii International Conference on Systems Science. [7] S. M. Nowick and D. L. Dill. Synthesis of asynchronousstate machines using a local clock. In ICCD-9. [8] S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-freelogic with multiple-input changes. In ICCAD-9. [9] S. M. Nowick, K. Y. Yun, and D. L. Dill. Practical asynchronous controller design. In ICCD-9. [] S. H. Unger. Asynchronous Sequential Switching Circuits. New York: Wiley- Interscience, 969. [] P. Vanbekbergen,F. Catthoor, G. Goossens and H. De Man. Optimized synthesis of asynchronouscontrolcircuits from graph-theoretic specifications. In ICCAD- 9. [] Kenneth Y. Yun and David L. Dill. Automatic synthesis of 3D asynchronous state machines. In ICCAD-9. [3] K. Y. Yun, D. L. Dill, and S. M. Nowick. Synthesis of 3D asynchronous state machines. In ICCD-9. [9] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli. Algorithms for synthesis of hazard-free asynchronouscircuits. In DAC-9. [] L.Lavagno,C. Moon,R. Brayton,A. Sangiovanni-Vincentelli. Solving the state assignment problem for signal transition graphs. In DAC-9. [] J. Maneatis and D. Ramsey, 99. Private communication.