Outline. CPE/EE 422/522 Advanced Logic Design L04. Review: 8421 BCD to Excess3 BCD Code Converter. Review: Mealy Sequential Networks

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1 Outline PE/EE 422/522 Advanced Logic Design L4 Electrical and omputer Engineering University of Alabama in Huntsville What we know ombinational Networks Analysis, Synthesis, Simplification, Hazards, Building Blocks, PALs, PLAs, ROMs Sequential Networks: Basic Building Blocks Design: Mealy Setup and hold times, Max clock frequency What we do not know Design: Moore Equivalent States State Table Reduction Intro to VHDL 9/6/23 UAH-PE/EE 422/522 AM 2 Review: Mealy Sequential Networks General model of Mealy Sequential Network () X inputs are changed to a new value (2) After a delay, the Z outputs and next state appear at the output of M (3) The next state is clocked into the state register and the state changes x Review: 842 BD to Excess3 BD ode onverter Q z t3 X (inputs) t2 t t t3 Z (outputs) t2 t t 9/6/23 UAH-PE/EE 422/522 AM 3 9/6/23 UAH-PE/EE 422/522 AM 4 Sequential Network Timing (cont d) Timing diagram assuming a propagation delay of ns for each flip-flop and gate (State has been replaced with the state of three flip-flops) Setup and Hold Times For a real D-FF D input must be stable for a certain amount of time before the active edge of clock cycle => Setup time D input must be stable for a certain amount of time after the active edge of the clock => Hold time Propagation time: from the time the clock changes to the time the output changes Manufacturers provide minimum tsu, th, and maximum tplh, tphl 9/6/23 UAH-PE/EE 422/522 AM 5 9/6/23 UAH-PE/EE 422/522 AM 6

2 tc max tp max tck tc max Maximum lock Frequency - Max propagation delay through the combinational network - Max propagation delay from the time the clock changes to the flip-flop output changes { = max(tplh, tphl)} - lock period + t p max tck tsu t ck t c max + t p max + t su Example: t p max = 5 ns, t su t gate = 5 ns t ck f max = 5 ns, = 2 * = 5 ns = = 2 MHz 5 ns 9/6/23 UAH-PE/EE 422/522 AM 7 Hold Time Violation Occur if the change in Q fed back through the combinational network and cause D to change too soon after the clock edge Hold time is satisfied if: t p min + t c min What about X? t h Make sure that input changes propagate to the flip-flops inputs such that setup time is satisfied. t x t cx max + t su Make sure that X does not change too soon after the clock. If X changes at time ty after the active edge, hold time is satisfied if ty th tcx min 9/6/23 UAH-PE/EE 422/522 AM 8 Moore Sequential Networks Outputs depend only on present state! General Model of Moore Sequential Machine Outputs depend only on present state! x x 2 X = x x 2... x n Q = Q Q 2... Q k Z = z z 2... z m Q z z 2 Inputs(X) ombinational Network Next State lock State Register ombinational Network State(Q) Outputs(Z) x n z m Z ( t ) = + Q ( t ) = F( Q ( t )) G ( X ( t ), Q ( t )) X = x x 2... x n + Q ( t ) = G ( X ( t ), Q ( t )) Q = Q Q 2... Q k Z ( t ) = F( Q ( t )) Z = z z 2... z m 9/6/23 UAH-PE/EE 422/522 AM 9 9/6/23 UAH-PE/EE 422/522 AM ode onverter: Moore Machine ode onverter: Moore Machine S S S3 Start S S3 Start S S S Do we need state S? How many states does Moore machine have? How many states does Mealy machine have? 9/6/23 UAH-PE/EE 422/522 AM 9/6/23 UAH-PE/EE 422/522 AM 2 2

3 Moore Machine: State Table Moore Machine Timing Start S X = _ => Z = _ PS S S S3 S X= S S3 S S S NS X= S S - Z S S3 S Note: state S could be eliminated (S == ), if was start state! Moore Mealy 9/6/23 UAH-PE/EE 422/522 AM 3 9/6/23 UAH-PE/EE 422/522 AM 4 State Assignments Moore Machine: Another Example Guidelines to reduce the amount of combinational logic Rule I: (S,, S), (, ), (, ) Rule II: (S, ), (S3, ), (, ), (, ), (, ), (, S) Rule III: (S,,,,, ) (S, S3,,, S) QQ2 S S -. S - Q3Q4 s S S3 PS S S S3 S NS X= X= S S3 S S S - S S Z A onverter for Serial Data Transmission: NRZ-to-Manchester oding schemes for serial data transmission NRZ: nonreturn-to-zero NRZI: nonreturn-to-zero-inverted in input sequence the bit transmitted is the same as the previous bit; in input sequence transmit the complement of the previous bit RZ: return-to-zero for full bit time; for the first half, for the second half Manchester S 9/6/23 UAH-PE/EE 422/522 AM 5 9/6/23 UAH-PE/EE 422/522 AM 6 Moore Network for NRZ-to-Manchester Moore Network for NRZ-to-Manchester 9/6/23 UAH-PE/EE 422/522 AM 7 9/6/23 UAH-PE/EE 422/522 AM 8 3

+ Synchronous Design Use a clock to synchronize the operation of all flip-flops, registers, and counters in the system all changes occur immediately following the active clock edge clock period must

4 + Synchronous Design Use a clock to synchronize the operation of all flip-flops, registers, and counters in the system all changes occur immediately following the active clock edge clock period must be long enough so that all changes flip-flops, registers, counters will have time to stabilize before the next active clock edge Typical design: ontrol section + Data Section Sequential machine to generate control signals to control the operation of data section Data registers Arithmetic Units ounters Buses, Muxes, Data section // s= n*(n+a) // R=n, R2=a // R=s Design flowchart for SMUL operation Design ontrol section S S F B B B + BR A + B An Example LD(BR) DE(BR) 6 ld dec LD(R) RD(R) 6 BR rd ld rd LD(L) L(L) RD(BR) 6 R ld cl LD(A) 6 ld 6 L A 6 F 5.. ALU F 6 A ld LD(R2) R2 rd RD(R2) 6 6 B S S 6 rd RD(A) cl L(A) 9/6/23 UAH-PE/EE 422/522 AM 9 9/6/23 UAH-PE/EE 422/522 AM 2 Timing hart for System with Falling-edge Devices Timing hart for System with Rising-edge Devices 9/6/23 UAH-PE/EE 422/522 AM 2 9/6/23 UAH-PE/EE 422/522 AM 22 Method Principles of Synchronous Design All clock inputs to flip-flops, registers, counters, etc., are driven directly from the system clock or from the clock ANDed with a control signal Result All state changes occur immediately following the active edge of the clock signal Advantage All switching transients, switching noise, etc., occur between the clock pulses and have no effect on system performance Asynchronous Design Disadvantage - More difficult Problems Race conditions: final state depends on the order in which variables change Hazards Special design techniques are needed to cope with races and hazards Advantages = Disadvantages of Synchronous Design In high-speed synchronous design propagation delay in wiring is significant => clock signal must be carefully routed so that it reaches all devices at essentially same time Inputs are not synchronous with the clock need for synchronizers lock cycle is determined by the worst-case delay 9/6/23 UAH-PE/EE 422/522 AM 23 9/6/23 UAH-PE/EE 422/522 AM 24 4

5 Read To Do Textbook chapters.6,.7,.8,.,.,.2 Equivalent States Two state are equivalent if we cannot tell them apart by observing input and output sequences Definition: Two states are equivalent si==sj only and only if, for every input sequence X, the output sequences Zand Z2 are the same. Not practical => try all sequences (what is the length of sequence?) 9/6/23 UAH-PE/EE 422/522 AM 25 9/6/23 UAH-PE/EE 422/522 AM 26 Equivalent States State Table Reduction State Equivalence Theorem Two state are equivalent Si == Sj if and only if for every single input X, the outputs are the same and the next states are equivalent ) States a and h have the same next states and outputs (when X= and X=) 2) Eliminate h from the table and replace with a 3) States a and b have the same output => they are same iff c==d and f==e. We say c-d and e-f are implied pairs for a-b. To keep track of the implied pairs we make an implication chart. 9/6/23 UAH-PE/EE 422/522 AM 27 9/6/23 UAH-PE/EE 422/522 AM 28 State Table Reduction State Table Reduction 4) Make another pass through the chart. E-g cell contains c-e and b-g; since c-e cell contains x, c!=e => e!=g (put X). 5) Repeat the step 4 until no additional squares are X-ed. {Put X in f-g, a-c, a-d, b-c, b-d squares}. 6) The remaining squares indicate equivalent state pairs => a==b, c==d, e==f. 9/6/23 UAH-PE/EE 422/522 AM 29 9/6/23 UAH-PE/EE 422/522 AM 3 5

6 Implication Table Method. onstruct a chart that contains a square for each pair of states. 2. ompare each pair in the state table. If the outputs associated with states i and j are different, place an X in square i-j to indicate that i!=j. If outputs are the same, place the implied pairs in square i-j. If outputs and next states are the same (or i-j implies only itself), i==j. 3. Go through the implication table square by square. If square i-j contains the implied pair m-n, and square m-n contains X, then i!=j, and place X in square i-j. 4. If any Xs were added in step 3, repeat step 3 until no more Xs are added. 5. For each square i-j that does not contain an X, i==j. Intro to VHDL Technology trends billion transistor chip running at 2 GHz in 27 Need for Hardware Description Languages Systems become more complex Design at the gate and flip-flop level becomes very tedious and time consuming HDLs allow Design and debugging at a higher level before conversion to the gate and flip-flop level Tools for synthesis do the conversion VHDL, Verilog VHDL VHSI Hardware Description Language 9/6/23 UAH-PE/EE 422/522 AM 3 9/6/23 UAH-PE/EE 422/522 AM 32 Intro to VHDL Developed originally by DARPA for specifying digital systems International IEEE standard (IEEE ) Hardware Description, Simulation, Synthesis Provides a mechanism for digital design and reusable design documentation Support different description levels Structural (specifying interconnections of the gates), Dataflow (specifying logic equations), and Behavioral (specifying behavior) Top-down, Technology Dependent 9/6/23 UAH-PE/EE 422/522 AM 33 VHDL Description of ombinational Networks 9/6/23 UAH-PE/EE 422/522 AM 34 Entity-Architecture Pair VHDL Program Structure Full Adder Example 9/6/23 UAH-PE/EE 422/522 AM 35 9/6/23 UAH-PE/EE 422/522 AM 36 6

4-bit Adder 4-bit Adder (cont d) 9/6/23 UAH-PE/EE 422/522 AM 37 9/6/23 UAH-PE/EE 422/522 AM 38 4-bit Adder - Simulation Modeling Flip-Flops Using VHDL Processes General form of process Whenever one

7 4-bit Adder 4-bit Adder (cont d) 9/6/23 UAH-PE/EE 422/522 AM 37 9/6/23 UAH-PE/EE 422/522 AM 38 4-bit Adder - Simulation Modeling Flip-Flops Using VHDL Processes General form of process Whenever one of the signals in the sensitivity list changes, the sequential statements are executed in sequence one time 9/6/23 UAH-PE/EE 422/522 AM 39 9/6/23 UAH-PE/EE 422/522 AM 4 oncurrent Statements vs. Process A, B,, D are integers A=, B=2, =3, D= D changes to 4 at time D Flip-flop Model Bit values are enclosed in single quotes time delta A B D (stat. 3 exe.) (stat. 2 exe.) (stat. exe.) (no exec.) Simulation Results 9/6/23 UAH-PE/EE 422/522 AM 4 9/6/23 UAH-PE/EE 422/522 AM 42 7

8 JK Flip-Flop Model JK Flip-Flop Model 9/6/23 UAH-PE/EE 422/522 AM 43 9/6/23 UAH-PE/EE 422/522 AM 44 Using Nested IFsand ELSEIFs VHDL Models for a MUX Sel represents the integer equivalent of a 2-bit binary number with bits A and B If a MUX model is used inside a process, the MUX can be modeled using a ASE statement (cannot use a concurrent statement): 9/6/23 UAH-PE/EE 422/522 AM 45 9/6/23 UAH-PE/EE 422/522 AM 46 MUX Models () MUX Models (2) library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_unsigned.all; entity SELETOR is port ( A : in std_logic_vector(5 downto ); SEL : in std_logic_vector( 3 downto ); Y : out std_logic); end SELETOR; architecture RTL of SELETOR is p : process (A, SEL) if (SEL = "") then Y <= A(); elsif (SEL = "") then Y <= A(); elsif (SEL = "") then Y <= A(2); elsif (SEL = "") then Y <= A(3); elsif (SEL = "") then Y <= A(4); elsif (SEL = "") then Y <= A(5); elsif (SEL = "") then Y <= A(6); elsif (SEL = "") then Y <= A(7); elsif (SEL = "") then Y <= A(8); elsif (SEL = "") then Y <= A(9); elsif (SEL = "") then Y <= A(); elsif (SEL = "") then Y <= A(); elsif (SEL = "") then Y <= A(2); elsif (SEL = "") then Y <= A(3); elsif (SEL = "") then Y <= A(4); else Y <= A(5); end if; end process; end RTL; library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_unsigned.all; entity SELETOR is port ( A : in std_logic_vector(5 downto ); SEL : in std_logic_vector( 3 downto ); Y : out std_logic); end SELETOR; architecture RTL3 of SELETOR is with SEL select Y <= A() when "", A() when "", A(2) when "", A(3) when "", A(4) when "", A(5) when "", A(6) when "", A(7) when "", A(8) when "", A(9) when "", A() when "", A() when "", A(2) when "", A(3) when "", A(4) when "", A(5) when others; end RTL3; 9/6/23 UAH-PE/EE 422/522 AM 47 9/6/23 UAH-PE/EE 422/522 AM 48 8

9 MUX Models (3) MUX Models (4) library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_unsigned.all; entity SELETOR is port ( A : in std_logic_vector(5 downto ); SEL : in std_logic_vector( 3 downto ); Y : out std_logic); end SELETOR; architecture RTL2 of SELETOR is p : process (A, SEL) case SEL is when "" => Y <= A(); when "" => Y <= A(); when "" => Y <= A(2); when "" => Y <= A(3); when "" => Y <= A(4); when "" => Y <= A(5); when "" => Y <= A(6); when "" => Y <= A(7); when "" => Y <= A(8); when "" => Y <= A(9); when "" => Y <= A(); when "" => Y <= A(); when "" => Y <= A(2); when "" => Y <= A(3); when "" => Y <= A(4); when others => Y <= A(5); end case; end process; end RTL2; library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_unsigned.all; entity SELETOR is port ( A : in std_logic_vector(5 downto ); SEL : in std_logic_vector( 3 downto ); Y : out std_logic); end SELETOR; architecture RTL4 of SELETOR is Y <= A( conv_integer(sel)); end RTL4; 9/6/23 UAH-PE/EE 422/522 AM 49 9/6/23 UAH-PE/EE 422/522 AM 5 9

Outline. CPE/EE 422/522 Advanced Logic Design L03. Review: Clocked D Flip-Flop with Rising-edge Trigger. Sequential Networks

Outline. CPE/EE 422/522 Advanced Logic Design L03. Review: Clocked D Flip-Flop with Rising-edge Trigger. Sequential Networks Outline PE/EE 422/522 Advanced Logic Design L3 Electrical and omputer Engineering University of Alabama in Huntsville What we know ombinational Networks Analysis, Synthesis, Simplification, Buiing Blocks,