Chapter 5 Sequential Circuits
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1 Logic and omputer esign Fundamentals hapter 5 Sequential ircuits Part - Storage Elements Part Storage Elements and Sequential ircuit Analysis harles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)
2 Overview Part - Storage Elements Introduction to sequential circuits Types of sequential circuits Storage elements Latches Flip-flops Part 2 - Sequential ircuit Analysis Part 3 - Sequential ircuit esign Part 4 State Machine esign hapter 5 - Part 2
3 Introduction to Sequential ircuits A Sequential circuit contains: Storage elements: Latches or Flip-Flops ombinational Logic: Inputs Storage Elements State Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements. ombinational Logic Next State Outputs hapter 5 - Part 3
4 Introduction to Sequential ircuits ombinatorial Logic Next state function Next State = f(inputs, State) Output function (Mealy) Outputs = g(inputs, State) Output function (Moore) Outputs = h(state) Inputs Storage Elements State ombinational Logic Next State Output function type depends on specification and affects the design significantly Outputs hapter 5 - Part 4
5 Types of Sequential ircuits epends on the times at which: storage elements observe their inputs, and storage elements change their state Synchronous Behavior defined from knowledge of its signals at discrete instances of time Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock) Asynchronous Behavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change Nevertheless, the synchronous abstraction makes complex designs tractable! hapter 5 - Part 5
6 Basic (NAN) S R Latch ross-oupling two NAN gates gives the S -R Latch: Which has the time sequence behavior: S =, R = is forbidden as input pattern Time S (set) R (reset) R S omment?? Stored state unknown Set to Now remembers Reset to Now remembers Both go high?? Unstable! hapter 5 - Part 6
7 Basic (NOR) S R Latch ross-coupling two NOR gates gives the S R Latch: Which has the time sequence Time behavior: R (reset) S (set) R S omment?? Stored state unknown Set to Now remembers Reset to Now remembers Both go low?? Unstable! hapter 5 - Part 7
8 locked S - R Latch Adding two NAN gates to the basic S - R NAN latch gives the clocked S R latch: S R Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line is high. means control or clock. hapter 5 - Part 8
9 locked S - R Latch (continued) The locked S-R Latch can be described by a table: S R The table describes what happens after the clock [at time (t+)] based on: current inputs (S,R) and current state (t). (t) S R (t+) omment No change lear Set??? Indeterminate No change lear Set??? Indeterminate hapter 5 - Part 9
10 locked S - R Latch Example LOK S R hapter 5 - Part
11 locked S - R Latch Example LOK S R hapter 5 - Part
12 locked S - R Latch Example 2 LOK S R hapter 5 - Part 2
13 locked S - R Latch Example 2 LOK S R hapter 5 - Part 3
14 Latch Adding an inverter to the S-R Latch, gives the Latch: Note that there are no indeterminate states! (t+) omment No change Set lear No hange The graphic symbol for a Latch is: hapter 5 - Part 4
15 Latch Example LOK hapter 5 - Part 5
16 Latch Example LOK hapter 5 - Part 6
17 Latch Example 2 LOK hapter 5 - Part 7
18 Latch Example 2 LOK hapter 5 - Part 8
19 Flip-Flops The latch timing problem Master-slave flip-flop Edge-triggered flip-flop Standard symbols for storage elements irect inputs to flip-flops hapter 5 - Part 9
20 The Latch Timing Problem In a sequential circuit, paths may exist through combinational logic: From one storage element to another From a storage element back to the same storage element The combinational logic between a latch output and a latch input may be as simple as an interconnect For a clocked -latch, the output depends on the input whenever the clock input has value hapter 5 - Part 2
21 The Latch Timing Problem (continued) onsider the following circuit: Y Suppose that initially Y =. lock Y lock As long as =, the value of Y continues to change! The changes are based on the delay present on the loop through the connection from Y back to Y. This behavior is clearly unacceptable. esired behavior: Y changes only once per clock pulse hapter 5 - Part 2
22 The Latch Timing Problem (continued) A solution to the latch timing problem is to break the closed path from Y to Y within the storage element The commonly-used, path-breaking solutions replace the clocked -latch with: a master-slave flip-flop an edge-triggered flip-flop hapter 5 - Part 22
23 S-R Master-Slave Flip-Flop onsists of two clocked S-R latches in series with the clock on the second latch inverted The input is observed by the first latch with = The output is changed by the second latch with = The path from input to output is broken by the difference in clocking values ( = and = ). The behavior demonstrated by the example with driven by Y given previously is prevented since the clock must change from to before a change in Y based on can occur. S R S R S R hapter 5 - Part 23
24 S-R Master-Slave Flip-Flop Example LOK S R 2 hapter 5 - Part 24
25 S-R Master-Slave Flip-Flop Example M M M M LOK S S S S S R 2 hapter 5 - Part 25
26 S-R Master-Slave Flip-Flop Example 2 LOK S R 2 hapter 5 - Part 26
27 S-R Master-Slave Flip-Flop Example 2 M M M M LOK S S S S S R 2 hapter 5 - Part 27
28 Flip-Flop Solution Use edge-triggering instead of master-slave An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal Edge-triggered flip-flops can be built directly at the electronic circuit level, or A master-slave flip-flop which also exhibits edge-triggered behavior can be used. hapter 5 - Part 28
29 Edge-Triggered Flip-Flop The edge-triggered flip-flop is the same as the masterslave flip-flop S R It can be formed by: Replacing the first clocked S-R latch with a clocked latch or Adding a input and inverter to a master-slave S-R flip-flop The delay of the S-R master-slave flip-flop can be avoided since the s-catching behavior is not present with replacing S and R inputs The change of the flip-flop output is associated with the negative edge (falling edge) at the end of the pulse It is called a negative-edge triggered flip-flop hapter 5 - Part 29
30 Edge-Triggered Flip-Flop Example LOK hapter 5 - Part 3
31 Edge-Triggered Flip-Flop Example M M M M LOK S S S S hapter 5 - Part 3
32 Edge-Triggered Flip-Flop Example 2 LOK hapter 5 - Part 32
33 Edge-Triggered Flip-Flop Example 2 M M M M LOK S S S S hapter 5 - Part 33
34 Positive-Edge Triggered Flip-Flop Formed by adding inverter to clock input S R changes to the value on applied at the positive clock (rising edge) edge within timing constraints to be specified Our choice as the standard flip-flop for most sequential circuits hapter 5 - Part 34
35 Positive-Edge Triggered Flip-Flop Example LOK hapter 5 - Part 35
36 Positive-Edge Triggered Flip-Flop Example LOK S S S S M M M M hapter 5 - Part 36
37 Standard Symbols for Storage Elements S S R R Master-Slave: Postponed output indicators S SR S SR with ontrol (a) Latches with ontrol R R Edge-Triggered: ynamic indicator Triggered SR Triggered SR Triggered (b) Master-Slave Flip-Flops Triggered Triggered Triggered (c) Edge-Triggered Flip-Flops hapter 5 - Part 37
38 irect Inputs At power up or at reset, all or part of a sequential circuit usually is initialized to a known state before it begins operation This initialization is often done outside of the clocked behavior of the circuit, i.e., asynchronously. irect R and/or S inputs that control the state of the latches within the flip-flops are used for this initialization. For the example flip-flop shown applied to R resets the flip-flop to the state applied to S sets the flip-flop to the state S R hapter 5 - Part 38
39 Other Flip-Flop Types J-K and T flip-flops Behavior Implementation Basic descriptors for understanding and using different flip-flop types haracteristic tables haracteristic equations Excitation tables For actual use, see Reading Supplement - esign and Analysis Using J-K and T Flip-Flops hapter 5 - Part 39
40 J-K Flip-flop Behavior Same as S-R flip-flop with J analogous to S and K analogous to R Except that J = K = is allowed, and For J = K =, the flip-flop changes to the opposite state As a master-slave, has same s catching behavior as S-R flip-flop If the master changes to the wrong state, that state will be passed to the slave E.g., if master falsely set by J =, K = cannot reset it during the current clock cycle hapter 5 - Part 4
41 J-K Flip-flop (continued) Small Glitch The small glitch in J propagates through the flipflop even though it is small. This is due to the fact that the JK has the s catching problem. hapter 5 - Part 4
42 J-K Flip-flop (continued) Implementation To avoid s catching behavior, one solution used is to use an edge-triggered as the core of the flip-flop Symbol J K J K hapter 5 - Part 42
43 J-K Flip-flop (continued) J? K K J J K (t+) = J + K J K hapter 5 - Part 43
44 T Flip-flop Behavior Has a single input T For T =, no change to state For T =, changes to opposite state Same as a J-K flip-flop with J = K = T As a master-slave, has same s catching behavior as J-K flip-flop annot be initialized to a known state using the T input Reset (asynchronous or synchronous) essential hapter 5 - Part 44
45 T Flip-flop (continued) Implementation To avoid s catching behavior, one solution used is to use an edge-triggered as the core of the flip-flop Symbol T T hapter 5 - Part 45
46 T Flip-flop (continued) T? T T (t+) T = T hapter 5 - Part 46
47 Basic Flip-Flop escriptors Used in analysis haracteristic table - defines the next state of the flip-flop in terms of flip-flop inputs and current state haracteristic equation - defines the next state of the flip-flop as a Boolean function of the flip-flop inputs and the current state Used in design Excitation table - defines the flip-flop input variable values as function of the current state and next state hapter 5 - Part 47
48 Flip-Flop escriptors haracteristic Table (t + ) Operation Reset Set haracteristic Equation (t+) = Excitation Table (t +) Operation Reset Set hapter 5 - Part 48
49 T Flip-Flop escriptors haracteristic Table T (t + ) Operation ( t ) ( t ) No change omplement haracteristic Equation (t+) = T Excitation Table (t + ) ( t ) ( t ) T Operation No change omplement hapter 5 - Part 49
50 S-R Flip-Flop escriptors haracteristic Table S R (t + ) ( t ) haracteristic Equation (t+) = S + R, S. R =? Excitation Table (t) (t+ ) S Operation No change Reset Set Undefined R Operation X No change Set Reset X No change hapter 5 - Part 5
51 S-R Flip-flop S R? S R - - SR= S R (t+) X X = S + R, SR = hapter 5 - Part 5
52 J-K Flip-Flop escriptors haracteristic Table J K (t + ) ( t ) ( t ) haracteristic Equation (t+) = J + K Excitation Table (t) (t + ) J Operation No change Reset Set omplement K Operation X X X X No change Set Reset No hange hapter 5 - Part 52
53 Example : Flip-flop Behavior Use the characteristic tables to find the output waveforms for the flip-flops shown: lock,t T T hapter 5 - Part 53
54 Example : Flip-Flop Behavior (continued) Use the characteristic tables to find the output waveforms for the flip-flops shown: lock S,J R,K S R SR? J K JK hapter 5 - Part 54
55 Terms of Use All (or portions) of this material 28 by Pearson Education, Inc. Permission is given to incorporate this material or adaptations thereof into classroom presentations and handouts to instructors in courses adopting the latest edition of Logic and omputer esign Fundamentals as the course textbook. These materials or adaptations thereof are not to be sold or otherwise offered for consideration. This Terms of Use slide or page is to be included within the original materials or any adaptations thereof. hapter 5 - Part 55
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