Overview of Chapter 4

Transcription

1 Overview of hapter 4 Types of equential ircuits torage Elements Latches Flip-Flops equential ircuit nalysis tate Tables tate iagrams equential ircuit esign pecification ssignment of tate odes Implementation HL epresentation equential ircuits equential circuit contains: ombinational Logic: torage Elements Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, tate or Present tate, are signals from storage elements. The remaining outputs, Next tate are inputs to storage elements. torage elements: Latches or Flip- Flops Inputs Outputs ombinational Logic Next tate tate 2 equential ircuits Types of equential ircuits ombinatorial Logic Next state function: Next tate = f(inputs, tate) ombinatorial Logic Outputs = g(inputs, tate) lternate output function (Moore): Outputs = h(tate) Type of output function heavily influences the design 3 epends on time at which inputs are observed by storage elements and state of storage elements change ynchronous ehavior defined from knowledge of its signals at discrete instances of time torage elements affected by inputs and can change state only in relation to a timing signal (clock pulses from a clock) synchronous ehavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous! Nevertheless, the synchronous abstraction makes complex designs tractable! 4 iscrete Event imulation imulated NN Gate In order to understand the time behavior of a equential ircuit we use discrete event simulation ules: Gates modeled by an ideal (instantaneous) function and a fixed gate delay ny change in input values is evaluated to see if it causes a change in output value hanges in output values are scheduled for after the fixed gate delay t the time for a scheduled output change, the output value is changed along with any inputs connected to it 5 Example: 2-Input NN gate with a 5 ns. delay: F(Instantaneous) EL 5 ns. ssume and have been for a long time t time t=, changes to a at t=8 ns, back to. t(ns) F(I) F omment == for a long time F(I) changes to 5 F changes to after a 5 ns delay 8 F(Instantaneous) changes to 3 F changes to after a 5 ns delay 6 F

2 Gate Models toring tate uppose we represent gates with delay n ns as follows: n n n onsider a simple 2-input multiplexer: With function: = for = = for =... 7 What would happen if we connect output signal to input signal? 8 toring tate (ontinued) toring tate (ontinued) The circuit becomes: With function: = for =, and (t) dependent on (t 2) for =. The simple combinational circuit has now become a sequential circuit because its output is a function of a time sequence of input signals!.. 9 imulation example as input signals change with time. hanges occur every ns, so that the.2 ns delays are negligible. omment = when = Now remembers for = No change in = when = remembers Even when changes represents the state of the circuit, not just an output. toring tate (ontinued) asic (NO) Latch uppose we place an inverter in the feedback path. The following behavior results: The circuit is said to be unstable. For = it is an oscillator!... omment = when = Now "remembers" at.2 ns later at.2 ns later at.2 ns later ross-coupling two NO gates gives the Latch: Which has the time sequence behavior: (reset) (set) ' omment?? We don't know "et" to Now "remembers" "eset" to Now "remembers" oth go low?? INTILIT ' 2 2

3 asic (NN) Latch ross-oupling two NN gates gives the - Latch: (set) (reset) Which has the time sequence behavior: ' omment?? We don't know "et" to Now "remembers" "eset" to Now "remembers" oth go high?? INTILIT ' 3 locked - Latch dding two NN gates to the basic - NN Latch, we arrive at the locked Latch: This has a time sequence behavior similar to the asic - Latch except that: and are now active high signals (i.e. -- a "" signal on sets to ) and The and inputs are only observed when the line is high. has the meaning "lock" or "lock Pulse". ' 4 locked - Latch (ontinued) The locked - Latch can be described by a table: (t) (t+) omment The table describes what happens after the clock [at time (t+)] based on: current inputs (,) and current state (t). ' No change lear et??? Indeterminate No change lear et??? Indeterminate 5 haracteristic Equation for - Latch We can describe the behavior of output at time (t+) (immediately after one clock pulse) using a -Map: We can see that: (t+) = + ' given that (both are not high at once): = The locked Latch has the symbol: X 3 2 X ' 6 Latch Latch and Flip-Flop Triggering dding an inverter to the - Latch, gives the Latch: Note that there are no "Indeterminate" states! (t+) omment No change et lear et The graphic symbol for a Latch is: ' ' o far, the latches we have talked about are "clocked" with an input pulse. Here are some possible wave forms: Positive lock Pulse lock Period Positive edge lock Period Negative lock Puls e w Negative Edge w Positive lock Pulse Negative lock Pulse W = Pulse Width lock Period = Time between referenced edges. eference level is generally 5%. ise and Fall times may be important as well

4 ystem Level locking Master-lave Flip-Flop onsider a system comprised of ranks of latches or flip-flops connected by logic: If the lock Period is TOO HOT, some data changes will not propagate through the network. If the lock Pulse Width is TOO LONG, some data will propagate through the second rank of latches! ' ' ' ' ' LO ' ' ' ' ' LO One way to solve the locking Problem is with a master-slave organization: The complement of the clock is used to change the outputs. Now outputs change on ' only. Problem: One's catching in Master. Problem: Instability in Master. nother solution: Use -FF's or Edge Triggering ' ' ' 9 2 Edge Triggered Flip-Flops Flip-Flop haracteristic Tables Edge triggered Flip-Flops are sensitive to a small window for data changes around the time of a clock edge. etup Time: The time required for input data to be stable before the clock edge. Hold Time: The time data must remain stable after the clock edge. T ' T ' ' ' Positive Edge Triggered FFs ' ' Negative Edge Triggered FFs The haracteristic Tables: how current inputs. locking conditions are: how current state implicitly. Positive level triggered. Predict flip-flop state Negative level triggered. FTE LOING. Positive edge triggered. Negative edge triggered. NOTE: Proper clocking or flip-flop operation may be subject to conditions such as: et-up and hold times are met. imultaneous changes disallowed haracteristic Tables - Master lave Flip Flop (t+) omment (t) No change lear et '(t) omplement (t+) omment (t) No change lear et??? Indeterminate Two Latches driven by inverted clocks form a master-slave configuration. Input logic forms the logic transition: et (master) = s' eset (master) = s P Mas te r lave m s T (t+) omment (t) No change '(t) omplement (t+) omment lear et Master et is possible if the slave s is currently "" any time the clock P is high! Master eset is possible if the slave s is currently "" any time the clock P is high! This is referred to as One's atching

5 Master lave ymbols Flip-Flop onventions Master-lave Flip Flops are denoted by a line near the outputs. This highlights the fact that the slave changes FTE the master clocking condition is deasserted. ' ' ' ' ubble near a clock input denotes an active low assertion. Triangle near the clock input denotes edge sensitive. L-haped Line near the output denotes Master/lave. ' Positive Pulse Triggered Mas ter/lave FFs Negative Pulse Triggered Mas ter/lave FFs Propagation elay Logic gate, Latch and Flip-Flop timing parameters: TPLH: Propagation time low-to-high -- the time required for an output to transition from a low logic level to a high logic level from an input event (usually clock). TPHL: Propagation time high-to-low -- the time required for an output to transition from a high logic level to a low logic level from an input event (usually clock). lock kew: ifference in clock arrival times at different flip-flops. Tsu et-up time: Time data must be stable at FFs before the clock. Minimum clock period is set by: MX(TPHL,TPLH) + Logicelay + Tsu Hold Time and lock kew constrain the minimum logic plus flipflop delay. 27 alculating lock Frequency Given the network below, assume signal is changing from "" to "": lock Period = t PHL(Flip-Flop) +3*t PHL(Logic) + t su (Flip-Flop) Frequency = /(lock Period) LO LO ' tphl (Logic) lock Period tphl (Flip-Flop) tphl (Log ic ) ts u (Flip-Flop) tphl (Logic) LO ' 28 alculating lock Frequency ontd equential ircuit nalysis Given the network below, assume signal is changing from "" to "": lock Period = t PLH(Flip-Flop) +3*t PLH(Logic) + t su (Flip-Flop Frequency = /(lock Period) We ususally pick MX(t PHL, T PLH). LO LO ' tplh (Log ic ) lock Period tplh (Flip-Flop) tplh (Logic) ts u (Flip-Flop) tpl H(Lo g ic ) LO ' General Model urrent tate at time (t) is stored in an array of flip-flops. Inputs torage Elements ombinati onal Logic Next tate tate Next tate at time (t+) is a L oolean function of current state and inputs. Outputs at time (t) are a oolean function of current state (t) and (sometimes) current inputs (t). Outputs

6 Example (from Fig. 4-8) Example (Fig. 4-8) (ontinued) Input: x(t) Output: y(t) x tate: (t), (t) What is the Output Function? What is the Next tate Function? P ' ' y oolean Equations for the functions: x (t+) = (t)x(t) + (t)x(t) (t+) = (t)x(t) y(t) = x(t)((t) + (t)) Next tate P ' ' ' y Output 3 32 Example (Fig. 4-8) (ontinued) Where in time are inputs, outputs and states defined? Functional imulation - Fig. 4-8 Mano & ime. 53ns 6ns 59ns 22ns 265ns 38ns 37ns 424ns l EET... l LO... l X... l N... l N... l... l... l... l t t+ t+2 t+3 tate Table haracteristics tate table a multiple variable function table with the following four sections: Present tate the values of the state variables for each allowed state. Input the input combinations allowed. Next-state the value of the state at time (t+) based on the present state and the input. Output the value of the output as a function of the present state and (sometimes) the input. From the viewpoint of a truth table: the inputs are Input, Present tate and the outputs are Output, Next tate Example: tate Table (Fig. 4-8) lternate tate Table The TTE TLE can be filled in using the next state and output equations: (t+) = (t)x(t) + (t)x(t) (t+) = (t)x(t) y(t) = x (t)((t) + (t)) Present tate Input Next tate Output (t) (t) x(t) (t+) (t+) y(t) 35 2-dimensional table that matches well to a -map. Present state rows and input columns in Gray code order. (t+) = (t)x(t) + (t)x(t) (t+) = (t)x(t) y(t) = x (t)((t) + (t)) Present Next tate Output tate x(t)= x(t)= x(t)= x(t)= (t) (t) (t+)(t+) (t+)(t+) y(t) y(t) 36 6

7 tate iagram haracteristics The oolean state variables are a vector of n bits. Not all 2 n states are necessarily used! imilarly not all input and output combinations are used. The state variables may need to be initialize to a valid, appropriate initial state. Examples: system with states requires a minimum of 4 bits (3 bits gives only 8 symbols). coded inputs can have 6 combinations, only of which have meaning. tate iagrams The sequential circuit function can be represented in graphical form as a state diagram with the following components: circle with the state name in it for each state directed arc from the Present tate to the Next tate for each state transition label on each directed arc with the Input value which causes the state transition, and label: On each circle with the output value produced, or On each directed arc with the output value produced tate iagrams Label form: On circle with output included: state/output Moore type output depends only on state On directed arc with the output included: input/output Mealy type output depends on state and input tate iagram Example x=/y= Which type? Gets confusing as circuit grows in size. For small circuits, usually easier to understand than the state table. x=/y= x=/y= x=/y= x=/y= x=/y= Try drawing state diagram for mod 4 counter and toggle (T) flip-flop x=/y= x=/y= 39 4 Flip-Flop Input Functions The -Flip-Flop easy to analyze since it has only one input. Other FFs such as the and have two inputs. onvention used in text: First Letters designate the FF input function. econd Letters (or subscript) designate the state variable. Example with Two FFs: = = x = x = x + x Example 4-8 with Two FFs: = x + x = x y = ( + ) x nalysis with Other Flip-Flops With a Flip-Flop: Next state obtained directly from the flip-flop input equation for i With a, T or Flip-Flop: Obtain the values for each flip-flop input in terms of present state and input values Use the corresponding flip-flop characteristic table from Table 4- to determine the next state value of the flip-flop

8 haracteristic Tables (t+) omment (t) No change lear et (t) omplement T (t+) omment (t) No change (t) omplement (t+) omment (t) No change lear et? Indeterminate (t+) omment lear et Flip-Flop ircuit nalysis tep : Write the oolean expression for each flip-flop input. For flip-flop : = = For flip-flop : = = x P ' ' x Flip-Flop nalysis (ont.) tep 2: Using the diagram or equations, fill in the flip-flop inputs. = x = = x = x P ' ' Present Input Next tate tate Flip-Flop Inputs x 45 Flip-Flop nalysis (ont.) tep 3: y using haracteristic Table, the and inputs and the present state from the table, fill in the next state in the table for each flip flop. (t) = ; =; = ; Implies (t+) = (No hange) (t) = ; =; = ; Implies (t+) = (et ) (t+) omment (t) No change lear et (t) omp. Present Input Next Flip-Flop tate tate Inputs x 46 Flip-Flop nalysis (ont.) Flip-Flop nalysis (ont.) The result of completion of tep 3: Present Input Next Flip-Flop tate tate Inputs x For convenience, discard the flip-flop input columns What is the output function? 47 tep 4: From the diagrams or equations, place the output values in the table: Present Input tate Next tate x Output 48 8

9 dditional oncepts haracteristic Equations Moore and Mealy Models iagram Examples Table Examples haracteristic Equations an be used instead of characteristic tables for transforming flip-flop inputs to next state information (t+) omment (t) No change lear et (t) omplement (t+) = (t) + (t) T (t+) omment (t) No change (t) omplement (t+) omment (t) No change lear et? Indeterminate (t+) = + (t) (t+) omment lear et 49 (t+) = T (t) (t+) = 5 Moore and Mealy Models equential ircuits or equential Machines are also called Finite tate Machines (FMs). Two formal models exist: Moore Model Named after E.F. Moore. Outputs are a function ONL of states Usually specified on the states. Mealy Model Named after G. Mealy Outputs are a function of inputs N states Usually specified on the state transition arcs. 5 Moore and Mealy Example iagrams Mealy Model tate iagram maps inputs and state to outputs x=/y= Moore Model tate iagram maps states to outputs x= x= x=/y= / x=/y= x= x= / 2/ x= x=/y= x= 52 Moore and Mealy Example Tables Mealy Model tate Table maps inputs and state to outputs Present Next tate Output tate x= x= x= x= Moore Model tate Table maps state to outputs Present Next tate Output tate x= x=