Sequential Circuits. Introduction to Digital Logic. Course Outline. Overview. Introduction to Digital Logic. Introduction to Sequential Circuits

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1 Introduction to igital Logic Prof. Nizamettin IN ourse Outline. igital omputers, Number ystems, rithmetic Operations, ecimal, lphanumeric, and Gray odes 2. inary Logic, Gates, oolean lgebra, tandard Forms 3. ircuit Optimization, Two-Level Optimization, Map Manipulation, Multi-Level ircuit Optimization 4. dditional Gates and ircuits, Other Gate Types, Exclusive-O Operator and Gates, High-Impedance Outputs 5. Implementation Technology and Logic esign, esign oncepts and utomation, The esign pace, esign Procedure, The major design steps 6. Programmable Implementation Technologies: ead-only Memories, Programmable Logic rrays, Programmable rray Logic,Technology mapping to programmable logic devices 7. ombinational Functions and ircuits 8. rithmetic Functions and ircuits 9. equential ircuits torage Elements and equential ircuit nalysis. equential ircuits, equential ircuit esign tate iagrams, tate Tables. ounters, register cells, buses, & serial operations 2. equencing and ontrol, atapath and ontrol, lgorithmic tate Machines (M) 3. Memory asics 2 Introduction to igital Logic Lecture 9 equential ircuits torage Elements and equential ircuit nalysis Overview torage Elements and nalysis Introduction to sequential circuits Types of sequential circuits torage elements Latches Flip-flops equential circuit analysis tate tables tate diagrams ircuit and ystem Timing equential ircuit esign pecification ssignment of tate odes Implementation 3 4 Introduction to equential ircuits Inputs equential circuit contains: torage torage elements: Elements Latches or Flip-Flops ombinatorial Logic: Implements a multiple-output switching function tate Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, tate or Present tate, are signals from storage elements. The remaining outputs, Next tate are inputs to storage elements. ombinational Logic Next tate Outputs Introduction to equential ircuits ombinatorial Logic Next state function Next tate = f(inputs, tate) Output function (Mealy) Outputs = g(inputs, tate) Output function (Moore) Outputs = h(tate) Inputs torage Elements tate ombinational Logic Next tate Output function type depends on specification and affects the design significantly Outputs 5 6 opyright 2 N. IN. ll rights reserved.

2 Types of equential ircuits epends on the times at which: storage elements observe their inputs, and storage elements change their state ynchronous ehavior defined from knowledge of its signals at discrete instances of time torage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock) 2 synchronous ehavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous! iscrete Event imulation In order to understand the time behavior of a sequential circuit we use discrete event simulation. ules: Gates modeled by an ideal (instantaneous) function and a fixed gate delay ny change in input values is evaluated to see if it causes a change in output value hanges in output values are scheduled for the fixed gate delay after the input change t the time for a scheduled output change, the output value is changed along with any inputs it drives 7 8 imulated NN Gate Example: 2-Input NN gate with a.5 ns. delay: F(Instantaneous) EL.5 ns. ssume and have been for a long time t time t=, changes to a at t=.8 ns, back to. t (ns) F(I) F omment == for a long time F(Instantaneous) changes to.5 F changes to after a.5 ns delay.8 F(Instantaneous) changes to.3 F changes to after a.5 ns delay F Gate elay Models uppose gates with delay n ns are represented for n =.2 ns, n =.4 ns, n =.5 ns, respectively: ircuit elay Model toring tate onsider a simple 2-input multiplexer: With function: = for = = for =.2 Glitch is due to delay of inverter What if connected to?.4 ircuit becomes:.2 With function:.5 = for =, and (t) dependent on.4 (t.9) for = The simple combinational circuit has now become a sequential circuit because its output is a function of a time sequence of input signals! is stored value in shaded area 2 opyright 2 N. IN. ll rights reserved. 2

3 toring tate (ontinued) imulation example as input signals change with time. hanges occur every ns, so that the tenths of ns delays are negligible. Time omment remembers = when = Now remembers = for = No change in when changes = when = remembers = for = No change in when changes represent the state of the circuit, not just an output. uppose we place an inverter in the feedback path. toring tate (ontinued).2 The following behavior results: The circuit is said omment to be unstable. = when = For =, the circuit has become Now remembers what is called an,. ns later oscillator. an be,. ns later used as crude clock.,. ns later asic (NN) Latch ross-oupling two NN gates gives the - Latch: which has the time sequence behavior: =, = is forbidden as input pattern (set) (reset) Time omment?? tored state unknown et to Now remembers eset to Now remembers oth go high?? Unstable! ross-coupling two NO gates gives the Latch: Which has the time sequence behavior: asic (NO) Latch (reset) (set) Time omment?? tored state unknown et to Now remembers eset to Now remembers oth go low?? Unstable! 5 6 locked - Latch dding two NN gates to the basic - NN latch gives the clocked latch: Has a time sequence behavior similar to the basic - latch except that the and inputs are only observed when the line is high. means control or clock. 7 8 opyright 2 N. IN. ll rights reserved. 3

4 locked - Latch (continued) Latch The locked - Latch can be described by a table: The table describes what happens after the clock [at time (t+)] based on: current inputs (,) and current state (t). (t) (t+) omment No change lear et??? Indeterminate No change lear et??? Indeterminate dding an inverter to the - Latch, gives the Latch: Note that there are no indeterminate states! (t+) omment No change et lear No hange The graphic symbol for a Latch is: 9 2 Flip-Flops The Latch Timing Problem The latch timing problem Master-slave flip-flop Edge-triggered flip-flop tandard symbols for storage elements irect inputs to flip-flops Flip-flop timing In a sequential circuit, paths may exist through combinational logic: From one storage element to another From a storage element back to the same storage element The combinational logic between a latch output and a latch input may be as simple as an interconnect For a clocked -latch, the output depends on the input whenever the clock input has value 2 22 The Latch Timing Problem (continued) The Latch Timing Problem (continued) onsider the following circuit: uppose that initially =. lock lock s long as =, the value of continues to change! The changes are based on the delay present on the loop through the connection from back to. This behavior is clearly unacceptable. esired behavior: changes only once per clock pulse solution to the latch timing problem is to break the closed path from to within the storage element The commonly-used, path-breaking solutions replace the clocked -latch with: a master-slave flip-flop an edge-triggered flip-flop opyright 2 N. IN. ll rights reserved. 4

5 - Master-lave Flip-Flop onsists of two clocked - latches in series with the clock on the second latch inverted The input is observed by the first latch with = The output is changed by the second latch with = The path from input to output is broken by the difference in clocking values ( = and = ). The behavior demonstrated by the example with driven by given previously is prevented since the clock must change from to before a change in based on can occur Flip-Flop Problem Flip-Flop olution The change in the flip-flop output is delayed by the pulse width which makes the circuit slower or and/or are permitted to change while = uppose = and goes to and then back to with remaining at The master latch sets to is transferred to the slave uppose = and goes to and back to and goes to and back to The master latch sets and then resets is transferred to the slave This behavior is called s catching Use edge-triggering instead of master-slave n edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal Edge-triggered flip-flops can be built directly at the electronic circuit level, or master-slave flip-flop which also exhibits edge-triggered behavior can be used Edge-Triggered Flip-Flop Positive-Edge Triggered Flip-Flop The edge-triggered flip-flop is the same as the masterslave flip-flop It can be formed by: eplacing the first clocked - latch with a clocked latch or dding a input and inverter to a master-slave - flip-flop The delay of the - master-slave flip-flop can be avoided since the s-catching behavior is not present with replacing and inputs The change of the flip-flop output is associated with the negative edge at the end of the pulse It is called a negative-edge triggered flip-flop Formed by adding inverter to clock input changes to the value on applied at the positive clock edge within timing constraints to be specified Our choice as the standard flip-flop for most sequential circuits 29 3 opyright 2 N. IN. ll rights reserved. 5

6 tandard ymbols for torage Elements irect Inputs Master-lave: Postponed output indicators Edge-Triggered: ynamic indicator with ontrol with ontrol (a) Latches Triggered Triggered Triggered Triggered (b) Master-lave Flip-Flops Triggered Triggered (c) Edge-Triggered Flip-Flops t power up or at reset, all or part of a sequential circuit usually is initialized to a known state before it begins operation This initialization is often done outside of the clocked behavior of the circuit, i.e., asynchronously. irect and/or inputs that control the state of the latches within the flip-flops are used for this initialization. For the example flip-flop shown applied to resets the flip-flop to the state applied to sets the flip-flop to the state 3 32 Flip-Flop Timing Parameters t s - setup time t h - hold time t w - clock pulse width t px - propagation delay t PHL - High-to-Low t PLH - Low-to-High t pd - max (t PHL, t PLH ) Flip-Flop Timing Parameters (continued) t s - setup time Master-slave - Equal to the width of the triggering pulse Edge-triggered - Equal to a time interval that is generally much less than the width of the the triggering pulse t h - hold time - Often equal to zero t px - propagation delay ame parameters as for gates except Measured from clock edge that triggers the output change to the output change equential ircuit nalysis Example General Model urrent tate at time (t) is stored in an array of flip-flops. torage Elements Inputs tate ombinational Logic Next tate Next tate at time (t+) LK is a oolean function of tate and Inputs. Outputs at time (t) are a oolean function of tate (t) and (sometimes) Inputs (t). Outputs Input: x(t) Output: y(t) tate: ((t), (t)) What is the Output Function? What is the Next tate Function? x P y opyright 2 N. IN. ll rights reserved. 6

7 Example (continued) Example (continued) oolean equations for the functions: (t+) = (t)x(t) + (t)x(t) (t+) = (t)x(t) y(t) = x(t)((t) + (t)) x Next tate P ' Output y 37 Where in time are inputs, outputs and states defined? Functional imulation - Fig. 4-8 Mano & Kime l EET... l LOK... l X... l N... l N... l... l... l... l. 53ns 6ns 59ns t t+ t+2 22ns t+3 265ns 38ns 37ns 424ns 38 tate Table haracteristics tate table a multiple variable table with the following four sections: Present tate the values of the state variables for each allowed state. Input the input combinations allowed. Next-state the value of the state at time (t+) based on the present state and the input. Output the value of the output as a function of the present state and (sometimes) the input. From the viewpoint of a truth table: the inputs are Input, Present tate and the outputs are Output, Next tate Example : tate Table The state table can be filled in using the next state and output equations: (t+) = (t)x(t) + (t)x(t) (t+) = (t)x(t) y(t) = x (t)((t) + (t)) Present tate Input Next tate Output (t) (t) x(t) (t+) (t+) y(t) 39 4 Example : lternate tate Table tate iagrams 2-dimensional table that matches well to a K-map. Present state rows and input columns in Gray code order. (t+) = (t)x(t) + (t)x(t) (t+) = (t)x(t) y(t) = x (t)((t) + (t)) Present Next tate Output tate x(t)= x(t)= x(t)= x(t)= (t) (t) (t+)(t+) (t+)(t+) y(t) y(t) The sequential circuit function can be represented in graphical form as a state diagram with the following components: circle with the state name in it for each state directed arc from the Present tate to the Next tate for each state transition label on each directed arc with the Input values which causes the state transition, and label: On each circle with the output value produced, or On each directed arc with the output value produced opyright 2 N. IN. ll rights reserved. 7

8 tate iagrams Label form: On circle with output included: state/output Moore type output depends only on state On directed arc with the output included: input/output Mealy type output depends on state and input Example : tate iagram Which type? iagram gets confusing for large circuits For small circuits, usually easier to understand than the state table x=/y= x=/y= x=/y= x=/y= x=/y= x=/y= x=/y= x=/y= Moore and Mealy Models Moore and Mealy Example iagrams equential ircuits or equential Machines are also called Finite tate Machines (FMs). Two formal models exist: Moore Model Named after E.F. Moore. Outputs are a function ONL of states Usually specified on the states. Mealy Model Named after G. Mealy Outputs are a function of inputs N states Usually specified on the state transition arcs. In contemporary design, models are sometimes mixed Moore and Mealy Mealy Model tate iagram maps inputs and state to outputs x=/y= Moore Model tate iagram maps states to outputs x= x= x=/y= x=/y= x=/y= / x= x= x= / 2/ x= Moore and Mealy Example Tables Example 2: equential ircuit nalysis Mealy Model state table maps inputs and state to outputs Present tate Next tate x= x= Output x= x= Moore Model state table maps state to outputs Present Next tate Output tate x= x= Logic iagram: lock eset Z opyright 2 N. IN. ll rights reserved. 8

9 Example 2: Flip-Flop Input Equations Example 2: tate Table Variables Inputs: None Outputs: Z tate Variables:,, Initialization: eset to (,,) Equations (t+) = (t)(t) (t+) = (t)(t) + (t)(t) (t+) = (t)(t) Z = (t)(t) lock eset Z X = X(t+) (t+) = (t)(t) (t+) = (t)(t) + (t)(t) (t+) = (t)(t) Z 49 5 Example 2: tate iagram ircuit and ystem Level Timing eset Which states are used? What is the function of the circuit? onsider a system comprised of ranks of flip-flops connected by logic: If the clock period is too short, some data changes will not propagate through the circuit to flip-flop inputs before the setup time interval begins ' ' ' ' ' LOK ' ' ' ' ' LOK 5 52 ircuit and ystem Level Timing (continued) Timing components along a path from flip-flop to flip-flop t p t pd,ff t pd,om t s t slack (a) Edge-triggered (positive edge) tpd,ff tpd,om tslack ts tp (b) Pulse-triggered (negative pulse) ircuit and ystem Level Timing (continued) New Timing omponents t p - clock period - The interval between occurrences of a specific clock edge in a periodic clock t pd,om - total delay of combinational logic along the path from flip-flop output to flip-flop input t slack - extra time in the clock period in addition to the sum of the delays and setup time on a path an be either positive or negative Must be greater than or equal to zero on all paths for correct operation opyright 2 N. IN. ll rights reserved. 9

10 ircuit and ystem Level Timing (continued) Timing Equations t p = t slack + (t pd,ff + t pd,om + t s ) For t slack greater than or equal to zero, t p max (t pd,ff + t pd,om + t s ) for all paths from flip-flop output to flip-flop input an be calculated more precisely by using t PHL and t PLH values instead of t pd values, but requires consideration of inversions on paths alculation of llowable t pd,om ompare the allowable combinational delay for a specific circuit: a) Using edge-triggered flip-flops b) Using master-slave flip-flops Parameters t pd,ff (max) =. ns t s (max) =.3 ns for edge-triggered flip-flops t s = t wh =. ns for master-slave flip-flops lock frequency = 25 MHz alculation of llowable t pd,om (continued) alculations: t p = /clock frequency = 4. ns Edge-triggered: t pd,om +.3, t pd,om 2.7 ns Master-slave: t pd,om +., t pd,om 2. ns omparison: uppose that for a gate, average t pd =.3 ns Edge-triggered: pproximately 9 gates allowed on a path Master-slave: pproximately 6 to 7 gates allowed on a path 57 opyright 2 N. IN. ll rights reserved.