Page 1. Some Definitions. Chapter 3: Sequential Logic. Sequential Logic. The Combinational Logic Unit. A NOR Gate with a Lumped Delay

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1 3- hapter 3 equential Logic hapter 3: equential Logic 3-2 hapter 3 equential Logic ome efinitions r. Tim McGuire am Houston tate University ased on notes by Miles Murdocca ombinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs (e.g., an adder). equential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs (e.g., a memory unit). Finite machine: a circuit which has an internal, and whose outputs are functions of both current inputs and its internal (e.g., a vending machine controller). 3-3 hapter 3 equential Logic The ombinational Logic Unit Translates a set of inputs into a set of outputs according to one or more mapping functions. Inputs and outputs for a LU normally have two distinct (binary) values: high and low, and, and, or 5 v and v, for eample. The outputs of a LU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. set of inputs i i n are presented to the LU, which produces a set of outputs according to mapping functions f f m. i i i n ombinational logic unit f f f m 3-4 hapter 3 equential Logic equential Logic The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs. There is a need for circuits with a memory, which behave differently depending upon their previous. n eample is the vending machine, which must remember how many and what kinds of coins have been inserted, and which behave according to not only the current coin inserted, but also upon how many and what kind of coins have been deposited previously. These are referred to as finite machines, because they can have at most a finite number of s. 3-5 hapter 3 equential Logic lassical Model of a Finite tate Machine 3-6 hapter 3 equential Logic NO Gate with a Lumped elay Inputs i o i k ombinational logic unit f o Outputs f m tate bits + + s n n sn ynchronization signal elay elements (one per bit) This delay between input and output is at the basis of the functioning of an important memory element, the flip-flop. Page

2 3-7 hapter 3 equential Logic n - Flip-Flop 3-8 hapter 3 equential Logic lock Waveform t t t i+ (disallowed) mplitude Time (disallowed) 2 2 ycle time = 25 ns The - flip-flop is an active-high (positive logic) device. In a positive logic system, the action happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs are stable at the correct value when the clock net goes high. 3-9 hapter 3 equential Logic locked - Flip-Flop 3- hapter 3 equential Logic locked (ata) Flip-Flop ircuit 2 3 ymbol 2 2 The clock signal,, turns on the inputs to the flip-flop. The clocked flip-flop, sometimes called a latch, has a potential problem: If changes while the clock is high, the output will also change. The Master- lave flip-flop solves this problem. 3- hapter 3 equential Logic Master-lave Flip-Flop 3-2 hapter 3 equential Logic The asic - Flip-Flop Master M ircuit lave M ircuit ymbol ymbol 3 2 The rising edge of the clock clocks new data into the master, while the slave holds previous data. The falling edge clocks the new master data into the slave. 2 2 The -L flip-flop eliminates the = = problem of the - flip-flop, because enables while ' disables, and vice versa. However there is still a problem. If goes momentarily to and then back to while the flip-flop is active and in the reset, the flip-flop will catch the. This is referred to as s catching. The - master-slave flip-flop solves this problem. Page 2

3 3-3 hapter 3 equential Logic Master-lave - Flip-Flop 3-4 hapter 3 equential Logic T Flip-Flop T T ircuit ymbol ircuit ymbol The presence of a constant at and means that the flipflop will change its from - or - each time it is clocked by the T (toggle) input. 3-5 hapter 3 equential Logic Negative Edge-Triggered Flip-Flop tores 3-6 hapter 3 equential Logic Finite tate Machine esign ounter has a clock input,, and a EET input. Has two output lines, which must take values of,,, and on subsequent clock cycles. mplitude ycle time = 25 ns Time When the clock is high, the two input latches output, so the main latch remains in its previous regardless of changes in. When the clock goes high-low, values in the two input latches will affect the of the main latch. While the clock is low, cannot affect the main latch. tores Main latch Modulo-4 ounter Time (t) It requires two flip-flops to store the. EET q 3-bit synchronous counter q s Time (t) s 3-7 hapter 3 equential Logic tate Transition iagram for a Modulo(4) ounter EET / q Output / q / / Output / / / / / / Output Output tate Table tate Table With tates ssigned Net tate Present tate EET / / / / / / / / Present tate EET : : : : The diagram and table tell all there is to know about the FM, and are the basis for a provably correct design. 3-8 hapter 3 equential Logic Truth Table r(t) (t)s (t) s (t+) q q (t+) evelop equations from this truth table for s (t+), (t+), q (t+), and q (t+) from inputs r(t), s (t) and (t) Page 3

4 3-9 hapter 3 equential Logic Equations 3-2 hapter 3 equential Logic Logic esign for a Modulo(4) ounter EET s(t? )? r(t)s(t)s(t)? r(t)s(t)s(t) s(t? )? r(t)s(t)s(t)? r(t)s(t)s(t) q q(t? )? r(t)s(t)s(t)? r(t)s(t)s(t) q(t? )? r(t)s(t)s(t)? r(t)s(t)s(t) s q Implement these equations There are many simpler techniques for implementing counters. 3-2 hapter 3 equential Logic Eample: equence etector esign a machine that outputs a when eactly 2 of the last 3 inputs are. e.g. input sequence of produces an output sequence of ssume input is a -bit serial line. Use flip-flops and 8- multipleers. egin by constructing a transition diagram hapter 3 equential Logic tate Transition iagram for equence etector esign a machine that outputs a when eactly 2 of the last 3 inputs are. / / / / / / / / E / F / / / Pres. X tate 2 2 Z 2 Z = / / = / / = / / = / / E= / / F= / / G= / / / G / iscuss: the meaning of each. onvert table to truth table (how?). olve for s 2 s and Z hapter 3 equential Logic Logic iagram for equence etector 3-24 hapter 3 equential Logic Eample: Vending Machine ontroller s 2 s Z cepts nickel, dime, and quarter. When value of money inserted equals or eceeds twenty cents, machine vends item and returns change if any, and waits for net transaction. Implement with PL and flip-flops. Page 4

5 3-25 hapter 3 equential Logic tate Transition iagram for Vending Machine ontroller / dime is inserted / N/ N/ / / / / = ispense/o not dispense merchandise / 5 / = eturn/o not return a nickel in change N/ / = eturn/o not return a dime in change / / N/ 5 N = Nickel = ime = uarter 3-26 hapter 3 equential Logic Truth Table for Vending Machine ontroller ase equivalent Present oin Net ispense s s z 2 z z eturn nickel eturn dime 2 3 d d d d d d d d d d 8 9 d d d d d d d d d d 3-27 hapter 3 equential Logic (a)fm ircuit, (b)truth Table, and (c)pl ealization for Vending Machine ontroller (a) ase equivalent Present oin 5 5 PL s 2 3 d d d d d d d d d d 8 9 d d d d d d d d d d (b) z 2 s z z ispense Net eturn nickel eturn dime s s z 2 z z (c) s z 2 z z 3-28 hapter 3 equential Logic Mealy versus Moore Machines Mealy model: Outputs are functions of inputs and present. Previous FM designs were Mealy machines, because net was computed from present and inputs. z2 5 5 z PL z s Moore model: Outputs are functions of present only. 4-to- MUX 4-to- MUX z s oth are equally powerful. z 3-29 hapter 3 equential Logic Tri-tate uffers F?? F?? 3-3 hapter 3 equential Logic 4-it egister Gate-Level View 3 2 Write (W) Enable (EN) F = or F =? F = or F =? bstract epresentation of a 4-it egister 3 2 Tri- buffer Tri- buffer, inverted control There is a third : high impedance. This means the gate output is essentially disconnected from the circuit. This is indicated by? in the figure. hip-level View W EN Page 5

6 3-3 hapter 3 equential Logic Internal Layout and lock iagram for Left-ight hift with Parallel ead/write apabilities 3-32 hapter 3 equential Logic Modulo(8) ipple ounter c c Left s hift out Left shift in 3 2 ight shift in Note the use of the T flip-flops. They are used to toggle the input of the net flipflop when its output i. Enable (EN) EET 2 c ight shift out c Enable (EN) ontrol Function 3 2 Enable MO(8) OUNTE EET 2 c c No change hift left hift right Left shift in Left shift out c c ight shift out ight shift in 2 Parallel load 3-33 hapter 3 equential Logic onverting a NO - to an NN hapter 3 equential Logic ircuit with a Hazard Glitch caused by a hazard ctive-high NO Implementation Push bubbles (emorgan s) earrange bubbles onvert from bubbles to active-low signal names It is desirable to be able to turn off the flip-flop so it does not respond to such hazards. 2 Page 6

Principles of Computer Architecture. Appendix A: Digital Logic

A-1 Appendix A - Digital Logic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational