Synthesis of Reversible Sequential Elements

Transcription

1 Synthesis of Reversible Sequential Elements Speaker:Kuang-Jung Chang Author: Min-Lun Chuang Chun-Yao Wang Dept. of Computer Science National Tsing Hua University, Taiwan

2 Introduction Outline Background Previous work Novel reversible sequential elements Results Conclusions 2

3 Motivations Reversible circuits have applications in low power design Landauer Principle E = k T ln2 Moore s Law Nanotechnology, low power CMOS, optical computing, quantum computer Every future technology have to use reversible gates in order to reduce power consumption Reversible logic synthesis on combinational logic This work presents reversible flip-flops and latches used in designing reversible sequential circuits 3

4 Introduction Outline Background Previous work Novel reversible sequential elements Results Conclusions 4

5 Reversible Computing If we know the output, we can derive the input of the function. This kind of computation is called reversible if C= A=?, B=? A B C The AND Gate f :(x, x 2,, x n ) (y, y 2,, y m ) is called reversible iff: f is a bijection function A bijection function means the function is - and onto 5

6 Generalized Toffoli Gate TOF(C;t),where C is the set of control variable,{x, x 2, x 3, }, t is the set of target variable {x n }and C t = {Ø} ex: NOT gate is TOF(Ø ; x n ) CN gate is TOF(x ; x n ) CCN gate is TOF(x, x 2 ; x n )... 6

7 The CN Gate & CCN gate Controlled NOT control x a y b target CN (Feynman) gate symbol x y a b b=y x x y z Controlled Controlled NOT gate CCN (Toffoli) gate symbol a b c=z xy c x y z a b c Truth Table for the CCN Gate Truth Table for the CN Gate 7

8 Irreversible Function Implementation x y xy f (x,y)=xy x y z x y xy z f (x,y,)=xy Garbage is the outputs added to make an n-input m-output function reversible. Garbage 8

9 Restriction Fanout count of a signal net must equal one Fanout structure is not reversible If two copies of one signal are needed, a duplication is necessary x a y x y CN gate CN CN gate b a=x b=y x b= x =x T. Toffoli. Reversible computing. Tech memo MIT/LCS/TM-5, MIT Lab for Comp. Sci, 98 9

10 Reversible Circuits Synthesis Objective Minimize the number of gates Gate count gives a simple estimate of the implementation cost of the reversible circuit Minimize the number of garbage outputs Minimizing the number of garbage outputs leads to minimizing area and power

11 Introduction Outline Background Previous work A Beginning in the Reversible Logic Synthesis of Sequential Circuits [7] Novel reversible sequential elements Results Conclusions

12 Basic Gate Controlled NOT gate NOT & fanout x a y b CN gate symbol x a=x CN y b=y x b= x b= x =x CN gate New gate (NG ) more complex and powerful NAND & NOR x a=x y NG b=xy z b=(xy) z c=x z y c=(x+z) New gate symbol 2

13 D Latch D Q CLK Q CLK D + D latch truth table 3

14 Reversible D Latch CLK NG NG CN Q D CN CLK NG NG CN Q Garbage Gate outputs counts [7] 8 7 4

15 Introduction Outline Background Previous work A New Look at Reversible Memory Elements [5] Novel reversible sequential elements Results Conclusions 5

16 Basic Gate Controlled Swap gate (CS): Controlled Swap gate is also called Fredkin gate control x y z a b CS (Fredkin) gate symbol x y z CS c a b c x y z a b c Truth Table for the CS gate 6

17 Reversible RS Latch S Q Fanout Structure S Q R Q R Q The reversible RS latch proposed by Picton The reversible RS latch proposed by Rice [5] 7

18 D Flip-Flop Flop CLK CS CN CCN S CCN S Q D CN CCN R CCN R Q D flip-flop Garbage outputs Gate counts [5] 2 8

19 Introduction Outline Background Previous work Novel reversible sequential elements Results Conclusions 9

20 Truth Table Extension Synthesis Method Add garbage outputs to make the truth table reversible Input: A general truth table CLK J K + JK latch truth table extend CLK CLK J KJ QK n CLK QJ n+ K + 2

21 in K J CLK out Synthesis Procedure [9] S S2 S3 D. M. Miller, A transformation based algorithm for reversible logic synthesis, DAC 23 K J CLK Our design Existing one Garbage outputs K J CLK + Gate counts 4 2

22 Function Verification Obtained by JK latch truth table C = C + = JC CK CJ K J CLK + K J CLK + K JC K JC K + =(JC CK J)C = JC CK CJ J J (JC K) C J = JC CK J C C C C = C 22

23 Reversible T Latch & D Latch T Latch D Latch + + T CLK T CLK + D D CLK CLK + Evaluation of T latch Our design Existing one Garbage outputs Gate counts Evaluation of D latch Our design Existing one Garbage outputs Gate counts

24 Reversible D Flip-Flop Flop D flip-flop D CLK D + clk * * CLKD D C D latch D (master) latch Q Q D + + Evaluation of D flip-flop Garbage bits D D C Gate counts D latch D latch (slave) CLK Q + + Q Q Q Our design 3 5 Existing one 2 24

25 Reversible JK Flip-Flop Flop CLK J * * JK flip-flop K + * * CLK J J JK K latch K + + D D latch CLK D + + Evaluation of JK flip-flop Our design Existing one Garbage bits Gate counts

26 Reversible T Flip-Flop Flop T flip-flop CLK CLK CLK T + * * T T T latch + + D D latch D + + Evaluation of T flip-flop Our design Existing one Garbage bits Gate counts

27 Introduction Outline Background Previous work Novel reversible sequential elements Results Conclusions 27

28 Results No. of garbage outputs No. of gates Ours 25 Ratio(%) Ours 25 Ratio(%) D-latch JK-latch T-latch D flip-flop 3 5 JK flip-flop T flip_flop 3 5 Average H. Thapliyal and M. B. Srinivas, A beginning in the reversible logic synthesis of sequential circuits, in Proc. of MAPLD,

29 Results No. of garbage outputs No. of gates Ours 26 Ratio(%) Ours 26 Ratio(%) D flip-flop JK flip-flop T flip_flop Average J. E. Rice, A New Look at Reversible Memory Elements", in Proc. of the IEEE International Symposium on Circuits and Systems, 26 29

30 Introduction Outline Background Previous work Novel reversible sequential elements Results Conclusions 3

31 Conclusions We propose novel designs of reversible latches and flip-flops The implementation costs of our new designs are more competitive 3

32 Thank You