Spring 2017 EE 3613: Computer Organization Chapter 5: The Processor: Datapath & Control - 1

Transcription

1 Spring 27 EE 363: Computer Organization Chapter 5: The Processor: atapath & Control - Avinash Kodi epartment of Electrical Engineering & Computer Science Ohio University, Athens, Ohio kodi@ohio.edu Website: Course Outline CPU Performance & Evaluation Instruction Set Architecture Computer Arithmetic Processor: atapath and Control Pipelining Cache and Main Memory

2 Processor: atapath and Control Review: Combinational Circuits Boolean algebra, basic gates, adders (done previously) Review: Sequential Circuits Latches, Flip-Flops, Memory cell, Registers Verilog Free versions available from Aldec and ilinx ISE atapath and Control Single Cycle atapath Implementation Multiple Cycle atapath Implementation SR-Latch Latch: The output state is changed whenever the appropriate inputs change S R S R 2

3 SR-Latch Latch: The output state is changed whenever the appropriate inputs change S R S R undefined As long as R and S remain, then the value of (and bar) will remain unchanged This value is stored in this circuit This is the basic memory cell Transparent Latch Flip-Flop: The output state is changed only on a clock edge S G R G Next state is set State retained C 3

4 Regular -Latch Response Gating Signal (instead of clock) Edge-Triggered -Flip Flop Rising Edge Trigger Falling Edge Trigger P 2 2 G G 2 8 4

5 SR Flip Flop S R Rising Edge Trigger S R Next state ( + ) No Change =, Set (after active edge) =, Reset (after active edge) Not allowed S S P S 2 R R P R 2 9 JK Flip-Flop (J = S, K = R) J K Rising Edge Trigger J K Next state ( + ) No Change =, Set (after active edge) =, Reset (after active edge) + = J + K (Characteristic Equation) J S P S 2 K R P R 2 5

6 T Flip Flop T Flip Flop, called as Toggle FF is frequently used in building counters T + + = T (Characteristic Equation) Falling edge triggered Negative Edge-Triggered (Master-Slave) ata q C C Clock C 6

7 -Flip Flop (positive edge triggered) ata q C C Clock C FF Summary Flip-Flop Characteristic Table JK Flip-Flop J K + Operation No Change Reset Set Complement Flip-Flop + Operation Reset Set SR Flip-Flop S R + Operation No Change Reset Set? Undefined T Flip-Flop T + Operation No Change Complement 4 7

8 FF Transition Input Codes Using FF state tables we can derive the input conditions that will cause specific transitions in each FF output 4 possible transitions: & T FFs have welldefined input conditions in each case J-K FF has on t Care () conditions Key to follow sequential logic circuit design examples (i.e. counters) FF Outputs FF Inputs (t) (t+) T J-K FF Excitation Table Flip-Flop Excitation Table JK Flip-Flop + J K Flip-Flop + SR Flip-Flop + S R T Flip-Flop + T 6 8

9 Analysis by Signal Tracing and Timing Charts Analysis steps: Assume an initial state of FFs (all FFs reset to unless specified) For the input sequence, determine the circuit output(s) and FF inputs etermine the new set of FF states after the next active clock edge etermine the output(s) that corresponds to the new states 7 Two Types of Clocked Sequential Circuits Moore Machine: If the output of a sequential circuit is a function of the present state only Mealy Machine: If the output of a sequential circuit is a function of both the present state and the input 8 9

10 State Tables and Graphs State Table Construction Step : etermine the FF input equations and output equations from the circuit Step 2: erive the next state equation for each FF from input equations from the circuit FF: + = T FF: + = T SR FF: + = S + R JK FF: + = J + K Step 3: Plot a next state map for each FF Step 4: Combine the maps to form a state table 9 Example of Moore s Machine (/3) Z A A B B A B Z = A B A = B B = + A 2

11 Example of Moore s Machine (2/3) Step : FF input equations and output equations: Z = A B A = B B = + A Step 2: Next state equations for the FF are: A + = B B + = + A Step 3: Corresponding K-maps for A + and B + 2 Example of Moore s Machine (3/3) Step 4: Combine the K-maps into transition table shown here from which states can be derived A + B + = = Z S Present State Next State = = Present Output (Z) S S3 S S S S2 S2 S S2 S3 S2 S S3 S2 S 22

12 Example of Mealy Machine (/3) A A B B B K A J A K B J B A A B Z B A A + = J A A + K A A = BA + A B + = J B B + K B B = B + (A) B = B + B + A B Z = A B + B + A 23 Example of Mealy Machine (2/3) Step : FF input equations and output equations: J A = B, K A = J B =, K B = A Step 2: Next state equations for the FF are: A + = BA + A B + = B + B + A B Z = A B + B + A Step 3: Corresponding K-maps for A + B + and Z 24 2

13 Example of Mealy Machine (3/3) Step 4: Combine the K-maps into transition table shown here from which states can be derived A + B + = = Z = = Present State Next State = = Present Output (Z) = = S S S S S S2 S2 S2 S S3 S3 S / S / / S / S3 / / / S2 / 25 esign of a Sequence etector (/3) Circuit examines a string of s and s applied to input and generates an output Z = only when the prescribed sequence occurs with the assumption that can only change between clock cycles. esign the circuit so that the input sequence ending in will produce an output Z = coincident with the last. The circuit does not reset when a occurs. = Z = Is this a Mealy machine or Moore machine? 26 3

14 esign of a Sequence etector (2/3) / Present State Next State = = Present Output (Z) = = S / S S S S S2 S / S2 / / S / S2 S S A + B + = = Z = = 27 esign of a Sequence etector (3/3) A + = B B + = Z = A 28 4

15 How about Moore Machine? Present State Next State = = Present Output (Z) S / S / S S S S S2 S S3 / S2 / S2 S S3 S3 S2 S A + B + = = Z 29 5