Chapter 6 Sequential Circuits

Transcription

1 Overview Logic and omputer esign Fundamentals hapter 6 equential ircuits Part torage Elements and equential ircuit nalysis pring 4 Part - torage Elements and nalysis Introduction to sequential circuits Types of sequential circuits torage elements Latches Flip-flops equential circuit analysis tate tables tate diagrams ircuit and ystem Timing Part - equential ircuit esign pecification ssignment of tate odes Implementation hapter 6 - Part Introduction to equential ircuits Inputs equential circuit contains: torage Elements torage elements: Latches or Flip-Flops ombinatorial Logic: tate Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, tate or Present tate, are signals from storage elements. The remaining outputs, Next tate are inputs to storage elements. ombinational Logic Next tate Outputs hapter 6 - Part 3 Introduction to equential ircuits Inputs torage Elements ombinatorial Logic Next state function Next tate = f(inputs, tate) Output function (Mealy) Outputs = g(inputs, tate) Output function (Moore) Outputs = h(tate) tate ombinational Logic Next tate Output function type depends on specification and affects the design significantly Outputs hapter 6 - Part 4 Types of equential ircuits epends on the times at which: storage elements observe their inputs, and storage elements change their state ynchronous ehavior defined from knowledge of its signals at discrete instances of time torage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock) synchronous ehavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous! Nevertheless, the synchronous abstraction makes complex designs tractable! hapter 6 - Part 5 iscrete Event imulation In order to understand the time behavior of a sequential circuit we use discrete event simulation. ules: Gates modeled by an ideal (instantaneous) function and a fixed gate delay ny change in input values is evaluated to see if it causes a change in output value hanges in output values are scheduled for the fixed gate delay after the input change t the time for a scheduled output change, the output value is changed along with any inputs it drives hapter 6 - Part 6

2 imulated NN Gate Example: -Input NN gate with a.5 ns. delay: F(Instantaneous) EL.5 ns. ssume and have been for a long time t time t=, changes to a at t=.8 ns, back to. t (ns) F(I) F omment == for a long time F(I) changes to.5 F changes to after a.5 ns delay.8 F(Instantaneous) changes to.3 F changes to after a.5 ns delay F hapter 6 - Part 7 Gate elay Models uppose gates with delay n ns are represented for n =. ns, n =.4 ns, n =.5 ns, respectively:..4.5 hapter 6 - Part 8 ircuit elay Model toring tate onsider a simple -input multiplexer: With function: = for = = for =. Glitch is due to delay of inverter hapter 6 - Part 9 What if connected to?.4 ircuit becomes:. With function:.5 = for =, and (t) dependent on.4 (t.9) for = The simple combinational circuit has now become a sequential circuit because its output is a function of a time sequence of input signals! is stored value in shaded area hapter 6 - Part toring tate (ontinued) imulation example as input signals change with time. hanges occur every ns, so that the tenths of ns delays are negligible. Time omment remembers = when = Now remembers = for = No change in when changes = when = remembers = for = No change in when changes represent the state of the circuit, not just an output. hapter 6 - Part toring tate (ontinued) uppose we place an inverter in the feedback path The following behavior results: The circuit is said omment to be unstable. = when = For =, the Now remembers circuit has become,. ns later what is called an,. ns later oscillator. an be,. ns later used as crude clock.. hapter 6 - Part

3 asic (NN) Latch ross-oupling two NN gates gives the - Latch: Which has the time sequence behavior: =, = is forbidden as input pattern Time (set) (reset) omment?? tored state unknown et to Now remembers eset to Now remembers oth go high?? Unstable! asic (NO) Latch ross-coupling two (reset) NO gates gives the Latch: Which has the time (set) sequence Time omment behavior:?? tored state unknown et to Now remembers eset to Now remembers oth go low?? Unstable! hapter 6 - Part 3 hapter 6 - Part 4 locked - Latch locked - Latch (continued) dding two NN gates to the basic - NN latch gives the clocked latch: Has a time sequence behavior similar to the basic - latch except that the and inputs are only observed when the line is high. means control or clock. The locked - Latch can be described by a table: The table describes what happens after the clock [at time (t+)] based on: current inputs (,) and current state (t). (t) (t+) omment No change lear et??? Indeterminate No change lear et??? Indeterminate hapter 6 - Part 5 hapter 6 - Part 6 Latch Flip-Flops dding an inverter to the - Latch, gives the Latch: Note that there are no indeterminate states! (t+) omment No change et lear No hange The graphic symbol for a Latch is: The latch timing problem Master-slave flip-flop Edge-triggered flip-flop tandard symbols for storage elements irect inputs to flip-flops Flip-flop timing hapter 6 - Part 7 hapter 6 - Part 8

4 The Latch Timing Problem The Latch Timing Problem (continued) In a sequential circuit, paths may exist through combinational logic: From one storage element to another From a storage element back to the same storage element The combinational logic between a latch output and a latch input may be as simple as an interconnect For a clocked -latch, the output depends on the input whenever the clock input has value hapter 6 - Part 9 onsider the following circuit: uppose that initially =. lock lock s long as =, the value of continues to change! The changes are based on the delay present on the loop through the connection from back to. This behavior is clearly unacceptable. esired behavior: changes only once per clock pulse hapter 6 - Part The Latch Timing Problem (continued) solution to the latch timing problem is to break the closed path from to within the storage element The commonly-used, path-breaking solutions replace the clocked -latch with: a master-slave flip-flop an edge-triggered flip-flop hapter 6 - Part - Master-lave Flip-Flop onsists of two clocked - latches in series with the clock on the second latch inverted The input is observed by the first latch with = The output is changed by the second latch with = The path from input to output is broken by the difference in clocking values ( = and = ). The behavior demonstrated by the example with driven by given previously is prevented since the clock must change from to before a change in based on can occur. hapter 6 - Part Flip-Flop Problem The change in the flip-flop output is delayed by the pulse width which makes the circuit slower or and/or are permitted to change while = uppose = and goes to and then back to with remaining at The master latch sets to is transferred to the slave uppose = and goes to and back to and goes to and back to The master latch sets and then resets is transferred to the slave This behavior is called s catching Flip-Flop olution Use edge-triggering instead of master-slave n edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal Edge-triggered flip-flops can be built directly at the electronic circuit level, or master-slave flip-flop which also exhibits edge-triggered behavior can be used. hapter 6 - Part 3 hapter 6 - Part 4

5 Edge-Triggered Flip-Flop Positive-Edge Triggered Flip-Flop The edge-triggered flip-flop is the same as the masterslave flip-flop Formed by adding inverter to clock input It can be formed by: eplacing the first clocked - latch with a clocked latch or dding a input and inverter to a master-slave - flip-flop The delay of the - master-slave flip-flop can be avoided since the s-catching behavior is not present with replacing and inputs The change of the flip-flop output is associated with the negative edge at the end of the pulse It is called a negative-edge triggered flip-flop hapter 6 - Part 5 changes to the value on applied at the positive clock edge within timing constraints to be specified Our choice as the standard flip-flop for most sequential circuits hapter 6 - Part 6 tandard ymbols for torage Elements irect Inputs Master-lave: Postponed output indicators Edge-Triggered: ynamic indicator with ontrol with ontrol (a) Latches Triggered Triggered Triggered Triggered (b) Master-lave Flip-Flops Triggered Triggered (c) Edge-Triggered Flip-Flops hapter 6 - Part 7 t power up or at reset, all or part of a sequential circuit usually is initialized to a known state before it begins operation This initialization is often done outside of the clocked behavior of the circuit, i.e., asynchronously. irect and/or inputs that control the state of the latches within the flip-flops are used for this initialization. For the example flip-flop shown applied to resets the flip-flop to the state applied to sets the flip-flop to the state hapter 6 - Part 8 Flip-Flop Timing Parameters Flip-Flop Timing Parameters (continued) t s - setup time t h -hold time t w -clock / pulse width t px -propagation delay t PHL - High-to- Low t PLH - Low-to- High t pd -max(t PHL, t PLH ) twh$ twh,min twl$ twl,min ts th tp-,min tp-,max (a) Pulse-triggered (positive pulse) t wh$ twh,min twl$ twl,min ts th tp-,min tp-,max (b) Edge-triggered (negative edge) hapter 6 - Part 9 t s - setup time Master-slave - Equal to the width of the triggering pulse Edge-triggered - Equal to a time interval that is generally much less than the width of the the triggering pulse t h - hold time - Often equal to zero t px -propagation delay ame parameters as for gates except Measured from clock edge that triggers the output change to the output change hapter 6 - Part 3

6 equential ircuit nalysis Example (from Fig. 6-7) General Model urrent tate Inputs at time (t) is stored in an torage array of Elements flip-flops. Next tate at time (t+) is a oolean function of tate and Inputs. tate LK ombinational Logic Next tate Outputs Outputs at time (t) are a oolean function of tate (t) and (sometimes) Inputs (t). Input: x(t) Output: y(t) tate: ((t), (t)) What is the Output Function? What is the Next tate Function? x P y hapter 6 - Part 3 hapter 6 - Part 3 Example (from Fig. 6-7) (continued) oolean equations for the functions: (t+) = (t)x(t) + (t)x(t) (t+) = (t)x(t) y(t) = x(t)((t) + (t)) x Next tate P Output ' y hapter 6 - Part 33 Example (from Fig. 6-7) (continued) Where in time are inputs, outputs and states defined? Functional imulation - Fig. 4-8 Mano & Kime l EET... l LOK... l... l N... l N... l... l... l... l. 53ns t 6ns t+ 59ns t+ ns t+3 65ns 38ns 37ns 44ns hapter 6 - Part 34 tate Table haracteristics tate table a multiple variable table with the following four sections: Present tate the values of the state variables for each allowed state. Input the input combinations allowed. Next-state the value of the state at time (t+) based on the present state and the input. Output the value of the output as a function of the present state and (sometimes) the input. From the viewpoint of a truth table: the inputs are Input, Present tate and the outputs are Output, Next tate hapter 6 - Part 35 Example : tate Table (from Fig. 6-7) The state table can be filled in using the next state and output equations: (t+) = (t)x(t) + (t)x(t) (t+) = (t)x(t) y(t) = x (t)((t) + (t)) Present tate Input Next tate Output (t) (t) x(t) (t+) (t+) y(t) hapter 6 - Part 36

7 Example : lternate tate Table tate iagrams -dimensional table that matches well to a K-map. Present state rows and input columns in Gray code order. (t+) = (t)x(t) + (t)x(t) (t+) = (t)x(t) y(t) = x (t)((t) + (t)) Present Next tate Output tate x(t)= x(t)= x(t)= x(t)= (t) (t) (t+)(t+) (t+)(t+) y(t) y(t) hapter 6 - Part 37 The sequential circuit function can be represented in graphical form as a state diagram with the following components: circle with the state name in it for each state directed arc from the Present tate to the Next tate for each state transition label on each directed arc with the Input values which causes the state transition, and label: On each circle with the output value produced, or On each directed arc with the output value produced. hapter 6 - Part 38 tate iagrams Label form: On circle with output included: state/output Moore type output depends only on state On directed arc with the output included: input/output Mealy type output depends on state and input Example : tate iagram x=/y= Which type? iagram gets confusing for large circuits For small circuits, usually easier to understand than the state table x=/y= x=/y= x=/y= x=/y= x=/y= x=/y= x=/y= hapter 6 - Part 39 hapter 6 - Part 4 Moore and Mealy Models Moore and Mealy Example iagrams equential ircuits or equential Machines are also called Finite tate Machines (FMs). Two formal models exist: Moore Model Named after E.F. Moore. Outputs are a function ONL of states Usually specified on the states. Mealy Model Named after G. Mealy Outputs are a function of inputs N states Usually specified on the state transition arcs. In contemporary design, models are sometimes mixed Moore and Mealy hapter 6 - Part 4 Mealy Model tate iagram x=/y= maps inputs and state to outputs x=/y= Moore Model tate iagram maps states to outputs x= x= / x=/y= x= x= x=/y= x= / / x= hapter 6 - Part 4

8 Moore and Mealy Example Tables Example : equential ircuit nalysis Mealy Model state table maps inputs and state to outputs Present tate Next tate x= x= Output x= x= Moore Model state table maps state to outputs Present Next tate tate Output x= x= Logic iagram: lock eset Z hapter 6 - Part 43 hapter 6 - Part 44 Example : Flip-Flop Input Equations Example : tate Table Variables Inputs: None Outputs: Z tate Variables:,, Initialization: eset to (,,) Equations (t+) = Z = (t+) = (t+) = = (t+) Z hapter 6 - Part 45 hapter 6 - Part 46 Example : tate iagram ircuit and ystem Level Timing eset Which states are used? What is the function of the circuit? onsider a system comprised of ranks of flip-flops connected by logic: If the clock period is too short, some data changes will not propagate through the circuit to flip-flop inputs before the setup time interval begins LOK ' ' ' ' ' ' ' ' ' ' LOK hapter 6 - Part 47 hapter 6 - Part 48

9 ircuit and ystem Level Timing (continued) Timing components along a path from flip-flop to flip-flop t p t pd,ff t pd,om t s t slack (a) Edge-triggered (positive edge) t pd,ff t pd,om t slack t s t p (b) Pulse-triggered (negative pulse) ircuit and ystem Level Timing (continued) New Timing omponents t p - clock period - The interval between occurrences of a specific clock edge in a periodic clock t pd,om - total delay of combinational logic along the path from flip-flop output to flip-flop input t slack - extra time in the clock period in addition to the sum of the delays and setup time on a path an be either positive or negative Must be greater than or equal to zero on all paths for correct operation hapter 6 - Part 49 hapter 6 - Part 5 ircuit and ystem Level Timing (continued) Timing Equations t p = t slack + (t pd,ff + t pd,om + t s ) For t slack greater than or equal to zero, t p max (t pd,ff + t pd,om + t s ) for all paths from flip-flop output to flip-flop input an be calculated more precisely by using t PHL and t PLH values instead of t pd values, but requires consideration of inversions on paths alculation of llowable t pd,om ompare the allowable combinational delay for a specific circuit: a) Using edge-triggered flip-flops b) Using master-slave flip-flops Parameters t pd,ff (max) =. ns t s (max) =.3 ns for edge-triggered flip-flops t s = t wh =. ns for master-slave flip-flops lock frequency = 5 MHz hapter 6 - Part 5 hapter 6 - Part 5 alculation of llowable t pd,om (continued) alculations: t p = /clock frequency = 4. ns Edge-triggered: t pd,om +.3, t pd,om.7 ns Master-slave: t pd,om +., t pd,om. ns omparison: uppose that for a gate, average t pd =.3 ns Edge-triggered: pproximately 9 gates allowed on a path Master-slave: pproximately 6 to 7 gates allowed on a path Logic and omputer esign Fundamentals hapter 6 equential ircuits Part equential ircuit esign hapter 6 - Part 53

10 Overview Part Types of equential ircuits torage Elements Latches Flip-Flops equential ircuit nalysis tate Tables tate iagrams Part equential ircuit esign pecification Formulation tate ssignment Flip-Flop Input and Output Equation etermination Optimization Verification hapter 6 - Part 55 The esign Procedure pecification Formulation - Obtain a state diagram or state table tate ssignment - ssign binary codes to the states Flip-Flop Input Equation etermination - elect flip-flop types and derive flip-flop equations from next state entries in the table Output Equation etermination - erive output equations from output entries in the table Optimization - Optimize the equations Technology Mapping - Find circuit from equations and map to flip-flops and gate technology Verification - Verify correctness of final design hapter 6 - Part 56 pecification omponent Forms of pecification Written description Mathematical description Hardware description language* Tabular description* Equation description* iagram describing operation (not just structure)* elation to Formulation If a specification is rigorous at the binary level (marked with * above), then all or part of formulation may be completed Formulation: Finding a tate iagram state is an abstraction of the history of the past applied inputs to the circuit (including power-up reset or system reset). The interpretation of past inputs is tied to the synchronous operation of the circuit. E. g., an input value (other than an asynchronous reset) is measured only during the setup-hold time interval for an edge-triggered flip-flop. Examples: tate represents the fact that a input has occurred among the past inputs. tate represents the fact that a followed by a have occurred as the most recent past two inputs. hapter 6 - Part 57 hapter 6 - Part 58 Formulation: Finding a tate iagram In specifying a circuit, we use states to remember meaningful properties of past input sequences that are essential to predicting future output values. sequence recognizer is a sequential circuit that produces a distinct output value whenever a prescribed pattern of input symbols occur in sequence, i.e, recognizes an input sequence occurence. We will develop a procedure specific to sequence recognizers to convert a problem statement into a state diagram. Next, the state diagram, will be converted to a state table from which the circuit will be designed. equence ecognizer Procedure To develop a sequence recognizer state diagram: egin in an initial state in which NONE of the initial portion of the sequence has occurred (typically reset state). dd a state that recognizes that the first symbol has occurred. dd states that recognize each successive symbol occurring. The final state represents the input sequence (possibly less the final input value) occurence. dd state transition arcs which specify what happens when a symbol not in the proper sequence has occurred. dd other arcs on non-sequence inputs which transition to states that represent the input subsequence that has occurred. The last step is required because the circuit must recognize the input sequence regardless of where it occurs within the overall sequence applied since reset.. hapter 6 - Part 59 hapter 6 - Part 6

11 tate ssignment equence ecognizer Example Each of the m states must be assigned a unique code Minimum number of bits required is n such that n log m where x is the smallest integer x There are useful state assignments that use more than the minimum number of bits There are n - m unused states hapter 6 - Part 6 Example: ecognize the sequence Note that the sequence contains and "" is a proper sub-sequence of the sequence. Thus, the sequential machine must remember that the first two one's have occurred as it receives another symbol. lso, the sequence contains as both an initial subsequence and a final subsequence with some overlap, i. e., or. nd, the in the middle,, is in both subsequences. The sequence must be recognized each time it occurs in the input sequence. hapter 6 - Part 6 Example: ecognize efine states for the sequence to be recognized: assuming it starts with first symbol, continues through each symbol in the sequence to be recognized, and uses output to mean the full sequence has occurred, with output otherwise. tarting in the initial state (rbitrarily named ""): / dd a state that recognizes the first "." tate "" is the initial state, and state "" is the state which represents the fact that the "first" one in the input subsequence has occurred. The output symbol "" means that the full recognized sequence has not yet occurred. hapter 6 - Part 63 Example: ecognize (continued) fter one more, we have: is the state obtained when the input sequence has two ""s. Finally, after and a, we have: / / Transition arcs are used to denote the output function (Mealy Model) Output on the arc from means the sequence has been recognized To what state should the arc from state go? emember:? Note that is the last state but the output occurs for the input applied in. This is the case when a Mealy model is assumed. / / / / hapter 6 - Part 64 Example: ecognize (continued) / / / learly the final in the recognized sequence is a sub-sequence of. It follows a which is not a sub-sequence of. Thus it should represent the same state reached from the initial state after a first is observed. We obtain: / / / / / hapter 6 - Part 65 Example: ecognize (continued) / / / The state have the following abstract meanings: : No proper sub-sequence of the sequence has occurred. : The sub-sequence has occurred. : The sub-sequence has occurred. : The sub-sequence has occurred. The / on the arc from to means that the last has occurred and thus, the sequence is recognized. / hapter 6 - Part 66

12 Example: ecognize (continued) The other arcs are added to each state for inputs not yet listed. Which arcs are missing? / / nswer: / "" arc from "" arc from "" arc from "" arc from. / hapter 6 - Part 67 Example: ecognize (continued) tate transition arcs must represent the fact that an input subsequence has occurred. Thus we get: / / / / / / Note that the arc from state to state implies that tate means two or more 's have occurred. / / hapter 6 - Part 68 Formulation: Find tate Table Formulation: Find tate Table From the tate iagram, we can fill in the tate Table. There are 4 states, one input, and one output. We will choose the form with four rows, one for each current state. From tate, the and input transitions have been filled in along with the outputs. / / Present tate / / / / / / Next tate x= x= Output x= x= From the state diagram, we complete the state table. / Present tate Next tate Output x= x= x= x= What would the state diagram and state table look like for the Moore model? / / / / / / / hapter 6 - Part 69 hapter 6 - Part 7 Example: Moore Model for equence For the Moore Model, outputs are associated with states. We need to add a state "E" with output value for the final in the recognized input sequence. This new state E, though similar to, would generate an output of and thus be different from. The Moore model for a sequence recognizer usually has more states than the Mealy model. Example: Moore Model (continued) We mark outputs on states for Moore model / / / rcs now show only / state transitions dd a new state E to produce the output Note that the new state, E/ E produces the same behavior in the future as state. ut it gives a different output at the present time. Thus these states do represent a different abstraction of the input history. hapter 6 - Part 7 hapter 6 - Part 7

13 Example: Moore Model (continued) tate ssignment Example The state table is shown below Memory aid re more state in the Moore model: Moore is More. Present tate Next tate x= x= E E Output y / / / / E/ hapter 6 - Part 73 Present Next tate Output tate x= x= x= x= How may assignments of codes with a minimum number of bits? Two =, = or =, = oes it make a difference? Only in variable inversion, so small, if any. hapter 6 - Part 74 tate ssignment Example Present Next tate Output tate x= x= x= x= How may assignments of codes with a minimum number of bits? 4 3 = 4 oes code assignment make a difference in cost? tate ssignment Example (continued) ssignment : =, =, =, = The resulting coded state table: Present tate Next tate x = x = Output x = x = hapter 6 - Part 75 hapter 6 - Part 76 tate ssignment Example (continued) ssignment : =, =, =, = The resulting coded state table: Present tate Next tate x = x = Output x = x = Find Flip-Flop Input and Output Equations: Example - ssignment ssume flip-flops Interchange the bottom two rows of the state table, to obtain K-maps for,, and Z: Z hapter 6 - Part 77 hapter 6 - Part 78

14 Optimization: Example : ssignment Find Flip-Flop Input and Output Equations: Example - ssignment Performing two-level optimization: Z = + = + + Z = Gate Input ost = ssume flip-flops Obtain K-maps for,, and Z: Z hapter 6 - Part 79 hapter 6 - Part 8 Optimization: Example : ssignment Map Technology Performing two-level optimization: Z = + Gate Input ost = 9 = elect this state assignment for Z = completion of the design Library: Flip-flops with eset (not inverted) NN gates with up to 4 inputs and inverters lock eset Initial ircuit: Z hapter 6 - Part 8 hapter 6 - Part 8 Mapped ircuit - Final esult equential esign: Example 3 lock eset Z esign a sequential modulo 3 accumulator for - bit operands efinitions: Modulo n adder - an adder that gives the result of the addition as the remainder of the sum divided by n Example: + modulo 3 = remainder of 4/3 = ccumulator - a circuit that accumulates the sum of its input operands over time - it adds each input operand to the stored sum, which is initially. tored sum: (, ), Input: (, ), Output: (Z,Z ) hapter 6 - Part 83 hapter 6 - Part 84

15 Example 3 (continued) omplete the state diagram: eset / / / Example 3 (continued) omplete the state table () () -() () (t+), (t+) (t+), (t+) (t+), (t+) (t+), (t+) tate ssignment: (, ) = (Z,Z ) odes are in gray code order to ease use of K-maps in the next step Z Z hapter 6 - Part 85 hapter 6 - Part 86 Example 3 (continued) ircuit - Final esult with N, O, NOT Find optimized flip-flop input equations for flip-flops Z Z = = eset lock hapter 6 - Part 87 hapter 6 - Part 88 Other Flip-Flop Types J-K and T flip-flops ehavior Implementation asic descriptors for understanding and using different flip-flop types haracteristic tables haracteristic equations Excitation tables For actual use, see eading upplement - esign and nalysis Using J-K and T Flip-Flops hapter 6 - Part 89 J-K Flip-flop ehavior ame as - flip-flop with J analogous to and K analogous to Except that J = K = is allowed, and For J = K =, the flip-flop changes to the opposite state s a master-slave, has same s catching behavior as - flip-flop If the master changes to the wrong state, that state will be passed to the slave E.g., if master falsely set by J =, K = cannot reset it during the current clock cycle hapter 6 - Part 9

16 J-K Flip-flop (continued) T Flip-flop Implementation To avoid s catching behavior, one solution used is to use an edge-triggered as the core of the flip-flop J K ymbol J K ehavior Has a single input T For T =, no change to state For T =, changes to opposite state ame as a J-K flip-flop with J = K = T s a master-slave, has same s catching behavior as J-K flip-flop annot be initialized to a known state using the T input eset (asynchronous or synchronous) essential hapter 6 - Part 9 hapter 6 - Part 9 T Flip-flop (continued) asic Flip-Flop escriptors Implementation To avoid s catching behavior, one solution used is to use an edge-triggered as the core of the flip-flop T ymbol T Used in analysis haracteristic table - defines the next state of the flip-flop in terms of flip-flop inputs and current state haracteristic equation - defines the next state of the flip-flop as a oolean function of the flip-flop inputs and the current state Used in design Excitation table - defines the flip-flop input variable values as function of the current state and next state hapter 6 - Part 93 hapter 6 - Part 94 Flip-Flop escriptors T Flip-Flop escriptors haracteristic Table (t + ) Operation eset et haracteristic Equation (t+) = Excitation Table (t +) Operation eset et haracteristic Table T (t+ ) Operation (t) (t) No change omplement haracteristic Equation (t+) = T Excitation Table (t+) (t) (t) T Operation No change omplement hapter 6 - Part 95 hapter 6 - Part 96

17 - Flip-Flop escriptors J-K Flip-Flop escriptors haracteristic Table (t +) Operation (t) No change eset et? Undefined haracteristic Equation (t+) = +,. = Excitation Table (t) (t+) Operation No change et eset No change haracteristic Table J K (t+) Operation (t) (t) No change eset et omplement haracteristic Equation (t+) = J + K Excitation Table (t) (t + ) J K Operation No change et eset No hange hapter 6 - Part 97 hapter 6 - Part 98 Flip-flop ehavior Example Use the characteristic tables to find the output waveforms for the flip-flops shown: lock,t Flip-Flop ehavior Example (continued) Use the characteristic tables to find the output waveforms for the flip-flops shown: lock,j,k? T T J K JK hapter 6 - Part 99 hapter 6 - Part