These conditions can be expressed by the following Boolean functions : A0 = D1 + D3 + D5 + D7 A1 = D2 + D4 + D6 + D7 A2 = D4 + D5 + D6 + D7

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1 PRELIMS EXAM MARCH (2010) STREAM: BCA-2 SUB:COA TIME: - 3:00 HOURS MARKS:100 Q-1 OCTAL TO BINARY ENCODER(8*3). ANS. Encoders : An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n (or less) input lines and n output lines. The output lines generate the binary code corresponding to the input value. An example of an encoder is the octalto-binary encoder, whose truth table is given below. Table 3.6 Truth Table for Octal-to-binary Encoder inputs outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A The encoder can be implemented with OR gates whose inputs are determined directly from the truth table. Output A0 =1 if the input octal digit is 1 or 3 or 5 or 7. Similar conditions apply for other two outputs. These conditions can be expressed by the following Boolean functions : A0 = D1 + D3 + D5 + D7 A1 = D2 + D4 + D6 + D7 A2 = D4 + D5 + D6 + D7 The encoder can be implemented with three OR gates. Figure 3.13 Octal-to-binary Encoder 1

2 ) EXPLAIN ALU IN DETAIL. ANS. To understand the organization of the CPU, let us consider the requirements placed on the CPU, the things that it must do: Fetch instruction:- -The CPU reads an instruction from memory. Interpret instruction:- -The instruction is decoded to determine what action is required. Fetch data:- -The execution of an instruction may require data from memory or an I/O module. Process data:- -The execution of an instruction may require performing some arithmetic or logical operation on data. Write data:- -The results of an execution may require writing data to memory or an I/O module. To do these things, it should be clear that the CPU needs to store some data temporarily. It must remember the location of the last instruction so that it can know where to get the next instruction. It needs to store instructions and data temporarily while an instruction is being executed. In other words, the CPU needs a small internal memory. 2 Figure 1 is a simplified view of a CPU, indicating its connection to the rest of the system via the system bus. A similar interface would be needed for any of the interconnection structures. The reader will recall that the major components of the CPU are an arithmetic and logic unit (ALU) and a control unit (CU). The ALU does the actual computation or processing of data. The control unit controls the

3 movement of data and instructions into and out of the CPU and controls the operation of the ALU. In addition, the figure shows a minimal internal memory, consisting of a set of storage locations, called registers. Working of Arithmetic & logic Unit : The ALU provides arithmetic and logic operation. In addition the CPU must provide shift operation. The shifter may be placed in the input of the ALU to provide a pre shift capability or at the output of the ALU to provide post shifting capability. In some cases the shift operations are included with the ALU ENCODING OF REGISTER SELECTION FIELDS BINARY CODE SEL A SEL B SEL D 000 INPUT INPUT NONE 001 R1 R1 R1 010 R2 R2 R2 011 R3 R3 R3 100 R4 R4 R4 101 R5 R5 R5 110 R6 R6 R6 111 R7 R7 R7 3 The encoding of the register selection fields is displayed in table. The three bit binary code listed in the column specify the binary code for each of 3 fields. The register selected by fields SEL A SEL B and SEL D is the one whose decimal

4 number is equivalent to the binary number in the code. When SEL A or SEL B is 000 the corresponding MUX select the external input data. When SEL D = 000 no destination register is selected but the contains of output bus are available in the external output. The OPR field has 5 bits and each operation is designated with symbolic name ) EXPLAIN DE-MORGAN S THEORAM. ANS. De morgan was a great logician and mathematician. He was the first to acclaim Boolean algebra. He discovered the two important theorems as follows. The complement of a product equals the sum of complements. i.e X+Y =X.Y demergen s theorem 1 : It can be proved with the help of truth table as shown below. X Y X Y X+Y X+Y X.Y Last two columns of the above truth table is equal hence LHS=RHS. Theorem 2 : The complement of a sum equals to the products of the complements. i.e x.y=x+y where X and y are Boolean variables. Proof of De morgans theorem : It can be proved with the help of truth table as shown below. X Y X Y X.Y X.Y X+Y hence second theorem is proved

5 Q-1 ATTEMPT ANY TWO. (1) EXPLAIN BOOLEAN ALGEBRA IN DETAIL. ANS: In George Bool an English mathematician, developed a two state algebra based on a set of Rules so that logical expression could be formed and manipulated. This algebra consists of Variable which can have one of the two possible values TRUE /FALSE or 1/0 or high /Low. These Variables are called Boolean variables and they have any one of the two above mentioned values. Boolean algebra differs from both the ordinary algebra and the binary number System. In Boolean algebra,x+x=x, because the variable x has only a logical value. It doesn t Have any numerical significance. In ordinary algebra x+x=2x and x.x=x 2 because the variable x Has numerical value here. In Boolean algebra 1+1=1 whereas in the binary number system 1+1=10 And in ordinary algebra 1+1=2. There is nothing like subtraction and division in Boolean Algebra. Also there are no negative or fractional numbers in Boolean algebra. In Boolean algebra multiplication and addition of the variables and functions are Also only logical. They actually represent logic operators. Logical multiplication is the same as AND operation. BOOLEAN OPERATORS : In ordinary algebra we use various mathematical operations like PLUS,MINUS, MULTIPLICATION AND DIVISION. Booelan Algebra allow only AND,OR & NOT operator. Boolean Operations: There are three basic logical operations: AND: This operation is represented by a dot or by the absence of an operator. For example, x.y = z or xy = z is read x AND y is equal to z. The logical operation AND is interpreted to mean that z=1 if and only if x=1 and y=1; otherwise z=0. OR: This operation is represented by a plus sign. For example, x+y = z is read x OR y is equal to z, meaning that z=1 if x=1 or if y=1 or if both x=1 and y=1. If both x=0 and y=0, then z=0. 5

6 NOT: This operation is represented by a prime (sometimes by a bar). For example, x = z (or x = z) is read x not is equal to z, meaning that z is complement of x. In other words, if x=1, then z=0, but if x=0, then z=1. Basic Identities of Boolean Algebra Table 2.1 Postulates and theorems of Boolean Algebra : (2) WHAT ARE THE REGISTERS AND WHAT ARE THE TYPES OF REGISTERS. ANS. Registers is a group of flip flop with each flip flop capable of storing 1 bit of digital information. A flip flop can store 1 bit of information. Thus an array of flip flop Is required to store binary Information. The number of flip flops is required being equal to the number of bits in the binary Word. Therefore n bit register has a group of n flip flop and is capable of storing any binary Information of n bits. 6 In addition to flip flop register may have combination gates that perform data processing tasks. In Broad definition register consists of group of flip flop and gates where flip flop hold the binary Information and gates control the information. Registers find application in a variety of digital systems including microprocessors. For example 8085 Intel microprocessor chip can contain seven 8 bit registers and five 1 bit registers. Types of Registers : In registers the data can be entered in serial form(i.e. one bit at a time) or In parallel form(i.e. all the bits at the same time). Same way data can be retrieved either in serial Or parallel form. As we know that registers are made of number of flip flops and these flip flops Connected in such a way that data may be shifted into or shifted out of them. Such registers are Known as shit registers. Hence we

7 can classify the registers based on data shifted and the way data retrieved. There are four basic types of shift registers as follows. Entered and a) Serial in, Serial out b) Serial in, parallel out c) Parallel in serial out d) Parallel in, parallel out 7

8 3) EXPLAIN MUX IN DETAIL. ANS. ) MUX is combinational circuit that is used to direct one out of 2 n input data Lines to A single output line. It is also known as data selector because it selects one of many inputs And directs it to the output. The selection of particular input data line is controlled by as Set of selection inputs. Normally there are 2 n input data lines and n input selection lines. The Block diagram of 4 to 1 line MUX is shown in fig. and logic circuit is displayed in fig. Each of the 4 data input I0 through I3 is applied to one input of AND gate. The two selection inputs s1 and s0 are decoded To select a particular AND gate. The output of the AND gates are applied to a single OR gate to provide The the single output. 8

9 simplification of Multiplexer. 1) It is used to connecting two or more sources to a single destination among computer units. 2) It is used in digital circuits to control signal and in data routing. 3) It is also useful in operation sequencing. 4) It is useful to constructing a common bus system ) SIMPLIFY THE BOOLEAN FUNCTION AND DRAW THE K MAP ANS. In addition to using Boolean algebra to simplify a Boolean function, a technique called map simplification can also be utilized. The map method is known as the Karnaugh map or K-map. Each combination of the variables in a truth table is called a minterm. There are 2 n minterms for a function of n variables. A fourth representation of a Boolean function can be given as the sum of the functions minterms. (Sum-of-Products) Examples F(x,y,z)= (1,4,5,6,7) Variable Map The following are maps for two, three and four-variable function: Figure 2.3 Maps for two, three and four variable functions 9

10 The variable names are listed across both the sides of the diagonal line into the corner of the map. The 0 s and the 1 s marked along each row and each column designate the value of the variables. Each variable under the brackets contain half of the squares in the map where that variable appears unprimed. The minterm represented by a square is determined from the binary assignment of the variable along the left top edges in the map. Here the min term 5 in the three variable maps are 101 of the second column. This minterm represents a value for the binary variables A, B and C with A and C being unprimed and B being primed. Sum-of-Products Simplification A Boolean function represented by a truth table is plotted into the map by inserting 1's into those squares where the function is 1. Boolean functions can then be simplified by identifying adjacent squares in the Karnaugh map that contain a 1. A square is considered adjacent to another square if it is next to, above, or below it. In addition, squares at the extreme ends of the same horizontal row are also considered 10

11 adjacent. The same applies to the top and bottom squares of a column. The objective to identify adjacent squares containing 1's and group them together. Groups must contain a number of squares that is an integral power of 2. Groups of combined adjacent squares may share one or more squares with one or more groups. Each group of squares represents an algebraic term, and the OR of those terms gives the simplified algebraic expression for the function. To find the most simplified algebraic expression, the goal of map simplification is to identify the least number of groups with the largest number of members. We will simplify the Boolean function. F (A,B,C) = (3,4,6,7) Figure 2.4 Map for F(A,B,C) = (3,4,6,7) The three variable maps for this function is shown in the figure 2.4 There are four squares marked with 1 s, one for each minterm that produces 1 for the function. These squares belong to minterm 3,4,6,7 and are recognized from the figure b. Two adjacent squares are combined in the third column. This column belongs to both B and C produces the term BC. The remaining two squares with 1 s in the two corner of the second row are adjacent and belong to row columns of C, so they produce the term AC. 11 The simplified expression for the function is the or of the two terms:

12 F = BC + AC The second example simplifies the following Boolean function: F(A,B,C) = (0,2,4,5,6) The five minterms are marked with 1 s in the corresponding squares of the three variable maps. The four squares in the first and the fourth columns are adjacent and represent the term C. The remaining square marked with a 1 belongs to minterm 5 and can be combined with the square of minterm 4 to produce the term AB. The simplified function is F = C +AB Figure 2.5 Map for F(A,B,C) = (0,2,4,5,6) Figure 2.6 Map for F(A,B,C,D) = (0,1,2,6,8,9,10) 12 The area in the map covered by this four variable consists of the squares marked with 1 s in fig The function contains 1 s in the four corners that when taken as groups give the term B D. This is possible because these four squares are adjacent when the map is considered with the top and bottom or left and right edges touching.

13 The two 1 s on the bottom row are combined with the two 1 s on the left of the bottom row to give the term B C. The remaining 1 in the square of minterm 6 is combined with the minterm 2 to give the term A CD. The simplified function is: F = B D + B C + A CD (2) EXPLAIN DE-CODER IN DETAIL. ANS. Decoders Discrete quantities of information are represented in digital computers with binary codes. A binary code of n bits is capable of representing up to 2 n distinct elements of the coded information. A decoder is a combinational circuit that converts binary information from the n coded inputs to a maximum of 2 n unique outputs. If the n-bit coded information has unused bit combinations, the decoder may have less than 2 n outputs. The decoders presented in this section are called n-to-m-line decoders, where m <= 2 n. Their purpose is to generate the 2 n (or fewer) binary combinations of the n input variables. A decoder has n inputs and m outputs and is also referred to as an n x m decoder. The logic diagram of a 3-to-8-line decoder is shown in the Figure 3.10 Figure to-8 line decoder 13

14 The three data inputs. A 0, A 1, and A 2, are decoded into eight outputs, each output representing one of the combinations of the three binary input variables. The three inverters provide the complement of the inputs, and each of the eight AND gates generates one of the binary combination. A particular application of this decoder is a binary-to-octal conversion. The input variables represent a binary number and the outputs represent the eight digits of the octal number system. However, a 3-to-8- line decoder can be used for decoding any 3-bit code to provide eight outputs, one for each combination of the binary code. Commercial decoders include one or more enable inputs to control the operation of the circuit. The decoder of the Figure has one enable input, E. The decoder is enabled when E is equal to 1 and disabled when E is equal to 0. The operation of the decoder can be clarified using the truth table listed in Table. When the enable input E is equal to 0, all the outputs are equal to 0 regardless of the values of the other three data inputs. The three x's in the table designate don't-care conditions. When the enable input is equal to 1, the decoder operates in a normal fashion. For each possible input combination, there are seven outputs that are equal to 0 and only one that is equal to 1. The output variable whose value is equal to 1 represents the octal number equivalent of the binary number that is available in the input data lines. Table 3.5 Truth Table for 3-to-8-line Decoder 14

15 Some decoders are constructed with NAND instead of AND gates. Since a NAND gate produces the AND operation with an inverted output, it becomes more economical to generate the decoder outputs in their complement form. A 2-to-4-line decoder with an enable input constructed with NAND gates is shown in Figure. The circuit operates with complemented outputs and a complemented enable input E. The decoder is enabled when E is equal to 0. As indicated by the truth table, only one output is equal to 0 at any given time; the other three outputs are equal to 1. The output whose value is equal to 0 represents the equivalent binary number in inputs Ai and Ao. The circuit is disabled when is equal to I, regardless of the values of the other two inputs. Figure to-4-line decoder with NAND gates Decoder Expansion A technique called decoder expansion can be utilized to construct larger decoders out of smaller ones. For example, two 2-to-4-line decoders can be combined to 15

16 construct a 3-to-8-line decoder. Figure below shows 3-8-line decoder constructed with two 2x4 decoders. Figure 3.12 A 3X8 decoder constructed with two 2X4 decoders The above given Figure shows how the decoders with enable inputs can be connected to form a larger decoder. As you can see that there are two 2-to-4-line decoders are combined to achieve a 3-to-8-line decoder. The two least significant bits of the input are connected to both decoders. The most significant bit is connected to the enable input of one decoder and through an inverter to the enable input of the other decoder. It is assumed that each decoder is enabled when its E input is equal to 1. When E is equal to 0, the decoder is disabled and all its outputs are in the 0 level. When A2 = 0, the upper decoder is enabled and the lower is disabled. The lower decoder outputs become inactive with all outputs at 0. The outputs of the upper decoder generate outputs Do through D3, depending on the values of A1 and A0(while A2 = 0). When A2= 1, the lower decoder is enabled and the upper is disabled. The lower decoder output generates the binary equivalent D4, through D7 since these binary numbers have a 1 in the A2 position. (3) EXPLAIN HALF ADDER IN DETAIL. ANS. Half-Adder The most basic digital arithmetic circuit. Performs the addition of two binary digits. 16

17 The input variables of a half-adder are called the augend and the addend. The output variables of a half-adder are called the sum and the carry. Figure 3.1 Half-adder The truth table shows when both x and y is high then output c produced 1 carry. While for other cases it will not generate any carry bit. The s output represents the Least significant bit of the sum. The boolean fuctions for the two output can be obtained directly from the truth table As below. Sum S= x y+xy = x+y (ex-or gate) Carry C = XY(And gate) OR Q.2 ATTEMPT ANY TWO IN DETAIL. 1) EXPLAIN FULL ADDER IN DETAIL. ANS. Full-Adder : A full-adder performs the addition of three binary digits. Two half-adders can be combined to for a full-adder.. Although a full adder has three inputs, it still only has two outputs since the largest number is = 3, and 3 can be represented by two bits. Table 3.1 Truth Table for Full-adder 17

18 Figure 3.2 Maps for Full-adder Figure 3.3 Full-adder circuit

19 (2)Flip-flops : ANS. A Flip-flop is a binary cell capable of storing one bit of information. It has two outputs, one for the normal value and one for the complement value of the bit stored in it. Flip-flops are storage elements utilized in synchronous sequential circuits. Synchronous sequential circuits employ signals that effect storage elements only at discrete instances of time. A timing device called a clock pulse generator that produces a periodic train of clock pulses achieves synchronization. Values maintained in the storage elements can only change when the clock pulses. Hence, a flip-flop maintains a binary state until directed by a clock pulse to switch states. The difference in the types of flip flops is in the number of inputs and the manner in which the inputs affect the binary state. Flip-flops can be described by a characteristic table which permutates all possible inputs (just like a truth table). The characteristic table of a flip-flop describes all possible outputs (called the next state) at time Q(t+1) over all possible inputs and the present state at time Q(t). The most common types of flip flops are: SR Flip-Flop D Flip-Flop 19

20 JK Flip-Flop T Flip-Flop SR Flip-Flop Figure 4.1 SR Flip-Flop Inputs: S (for set) R (for reset) C (for clock) Outputs: Q Q' The operation of the SR flip-flop is as follow. If there is no signal at the clock input C, the output of the circuit cannot change irrespective of the values at inputs S and R. Only when the clock signals changes from 0 to 1 can the output be affected according to the values in inputs S and R If S =1 and R = 0 when C changes when C changes from 0 to 1 output Q is set to 1. If S = 0 and R =1 when C changes from 0 to 1. If both S and R are 0 during the clock transition, output does not change. When both S and R are equal to 1, the output is unpredictable and may go to either 0 or 1, depending on internal timing that occur within the circuit. D Flip-Flop Figure 4.4 D D Flip-flop 20

21 Inputs: D (for data) C (for clock) Outputs: Q Q' The operation of the D flip-flop is as follow. The D Flip-Flop can be converted from SR Flip-Flop by inserting an inverter between S and R and assigning the symbol D to the single input. The D input is sampled during the occurrence of a clock transition from 0 to 1. If D=1, the output of the flip-flop goes to the 1 state, but if D=0, the output of the flip-flop goes to the 0 state. The next state Q(t+1) is determined from the D input. The relationship can be expressed by a characteristic equation: Q(t+1) = D D Flip-Flop has the advantage of having only one input (excluding ), but the disadvantage that its characteristic table does not have a no change condition Q(t+1) = Q(t). JK Flip-Flop Figure 4.6 Jk Flip-Flop 21

22 Inputs: J K C (for clock) Outputs: Q Q' The operation of the JK flip-flop is as follow. A JK Flip-Flop is a refinement of the SR flip-flop in that the indeterminate condition of the SR type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop, respectively. When inputs J and K are both equal to 1, a clock transition switches the outputs of the flip-flop to their complement state. Instead of the indeterminate condition of the SR flip-flop, the JK flip-flop has a complement condition Q(t+1) = Q (t) when both J and K are equal to T Flip-Flop Figure 4.8 T Flip-Flop

23 Inputs: T (for toggle) C (for clock) Outputs: Q Q' The operation of the T flip-flop is as follow. Most flip-flops are edge-triggered flip-flops, which means that the transition occurs at a specific level of the clock pulse. A positive-edge transition occurs on the rising edge of the clock signal. A negative-edge transition occurs on the falling edge of the clock signal. Another type of flip-flop is called a master-slave flip-flop that is basically two flipflops in series. Flip-flops can also include special input terminals for setting or clearing the flip-flop asynchronously. These inputs are usually called preset and clear and are useful for initialing the flip-flops before clocked operations are initiated. 1) EXPLAIN DE-MUX IN DETAIL. ANS. DeMultiplexer : 23 A decoder with an enable input can function as a demultiplexer. A demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2 n possible output lines. The selection of a specific output line is controlled by the bit values of n selection lines. The decoder of figure a can function as a demultiplexer if the E line is taken as a data input line and lines A and B are taken

24 as the selection lines. This is shown in figure 3.15(b). The single input variable E has a path to all four outputs, but the input information is directed to only one of the output lines, as specified by the binary value of the two selection lines A and B. For example, if the selection lines AB = 10; output D 2 will be the same as the input value E, while all other outputs are maintained at 1. Because decoder and demultiplexer operations are obtained from the same circuit, a decoder with an enable input is referred to as a decoder / demultiplexer. It is the enable input that makes the circuit a demultiplexer. Figure 3.15 Block Diagram for DeMultiplexer Truth table of Demultiplexer Inputs Outputs D S0 S1 F0 F1 F2 F Q-3 WRITE A SHORT NOTE OF FOLLOWING (ANY TWO) (20) 24

25 (1) EXPLAIN IC. ANS. Integrated Circuit : An integrated circuit is a small silicon semiconductor crystal, called a chip Which containing the electronic components for the digital gates. The various gates are interconnected inside the chip to form the required circuit. The chip is mounted in a ceramic or plastic container and connections are welded By thin gold wires. a) Small scale integration (SSI) : Small scale integration devices contain several independent gates in a single package. The number of gates is usually less than 10. b) Medium scale integration (MSI) : Medium scale integration devices contain 10 to 200 gates in a single package. They usually perform specific elementary digital functions such as decoders, adders and Registers. c) Large scale integration (LSI) : Large scale integration devices contain between 200 and a few thousands gates in a single package. They include digital systems such as processors, memory chips and programmable modules. d) Very large scale integration (VLSI) : Very large scale integration devices contain thousands of gates in a single package (1) EXPLAIN SHIFT REGISTER IN DETAIL. ANS. Registers : A register is a group of flip-flops capable of storing one bit of information. An n-bit register has a group of n flip-flops and is capable of storing any binary information of n bits. In addition to flip-flops, registers can have combinational gates that perform certain data-processing tasks. The gates control how and when new information is transferred into the registers. 25

26 The transfer of new information into a register is referred to as a register load. If the loading occurs simultaneously at a common clock pulse transition, we say that the load is done in parallel. The load input in a register determines the action to be taken with each clock pulse. When the load input is 1, the data from the input lines is transferred into the register's flip-flops. When the load input is 0, the data inputs are inhibited and the flipflop maintains its present state. Shift Registers : A register capable of shifting its binary information in one or both directions is called a shift register. Shift registers are constructed by connecting flip-flops in cascade, where the output of one flip-flop is connected to the input of the next flip-flop. All flip-flops receive common clock pulses that initiate the shift from one stage to the next. A serial input shift register has a single external input (called the serial input) entering an outermost flip-flop. Each remaining flip-flop uses the output of the previous flip-flop as its input, with the last flip-flop producing the external output (called the serial output). A register capable of shifting in one direction is called a unidirectional shift register. A register that can shift in both directions is called a bi-directional shift register. The most general shift register has the following capabilities: An input for clock pulses to synchronize all operations. A shift-right operation and a serial input line associated with the shift-right. A shift-left operation and a serial input line associated with the shift-left. 26

27 A parallel load operation and n input lines associated with the parallel transfer. N parallel output lines. A control state that leaves the information in the register unchanged even though clock pulses are applied continuously. A mode control to determine which type of register operation to perform. The simplest possible shift register is one that uses only flip-flops, as shown in the figure below. Figure bit shift register 27 Application of Shift Registers : Shift registers are often used to interface digital systems situated remotely from each other. For example, suppose that it is necessary to transmit an n-bit quantity between two points. If the distance between the source and the destination is too far, it will be expensive to use n lines to transmit the n bits in parallel. It may be more economical to use a single line and transmit the information serially one bit at a time. The transmitter loads the n-bit data in parallel into a shift register and then transmits the data from the serial output line. The receiver accepts the data serially

28 into a shift register through its serial input line. When the entire n bits are accumulated they can be taken from the outputs of the register in parallel. Thus the transmitter performs a parallel-to-serial conversion of data and the receiver converts the incoming serial data back to parallel data transfer. (2) BINARY ADDTION, SUBSTRACTION, BINARY DIVISON & BINARY MULTIPLICATION RULES. ANS. Bi BInary Addition :Binary addition is just like decimal addition. In the decimal system we tart With 0 and by successively adding 1, we reach 9. As the base of the system is 10, there are o Further symbols thus after 9 we count 10, the 1 becomes a carry to the tens position in the Positional system. In the binary system the count progresses as follows: 0,1,10,11,100,101 Addition Rules : Value Result Sum Carry Ex : Add the binary numbers and B)Binary Subtraction : The rules for binary subtraction are as follows.

29 29 Value Result D B Example : c C)Binary Multiplication : There are two methods of binary multiplication first is p aper method and second is computer method. Both method obey following rules. Multiplication Rules 0x0 = 0 0x1 = 0 1x0 = 0 1x1 = 1 Example : Multiply by Ans : d) Binary Division: Binary division Is obtained using the same procedure as decimal division. The rules

30 of binary division is given below. Binary division Rules 0/0 = undefined 0/1= 0 1/0= undefined 1/ 1=1 : Binary division rules are as follows. OR Q-3 ATTEMPT ANY TWO IN DETAIL. (20) 1) STACK ORGANIZATION Stack is a storage device that store the information in a manner in that item Store last that first item retrieve. I means that if follows LIFO policy. The Register that holds the address for stack is called stack pointer. Because Its value always point at the top item in the stack. There are two operations possible In stack i.e Push and pop. Register stack : 30

31 The fig shows the organization of 64 words register stack. As shown in figure Three items are place in stack that is x,y, and z item is top of the stack. So that Contain of SP is now 3. PUSH : Push operation is as below. SP SP+1 INCREMENT POINTER M[SP]] DR WRITE ITEM ON TOP OF THE STACJ IF SP =0 THEN (FULL 1) CHECK IF STACK IS FULL IF EMPTU 0 MARK THE STACK IS NOT EMPTY POP :POP OPERATION IS AS BELOW DR M[SP] READ 1 ITEM FROM TOP OF THE STACK SP SP-1 DECREMENT STACK POINTER IF (SP=0)THEN (EMPTY 0 CHECK STACK IS EMPTY FULL 0 MARK THE STACK IS NOT FULL )COUNTER.. A counter is a register capable of counting the number of clock pulse that have arrived at Its clock input. The binary counter can also be used to measure the frequency of the clock Cycle. There are two types of counters Asynchronous and synchronous counter. The Simplest binary counter is an Asynchronous counter. In which the number of FFs are Connected in series. Ripple counters are sometimes called asynchronous counters. The term asynchronous Refers to the events that do not occur at the same time. It means that all the FFs in this Counter are not simultaneously clocked. 4 BIT BINARY RIPPLE COUNTER 31

32 A four bit asynchronous counter is shown in the fig. It is consists of a series connection Of complementing flip flops. With the output of each flip flop connected to the CP Input of the next higer order flip flop. All j & k inputs are equal to 1. The small Circle in CP input indicates that the flip flop complements during a negative going Transition. 32

33 3.DMA Direct memory access is a sophisticated input output technique in which DMA controller Replaces the CPU and takes care of the access of input output device and the memory for Fast data transfers. Direct memory access(dma) is a feature of modern computers that allow certain hardware Subsystems within the computer access system memory for reading and or writing Independently of the central processing unit. Many hardware systems use DMA including Disk drive controllers, graphics cards, network cards and sound cards. Central processing unit often limited data transfer speed between secondary memory and Main memory. This problem can be resolved by removing CPU from the path. After Removing CPU different peripheral manage the memory buses directly For the Improvement of data transfer rate. This special kind of method is known as Direct Memory Access(DMA). It is important to note that during the DMA transfer CPU is idle And has no control of the memory bus. Advantage of DMA : Without DMA using programmed input/output (PIO) mode, the cpu is typically fully occupied for the entire duration of the read or write operation and is thus unavailable to perform other. With DMA the cpu would initiate the transfer, do other operations while the transfer is in progress, and receive an interrupt from the DMA controller once the operation has been done. This is especially useful in real time computing applications. WORKING OF DMA 33

34 Fig shows the two control signal that provides the DMA transfer. The bus request BR input is used by DMA to request the CPU to release the control of buses. When This input is active the CPU terminates the execution of current instruction And places the address bus, data bus and read write lines into a high impendence State. When DMA terminates the transfer it disable the bus request line. Then CPU again takes control of the data bus and returns its normal operation Q-4 ATTEMPT ANY TWO IN DETAIL. (20) (1) EXPLAIN GENERAL REGISTER ORG. ANS. General Register Organization : The set of registers in a computer are connected to the ALU using busses and Multiplexers. A 14-bit control word specifies two source registers (SELA & SELB), a destination register (SELD), and an operation (OPR). The registers can be specified using three bits each as follows: 34

35 35 A bus organization for seven CPU registers is shown in fig. The output of each register Connected to two multiplexers to perform the two buses A and B. The selection lines in each multiplexer select one register of the input data for the particular logic unit (ALU). The operation selected in the ALU determines the arithmetic or logic microoperations that is to be performed. The result of the micro-operation is available

36 for output data and also goes into the inputs of all the registers. The register that receives the information from the output bus is selected the decoder. The decoder activates one of the register load inputs, thus providing a transfer Path between the data in the output bus and the inputs of the selected destination register. The control unit that operates the CPU bus system directs the information flow through the registers and ALU selecting the various components in the system. (2) EXPLAIN LOGIC GATES IN DETAIL. ANS. Logic Gates : Binary information is represented in digital computers using electrical signals. These signals can be represented by voltage to specify one of two possible states. For example, if a wire contains a signal of 3 volts, it is considered to contain the digital value 1. Likewise, if the wire contains 1.5 volts, then it represents the digital value 0. The manipulation of binary information in a computer is done using logic circuits called gates. The gates are as shown in figure 1.2 Figure 1.2 Digital Logic Gates 36

37 3)EXPLAIN RPN. 37

38 38 ANS. ANS. Evaluating ordinary arithmetic expressions using a computer is difficult, particularly when an Expression consists of parenthesis and brackets. In this case an expression has to be scanned from Left as well from the right. These problems arise because in an ordinary arithmetic expression Operator is placed in between the two operands. Such types of ordinary expressions are called Infix expression. To overcome this problem the polish mathematician Lukasiewicz showed that a Arithmetic Expression can be represented in prefix or postfix Notation. In prefix notation (also known as Polish notation )the operator is placed before the operands while in postfix notation (also known as Reverse polish notation,rpn)the operator is placed after the operands. In short arithmetic expression can be represented in three different way as follows. A+B : INFIX NOTATION +AB : PREFIX OR POLISH NOTATION AB+ : POSTFIX OR REVERSE POLISH NOTATION (RPN) Advantage of Polish notations : RPN has number of advantages over infix notation for expressing algebraic formulas. 1) Any formula can be expressed without parenthesis. 2) It is convenient for evaluating formulas on computer with stack. 3) The infix operator has precedence which is undesirable. This disadvantages is eliminated By reverse polish notation. Evaluation of Arithmetic expressions: The main advantage of polish notation is that any formula can be expressed without Parenthesis. This is possible by combining reverse polish notation with a stack registers. Hence stack is very useful for handling long and complex problems involving arithmetic Expressions. This procedures is employed in some electronic calculators and computers. In this method The arithmetic expressions first converted reverse polish notation and then operands are pushed Into the stack in the order in which they appear. Let us discuss one example for more clarification of this procedure. Consider arithmetic

39 Expression. (6*3) + (5*9) In reverse polish notation it is expressed as 36*95*+ Q.4 DO AS DIRECTED (ANY THREE) (20) (1) PROVES THAT -AB + A C+BC=AB+A C ANS(1)L.H.S = AB+A C+BC = AB+A C+BC(A+A ) = AB+A C+BCA+A BC = AB+ABC+A C+A BC = AB(1+C) + A C (1+B) =AB(1)+ A C(1) = AB+A C R.H.S (2)PROVES THAT (A+B) (A +C)(B+C)=(A+B) (A +C) ANS.2) L.H.S= (A+B)(A +C)(B+C) =(AA +AC+BA +BC)(B+C) =(AC+BC+A B)(B+C) =(ACB+ACC+BBC+BCC+A BB+A BC) [BUT BB=B AND CC=C] =ACB+AC+BC+BC+A B+A BC NOW WRITE IN ORDER =ABC+BC+BC+A B+A BC+AC [BUT BC+BC=BC] =ABC+BC+A B+BC+A BC+AC =ABC+AC+A B+A BC+BC+BC =AC[1+B]+A B[1+C]+BC+BC =AC.1+A B.1+BC+BC =AC+A B+BC RHS=(A+B)(A +C) =AA +AC+BA +BC 0+AC+BC+A B WRITE IN ORDER =AC+A B+BC 39

40 (3)(X+Y)(X +Z)(Y+Z)=(X+Y)(X +Z). ANS. ) L.H.S = (X+Y)(X +Z)(Y+Z) =(X+Y)(X +Z)(Y+Z)+0 =(X+Y)(X +Z)(Y+Z)+X.X =(X+Y)(X +Z)(X+Y+Z)+(X +Y+Z) =(X+Y)(X+Y+Z)(X +Z)(X +Y+Z) =(X+Y)(1+Z)(X +Z)(1+Z) =(X+Y)(1)(X +Z)(1) =(X+Y)(X +Z) R.H.S. (4) SIMPLIFY EQUATION AND THEN FIND THE COMPLEMENT. F=XY+X Z+XYZ+X YZW ANS.4) =XY+XYX+X Z+X YZW =XY(1+Z)+X Z(1+YW) =XY(1)+X Z(1) 1+X=X =XY+X Z =X Y.XZ =(X +Y).(X+Z ) Q-5 EXPLAIN ANY TWO IN DETAIL. (20) (1) AC REGISTER IN DETAIL. ANS. Some processor unit separate one register from all other and call it an Accumulator Register. This register is also called AC or A register. The name of this register is derived from Arithmetic addition process. PROCESSOR WITH AN AC REGISTER 40

41 The accumulator register is a multipurpose register capable of performing not only add micro operation but many other micro operation as well. The fig shows the block diagram of AC register. Input B supplies one external source information & this information may come from other processors Or directly from the main memory of the computer. The A register supplies the other source information to the ALU., at input A. The result of operation is transfer back to the A register and replace its previous contain. The output from the A register may go to an external destination or into the input terminals of other processor register. A register using the sequence of micro operations. A 0 CLEAR A A A+R1 TRANSFER R1 TO A A A+R2 ADD R2 TO A. 41 Register A is first cleared then first number. In R1 is transferred into the accumulator register(a) by adding it to the present zero content to A. The second number in R2 is then added to the present value of A. The sum formed in A may be used for other computations or may be transferred to a required destination.

42 (2) WHAT IS INTERRUPT?EXPLAIN IN DETAIL. ANS. The concept of program interrupt is use to handle variety of problems that arrives out of Of normal program sequence. The interrupt facility is useful in multi programming Environment when two or more program resided in the memory at same time. The function of interrupt facility is to take care of data transfer of one or more program While another program is currently being executed. Types of interrupt : There are three major type of interrupt. 1) External interrupt : The external interrupt caused by external events, they comes from Input output devices, timing devices, timing devices of power supply or any other External sources. The external interrupt are asynchronous and they are independent of The program being executed at the time. 2) Internal interrupt: a) Internal interrupt is initiated by some exceptional condition cause By the program it self. This type of interrupt arise from illegal or erroneous use of an Instruction or data. It is known as traps. etc. b) Examples that cause the internal interrupts are register overflow, stack overflow, c) This interrupt are synchronous with program. If the program is rerun the internal interrupts will occur in the same place each time. 3) Software interrupt : a) Software interrupts is initiated by executing an instruction. Software Interrupt is a special call instruction that behave like an interrupt rather then subroutine Call. 42

43 b) The most common use of this interrupt is associated with supervisor switching from CPU. User mode to the supervisor mode. c) When input-output transfer is required the supervisor mode is requested by means of supervisor call instruction ) WHAT IS IOP? EXPLAIN IN DETAIL. ANS. INPUT-OUTPUT PROCESSOR Many computers combine the interface logic with the requirement for direct memory access into one unit. Such kind of arrangement call it an input output processor. It can handle many peripherals through a DMA and interrupt facility. In IOP the computer is divided into three modules as follows. 43

44 a).memory Unit b).cpu c) INPUT OUTPUT PROCESSOR i. Input output processor (IOP) may be classified as a processor with direct memory access. ii. Capability that communicates with I/O device. In this configuration computer system can be divided into a memory unit and a number of processor consist of CPU and one or more IOPs. Each IOP takes care of input and output task. THE IOP is similar to a CPU accept that it is designed to handle the details of processing. The IOP can fetch and execute its own instruction that is not possible in DMA controller. IOP I Instructions are specifically designed to facility tes I MODE transfers. In addition the IOP can perform Other processing task such as arithmetic, logic.branching and code translation. In most of the computer system CPU is master and IOP is slave. Processor CPU is assign the task of initiating all operation but I/O instructions are executed in IOP. OR Q-5 EXPALIN ANY TWO IN DETAIL. (1) PARITY BIT WITH ERROR DETACTION CODE. Ans. An error detection code is a binary code that detects digital errors during transmission.the detected errors can not be corrected but their present is indicated. PARITY BIT GENERATION 44 MESSAGE (XYZ) P(ODD) P(EVEN)

45 Parity : The most common error detection code use is parity bit. Parity bit is an extrabit With binary message to make the total number of 1(onece) is either odd or even. A message of 3 bit and two possible parity bits is shown in the table. The p(odd) bit is chosen in such a Way as to make the sum of 1 s odd. The p(even) is chosen to make the sum of all 1 s even. The even Parity scheme has the disadvantage of having a bit combination of all 0 s. while in the odd parity. There is always one bit of the four bits that constitute the message and P that is 1. The parity bit is handling as follows : 1)At sending end message is apply to parity generator. Where the required parity bit is generated. 2)At the receiving end all the incoming bits are apply to parity checker that checks the proper parityadopted. The error is detected if the check parity does not confirm to the adopter parity. 45 (2) FLOATING POINT REPRESENTATION. ANS. A number which has both an integer part as well as fractional part is called real Number or floating Point number. For example 0.956, 12.25, etc are called floating point decimal numbers. Similarly binary real numbers examples are 11.11, 1.101, etc. The part which is to t he left Of the decimal point as the integer part and part on the right side of the decimal point called the Fractional part. The real number can also be written as X Similarly the real number Can be written as 1.25 X Such a representation of floating point number isknown as scientific Representation. Thus in scientific representation the

46 number is expressed as a com notation of mantissa (or fractional) and an exponent. In short the Floating point representation of the number has two parts. The first part is representing a signed fix point number called mantissa. Second part is the Position of the decimal of binary point and its called exponent. For example the decimal number can be represented in floating point with a fraction and Exponent as can be represented as x 10 4 where Sign Mantissa Sign Exponent The zero in the sign bit indicates positive number. The decimal point shown in thema part is not Represented in physical form in computers. It is a logical decimal and its position is assumed by the factures. Thus in general the floating point is represented in the form n=m x r e Where m= mantissa (349802) e= Exponent (4) r =radix (10). (3) EXPLAIN NORMALIZATION. Ans. A normalization number is the number in which the most significant digit of the Mantissa Part is non zero. For example is normalized but x 10 2 is non normalized Number. Similarly in case of binary number x 2 4 in non normalize and x 2 5 Is normalization. In some computer only normalized numbers are stored. The mantissa part is shifted left till Its most significant digit becomes non zero and the exponent part is then adjusted accordingly. 46 The process of shifting of mantissa to the left to make the most significant bit to be non zero is called normalization. Ex : Represent in the floating point representation using 32 bit word length. Assume That 24 bits represents mantissa and 8 bits represent exponent. Solutions: = x 2 7 and exponent =7 or (111).

47 8 bits are used to represent exponent part. Hence exponent = ========================================================= 47