SYNTCOMP Synthesis Competition for Reactive Systems
|
|
|
- Godwin Thornton
- 5 years ago
- Views:
Transcription
1 SYNTCOMP Synthesis Competition for Reactive Systems Swen Jacobs (TU Graz) with Roderick Bloem and Rüdiger Ehlers Thanks to Timotheus Hell, Ayrat Khalimov, Robert Könighofer, and all participants! Swen Jacobs SYNTCOMP 1
2 Reactive Synthesis: State of the Art Currently: Tools are not easily comparable No standard language No comprehensive benchmark set We want to establish: a common language for synthesis problems a repository for synthesis benchmarks foster research by competition Swen Jacobs SYNTCOMP 2
3 Design Choices want a low entry-barrier for first competition low-level format (no translation from LTL) restriction to safety properties re-use existing standards extend well-known AIGER format from HWMCC verifiable correctness synthesis output in AIGER format can directly be checked by many model checkers Swen Jacobs SYNTCOMP 3
4 AIGER Format (for model checking) AIGER format defines system and spec as a circuit A, composed of And-Gates, Inverters, and Latches (or: transition system with state variables X and inputs I) For safety specs, single output is error; system is correct iff error is always false Swen Jacobs SYNTCOMP 4
5 Extended AIGER Format for Synthesis For synthesis problems, partition inputs I of system into controllable inputs C and uncontrollable inputs U A solution of synthesis problem is an AIG that includes original AIG A, and adds control structure B for inputs C such that resulting system is correct Swen Jacobs SYNTCOMP 5
6 Rules Realizability Track: determine realizability within time bound fastest tool gets most points Synthesis Track: find small implementation within time bound (points distributed according to ranking in size) result must be verifiable Sequential and Parallel subtracks in both cases Swen Jacobs SYNTCOMP 6
7 Benchmark Collection 569 benchmark instances Classes: simple building blocks (adder, counter, bit-shifter, etc.) AMBA case study, Generalized Buffer case study Robotics benchmarks: assembly line, moving obstacles translated benchmarks from Acacia+ Most benchmarks parameterized (size, safety translation) Swen Jacobs SYNTCOMP 7
8 Competition Entrants tools from 5 different research groups AbsSynthe Basil Demiurge realizer [Raskin Group, UL Bruxelles] [Ehlers, Uni/DFKI Bremen] [Könighofer, Seidl, TU Graz/JKU Linz] [Tentrup, Saarland University] Simple BDD Solver [Walker, Ryzhyk, NICTA/Uni Toronto] tools can compete in 3 configurations per track overall, 10 (or 19) different solver configurations Swen Jacobs SYNTCOMP 8
9 Results 6000 Realizability (Sequential) AbsSynthe_s1 AbsSynthe_s2 AbsSynthe_s3 Basil Demiurge learn Demiurge templ Realizer Simple BDD Solver Scores (1000 Pt. divided by 569 benchmarks, distributed over 8 tools): 1.Simple BDD Solver Realizer Basil 163 Demiurge 163 Swen Jacobs SYNTCOMP 9
10 Results Realizability (Parallel) Entrants: AbsSynthe, Basil, Demiurge, realizer Scores (1000 Pt. distributed over 4 tools, 569 benchmarks): 1. Basil realizer AbsSynthe 219 Swen Jacobs SYNTCOMP 10
11 Results Synthesis (Sequential) Selection of benchmarks: only realizable benchmarks that have been solved by at least one tool in realizability track, smaller number of variants of each benchmark. Entrants: AbsSynthe (x3), Basil, Demiurge (x2) Scores (1000 Pt. distributed over 6 tools, 157 benchmarks): 1. AbsSynthe (all) 256 (solved+checked* 143) 2. Demiurge (1) 249 (solved+checked 121) 3. Basil 131 (solved+checked* 117) Swen Jacobs SYNTCOMP 11
12 Results Synthesis (Parallel) Selection of benchmarks: same as Synthesis sequential. Entrants: AbsSynthe, Basil, Demiurge Scores (1000 Pt. distributed over 3 tools, 157 benchmarks): 1. Demiurge 393 (solved+checked 119) 2. AbsSynthe 352 (solved+checked* 143) 3. Basil 235 (solved+checked* 117) Swen Jacobs SYNTCOMP 12
13 Winners SYNTCOMP 2014 Synthesis (Seq.): Synthesis (Par.): AbsSynthe [UL Bruxelles] Demiurge [TU Graz/JKU Linz] Realizability (Seq.): Simple BDD Solver [NICTA/Uni Toronto] Realizability (Par.): Basil [Uni/DFKI Bremen] Award Ceremony: Today, 16:30 More Details: SYNT Workshop, Wednesday Further information: SYNTCOMP website & blog: SYNTCOMP mailinglist: Swen Jacobs SYNTCOMP 13
Section 6.8 Synthesis of Sequential Logic Page 1 of 8
Section 6.8 Synthesis of Sequential Logic Page of 8 6.8 Synthesis of Sequential Logic Steps:. Given a description (usually in words), develop the state diagram. 2. Convert the state diagram to a next-state
Logic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 05 February 23, 2012 Dohn Bowden 1 Today s Lecture Analysis of Clocked Sequential Circuits Chapter 13 2 Course Admin 3 Administrative Admin
Objectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
Lecture 8: Sequential Logic
Lecture 8: Sequential Logic Last lecture discussed how we can use digital electronics to do combinatorial logic we designed circuits that gave an immediate output when presented with a given set of inputs
EE 109 Homework 6 State Machine Design Name: Score:
EE 9 Homework 6 State Machine esign Name: Score: ue: See Blackboard Blackboard ONLY Submission. While the Blackboard submission may not require you to go through all the design steps (such as drawing out
Electrical and Telecommunications Engineering Technology_TCET3122/TC520. NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York
NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York DEPARTMENT: SUBJECT CODE AND TITLE: COURSE DESCRIPTION: REQUIRED: Electrical and Telecommunications Engineering Technology TCET 3122/TC
Sequential Logic Circuits
Sequential Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory
Chapter 4. Logic Design
Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table
Sequential Logic and Clocked Circuits
Sequential Logic and Clocked Circuits Clock or Timing Device Input Variables State or Memory Element Combinational Logic Elements From combinational logic, we move on to sequential logic. Sequential logic
Flip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
Introduction. Serial In - Serial Out Shift Registers (SISO)
Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
Chapter 5 Sequential Circuits
Logic and Computer Design Fundamentals Chapter 5 Sequential Circuits Part 2 Sequential Circuit Design Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)
CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division
CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division Objectives In this lab, you will see two types of sequential circuits: latches and flip-flops. Latches and flip-flops can be used
Previous Lecture Sequential Circuits. Slide Summary of contents covered in this lecture. (Refer Slide Time: 01:55)
Previous Lecture Sequential Circuits Digital VLSI System Design Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology, Madras Lecture No 7 Sequential Circuit Design Slide
Chapter 3. Boolean Algebra and Digital Logic
Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how
Microprocessor Design
Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004 To my wife and children Windy, Jonathan and Michelle Contents 1. Designing a Microprocessor... 2 1.1 Overview
problem maximum score 1 28pts 2 10pts 3 10pts 4 15pts 5 14pts 6 12pts 7 11pts total 100pts
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2002 4/5/02 Midterm Exam II Name: Solutions ID number:
6.3 Sequential Circuits (plus a few Combinational)
6.3 Sequential Circuits (plus a few Combinational) Logic Gates: Fundamental Building Blocks Introduction to Computer Science Robert Sedgewick and Kevin Wayne Copyright 2005 http://www.cs.princeton.edu/introcs
CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam
CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION Spring 2012 Question No: 1 ( Marks: 1 ) - Please choose one A SOP expression is equal to 1
CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division
CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division Objectives In this lab, we will see the sequential circuits latches and flip-flops. Latches and flip-flops can be used to build
EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true.
EXPERIMENT: 1 DATE: VERIFICATION OF BASIC LOGIC GATES AIM: To verify the truth tables of Basic Logic Gates NOT, OR, AND, NAND, NOR, Ex-OR and Ex-NOR. APPARATUS: mention the required IC numbers, Connecting
Bell. Program of Study. Accelerated Digital Electronics. Dave Bell TJHSST
Program of Study Accelerated Digital Electronics TJHSST Dave Bell Course Selection Guide Description: Students learn the basics of digital electronics technology as they engineer a complex electronic system.
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in
EE292: Fundamentals of ECE
EE292: Fundamentals of ECE Fall 2012 TTh 10:00-11:15 SEB 1242 Lecture 23 121120 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Combinatorial Logic Sequential Logic 3 Combinatorial Logic Circuits
Flip-flop and Registers
ECE 322 Digital Design with VHDL Flip-flop and Registers Lecture Textbook References n Sequential Logic Review Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2 nd or
CHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
CHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
Hardware Model Checking Competition 2014 CAV Edition
FLoC Citius, Maius, Potentius Faster, Bigger, More Powerful Armin Biere Johannes Kepler University Austria Keijo Heljanko Aalto University Finland Hardware Model Checking Competition CAV Edition FL oc
Logic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 03 February 09, 2012 Dohn Bowden 1 Today s Lecture Registers and Counters Chapter 12 2 Course Admin 3 Administrative Admin for tonight Syllabus
0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 Stop bits. 11-bit Serial Data format
Applications of Shift Registers The major application of a shift register is to convert between parallel and serial data. Shift registers are also used as keyboard encoders. The two applications of the
Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany
Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs
VeriLab. An introductory lab for using Verilog in digital design (first draft) VeriLab
VeriLab An introductory lab for using Verilog in digital design (first draft) VeriLab An introductory lab for using Verilog in digital design Verilog is a hardware description language useful for designing
Chapter 5 Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic Chih-Tsun Huang ( 黃稚存 ) http://nthucad.cs.nthu.edu.tw/~cthuang/ Department of Computer Science National Tsing Hua University Outline Introduction Storage Elements:
Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers
EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a S-R Latch and
Read-only memory (ROM) Digital logic: ALUs Sequential logic circuits. Don't cares. Bus
Digital logic: ALUs Sequential logic circuits CS207, Fall 2004 October 11, 13, and 15, 2004 1 Read-only memory (ROM) A form of memory Contents fixed when circuit is created n input lines for 2 n addressable
The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of
1 The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of the AND gate, you get the NAND gate etc. 2 One of the
We are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors
CSC258 Week 5 1 We are here Assembly Language Processors Arithmetic Logic Units Devices Finite State Machines Flip-flops Circuits Gates Transistors 2 Circuits using flip-flops Now that we know about flip-flops
Chapter Contents. Appendix A: Digital Logic. Some Definitions
A- Appendix A - Digital Logic A-2 Appendix A - Digital Logic Chapter Contents Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A. Introduction A.2 Combinational
A Combined Combinational-Sequential System
A Combined Combinational-Sequential System Object To construct a serial transmission circuit with a comparator to check the output. Parts () 7485 4-bit magnitude comparators (1) 74177 4-bit binary counter
1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.
![1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.](/thumbs/88/117492374.jpg "1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.")
[Question 1 is compulsory] 1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. Figure 1.1 b) Minimize the following Boolean functions:
DALHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 220. Experiment 4 - Latches and Flip-Flops
DLHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 0 Experiment - Latches and Flip-Flops Objectives:. To implement an RS latch memory element. To implement a JK
Assignment 2b. ASSIGNMENT 2b. due at the start of class, Wednesday Sept 25.
ASSIGNMENT 2b due at the start of class, Wednesday Sept 25. For each section of the assignment, the work that you are supposed to turn in is indicated in italics at the end of each problem or sub-problem.
EET2411 DIGITAL ELECTRONICS
5-8 Clocked D Flip-FlopFlop One data input. The output changes to the value of the input at either the positive going or negative going clock trigger. May be implemented with a J-K FF by tying the J input
12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009
12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009 Project Overview This project was originally titled Fast Fourier Transform Unit, but due to space and time constraints, the
Solar Power for Small Hall
Solar Power for Small Hall [image from www.speedace.info] The university is interested in installing a Solar Power Generating Facility on the roof of Small Hall. Project not official at university level
Why FPGAs? FPGA Overview. Why FPGAs?
Transistor-level Logic Circuits Positive Level-sensitive EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) January 28, 2003 John Wawrzynek Transistor Level clk clk clk Positive
Combinational Logic Design
Lab #2 Combinational Logic Design Objective: To introduce the design of some fundamental combinational logic building blocks. Preparation: Read the following experiment and complete the circuits where
Multiplexor (aka MUX) An example, yet VERY useful circuit!
Multiplexor (aka MUX) An example, yet VERY useful circuit! A B 0 1 Y S A B Y 0 0 x 0 0 1 x 1 1 x 0 0 1 x 1 1 S=1 S=0 Y = (S)? B:A; Y=S A+SB when S = 0: output A 1: output B 56 A 32-bit MUX Use 32 1-bit
Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology
Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology Course Title: Digital Logic Full Marks: 60 + 0 + 0 Course No.: CSC Pass Marks:
AIM: To study and verify the truth table of logic gates
EXPERIMENT: 1- LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various Logic gates and their output. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main
Physics 217A LAB 4 Spring 2016 Shift Registers Tri-State Bus. Part I
Physics 217A LAB 4 Spring 2016 Shift Registers Tri-State Bus Part I 0. In this part of the lab you investigate the 164 a serial-in, 8-bit-parallel-out, shift register. 1. Press in (near the LEDs) a 164.
Sequencing and Control
Sequencing and Control Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2016 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Source:
DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
27.2.2. DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 6. LECTURE (ANALYSIS AND SYNTHESIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS) 26/27 6. LECTURE Analysis and
Principles of Computer Architecture. Appendix A: Digital Logic
A-1 Appendix A - Digital Logic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
Rangkaian Sekuensial. Flip-flop
Rangkaian Sekuensial Rangkaian Sekuensial Flip-flop Combinational versus Sequential Functions Logic functions are categorized as being either combinational (sometimes referred to as combinatorial) or sequential.
Formal Timing Analysis of Digital Circuits
Formal Timing Analysis of Digital Circuits Qurat-ul-Ain and Osman Hasan System Analysis and Verification (SAVe Lab) National University of Sciences and Technology (NUST) Islamabad, Pakistan FTSCS 2018
Combinational / Sequential Logic
Digital Circuit Design and Language Combinational / Sequential Logic Chang, Ik Joon Kyunghee University Combinational Logic + The outputs are determined by the present inputs + Consist of input/output
Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24
2065 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 Time: 3 hours. Candidates are required to give their answers in their own words as for as practicable. Attempt any TWO questions:
Unit 11. Latches and Flip-Flops
Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,
Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012
1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date:
UNIVERSITY OF MASSACHUSSETS LOWELL Department of Electrical & Computer Engineering Course Syllabus for Logic Design Fall 2013
UNIVERSITY OF MASSACHUSSETS LOWELL Department of Electrical & Computer Engineering Course Syllabus for 16.265 Logic Design Fall 2013 I. General Information Section 201 Instructor: Professor Anh Tran Office
DIGITAL SYSTEM DESIGN UNIT I (2 MARKS)
DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) 1. Convert Binary number (111101100) 2 to Octal equivalent. 2. Convert Binary (1101100010011011) 2 to Hexadecimal equivalent. 3. Simplify the following Boolean function
The PeRIPLO Propositional Interpolator
The PeRIPLO Propositional Interpolator N. Sharygina Formal Verification and Security Group University of Lugano joint work with Leo Alt, Antti Hyvarinen, Grisha Fedyukovich and Simone Rollini October 2,
Combinational vs Sequential
Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs
Lecture 7: Sequential Networks
Lecture 7: Sequential Networks CSE 14: Components and Design Techniques for Digital Systems Spring 214 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego
CS T34-DIGITAL SYSTEM DESIGN Y2/S3
UNIT III Sequential Logic: Latches versus Flip Flops SR, D, JK, Master Slave Flip Flops Excitation table Conversion of Flip flops Counters: Asynchronous, synchronous, decade, presettable Shift Registers:
Computer Architecture and Organization
A-1 Appendix A - Digital Logic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Appendix A Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
TSIU03, SYSTEM DESIGN. How to Describe a HW Circuit
TSIU03 TSIU03, SYSTEM DESIGN How to Describe a HW Circuit Sometimes it is difficult for students to describe a hardware circuit. This document shows how to do it in order to present all the relevant information
DIGITAL ELECTRONICS MCQs
DIGITAL ELECTRONICS MCQs 1. A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180A DIGITAL SYSTEMS I Winter 2006
UNIVERSIT OF CLIFORNI, DVIS Department of Electrical and Computer Engineering EEC180 DIGITL SSTEMS I Winter 2006 L 5: STTIC HZRDS, LTCHES ND FLIP-FLOPS The purpose of this lab is to introduce a phenomenon
COE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Sequential Circuits Part 1 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Sequential Circuits Memory Elements Latches Flip-Flops Combinational
Digital Logic Design I
Digital Logic Design I Synchronous Sequential Logic Mustafa Kemal Uyguroğlu Sequential Circuits Asynchronous Inputs Combinational Circuit Memory Elements Outputs Synchronous Inputs Combinational Circuit
# "$ $ # %!"$!# &!'$("!)!"! $ # *!"! $ '!!$ #!!)! $ "# ' "
!" #!""! # "$ $ # %!"$!# &!'$("!)!"! $ # *!"! $ '!!$ #!!)! $ "# ' " % &! # Design a combinational logic circuit 10:4 encoder which has a 10-bit input (D9 to D0) and a 4-bit output. If bit position i of
The word digital implies information in computers is represented by variables that take a limited number of discrete values.
Class Overview Cover hardware operation of digital computers. First, consider the various digital components used in the organization and design. Second, go through the necessary steps to design a basic
Final Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
Experiment 8 Introduction to Latches and Flip-Flops and registers
Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
Integrated Circuit Design ELCT 701 (Winter 2017) Lecture 1: Introduction
1 Integrated Circuit Design ELCT 701 (Winter 2017) Lecture 1: Introduction Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 2 Course Overview Lecturer Teaching Assistant Course Team E-mail:
Registers and Counters
Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of
UNIVERSITI TEKNOLOGI MALAYSIA
SULIT Faculty of Computing UNIVERSITI TEKNOLOGI MALAYSIA FINAL EXAMINATION SEMESTER I, 2016 / 2017 SUBJECT CODE : SUBJECT NAME : SECTION : TIME : DATE/DAY : VENUES : INSTRUCTIONS : Answer all questions
EE 367 Lab Part 1: Sequential Logic
EE367: Introduction to Microprocessors Section 1.0 EE 367 Lab Part 1: Sequential Logic Contents 1 Preface 1 1.1 Things you need to do before arriving in the Laboratory............... 2 1.2 Summary of material
Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements
The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #3 Flip Flop Storage
CSE115: Digital Design Lecture 23: Latches & Flip-Flops
Faculty of Engineering CSE115: Digital Design Lecture 23: Latches & Flip-Flops Sections 7.1-7.2 Suggested Reading A Generic Digital Processor Building Blocks for Digital Architectures INPUT - OUTPUT Interconnect:
An automatic synchronous to asynchronous circuit convertor
An automatic synchronous to asynchronous circuit convertor Charles Brej Abstract The implementation methods of asynchronous circuits take time to learn, they take longer to design and verifying is very
Digital Circuits 4: Sequential Circuits
Digital Circuits 4: Sequential Circuits Created by Dave Astels Last updated on 2018-04-20 07:42:42 PM UTC Guide Contents Guide Contents Overview Sequential Circuits Onward Flip-Flops R-S Flip Flop Level
Course Administration
EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN Lecture 5: Sequential Logic - 2 Analysis of Clocked Sequential Systems 4/2/2 Avinash Kodi, kodi@ohio.edu Course Administration 2 Hw 2 due on today
IJMIE Volume 2, Issue 3 ISSN:
Development of Virtual Experiment on Flip Flops Using virtual intelligent SoftLab Bhaskar Y. Kathane* Pradeep B. Dahikar** Abstract: The scope of this paper includes study and implementation of Flip-flops.
FPGA Design. Part I - Hardware Components. Thomas Lenzi
FPGA Design Part I - Hardware Components Thomas Lenzi Approach We believe that having knowledge of the hardware components that compose an FPGA allow for better firmware design. Being able to visualise
6.S084 Tutorial Problems L05 Sequential Circuits
Preamble: Sequential Logic Timing 6.S084 Tutorial Problems L05 Sequential Circuits In Lecture 5 we saw that for D flip-flops to work correctly, the flip-flop s input should be stable around the rising
Chapter 8 Sequential Circuits
Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By 1 Chapter 8 Sequential Circuits 1 Classification of Combinational Logic 3 Sequential circuits
Introduction to Microprocessor & Digital Logic
ME262 Introduction to Microprocessor & Digital Logic (Sequential Logic) Summer 2 Sequential Logic Definition The output(s) of a sequential circuit depends d on the current and past states of the inputs,
Contents Circuits... 1
Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...
Final Examination (Open Katz, Calculators OK, 3 hours)
Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS
1 Hour Sample Test Papers: Sample Test Paper 1. Roll No.
6.1.2 Sample Test Papers: Sample Test Paper 1 Roll No. Institute Name: Course Code: EJ/EN/ET/EX/EV/IC/IE/IS/MU/DE/ED/ET/IU Subject: Principles of Digital Techniques Marks: 25 1 Hour 1. All questions are
Using Scan Side Channel to Detect IP Theft
Using Scan Side Channel to Detect IP Theft Leonid Azriel, Ran Ginosar, Avi Mendelson Technion Israel Institute of Technology Shay Gueron, University of Haifa and Intel Israel 1 Outline IP theft issue in
1.b. Realize a 5-input NOR function using 2-input NOR gates only.
. [3 points] Short Questions.a. Prove or disprove that the operators (,XOR) form a complete set. Remember that the operator ( ) is implication such that: A B A B.b. Realize a 5-input NOR function using
Administrative issues. Sequential logic
Administrative issues Midterm #1 will be given Tuesday, October 29, at 9:30am. The entire class period (75 minutes) will be used. Open book, open notes. DDPP sections: 2.1 2.6, 2.10 2.13, 3.1 3.4, 3.7,
Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET
Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET LABORATORY MANUAL EXPERIMENT NO. 1 ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE :
5: Sequential Logic Latches & Flip-flops
5: Sequential Logic Latches & Flip-flops Introduction Memory Elements Pulse-Triggered Latch S-R Latch Gated S-R Latch Gated D Latch Edge-Triggered Flip-flops S-R Flip-flop D Flip-flop J-K Flip-flop T Flip-flop
DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
26.3.9. DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: ANALYSIS AND SYNTHESIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS 2nd (Spring) term 25/26 5.
MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM
MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM MDETS UCTECH's Modular Digital Electronics Training System is a modular course covering the fundamentals, concepts, theory and applications of digital electronics.