Sequencing and Control

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1 Sequencing and Control Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2016 ldvan@cs.nctu.edu.tw Source: Prof. M. Morris Mano and Prof. Charles R. Kime, Logic and Computer Design Fundamentals, 3rd Edition, 2004, Prentice Hall.

2 Content Relationships DSP System: Adder, Mul, Filter Digital System Design Computer Architecture Embedded System: Galileo Embedded System: Edison 2

3 Outline Control Unit Algorithmic State Machines (ASM) ASM Chart Example: Binary Multiplier Hardwired Control Microprogrammed Control Summary 3

4 Digital System (1/3) Digital system: Datapath + Control unit Binary information stored in a DSP system and digital computer: data or control information Timing of a synchronous digital system: all regs are controlled by a master clock generator Two types of digital systems: i. Programmable system ii. Nonprogrammable system 4

5 Programmed system: Digital System (2/3) Instruction: a portion of the input to the processor specifies the op that the system is to perform which operands to use for the op where to place the results of the op which instr to execute next (optional) RAM or ROM: memory stores the instrs PC: program counter provides the addr in memory of the instr to be executed Executing an instr: activates the necessary sequence of -ops in the datapath that are required to perform the op specified by the instr 5

6 Digital System (3/3) Nonprogrammable system: needs not obtain instrs from memory no PC The control unit determines the ops to be performed and the sequence of those ops, based on only its inputs and the status bits 6

7 Algorithmic State Machines (ASM) ASM chart: Describe procedural steps and decision paths for the hardware algorithm. Describe a sequence of events and the timing relationship b/t the states of the control unit, and the actions that occur in the states in response to clock pulses. Hardware algorithm: Define the register transfer ops controlled by a sequencing mechanism of a data-processing task design both the datapath and the control unit 7

8 ASM Chart Four basic elements: ASM primitives i. State box ii.scalar decision box iv. Conditional output box iii. Vector decision box 8

9 State Box A rectangle-shaped box with: The symbolic name for the state marked outside the upper left top Containing register transfer operations and outputs activated within or while leaving the state An optional state code, if assigned, outside the upper right top (Symbolic Name) IDLE (Register transfers or outputs) R 0 RUN (Optional state code)

10 Scalar Decision Box A diamond-shape box with: One input path (entry point). One input condition, placed in the center of the box, that is tested. A TRUE exit path taken if the condition is true (logic 1). A FALSE exit path taken if the condition is false (logic 0). (False Condition) (True Condition) 0 (Input) 1 START 10

11 Vector Decision Box A hexagon-shaped box with: One input path (entry point). A vector of input conditions, placed in the center of the box, that is tested. Up to 2 n output paths. The path taken has a binary vector value that matches the vector input condition. 11

12 Conditional Output Box An oval-shaped box with: One input path from a decision box or decision boxes. One output path Register transfers or outputs that occur only if the conditional path to the box is taken. From Decision Box(es) (Register transfers or outputs) R 0 RUN 12

13 ASM Blocks An ASM block consists of one state box and all of the decision and conditional output boxes connected between the state box exit and entry paths to the same or other state boxes. 13

14 ASM Timing Behavior (1/2) ASM timing behavior: Any reg transfer for which conditions are satisfied within the ASM block will be executed when the clock event occurs. Register transfers occur at the clock while exiting the state - New value occurs in the next state! 14

15 ASM Timing Behavior (2/2) Clock cycle 1 Clock cycle 2 Clock cycle 3 Clock START Q 1 Q 0 State IDLE MUL 1 AVAIL A

16 Example: Binary Multiplier (1/3) Problem description for binary multiplier: Design a digital system that multiplies two unsigned binary numbers by successive shifts and adds. (n-bit multiplicand) (n-bit multiplier) = (2n-bit product) Paper and pencil method: Look at successive bits of the multiplier, LSB first. If the multiplier bit is 1, the multiplicand is copied down to enter into the addition to be performed later. Otherwise, 0 s are copied down. The numbers copied in successive lines are shifted one position to the left from the previous number copied. Finally, the numbers are added and their sum forms the product. 16

17 Example: Binary Multiplier (2/3) E.g.:

18 Example: Binary Multiplier (3/3) E.g.:

19 n-1 Counter P Block Diagram IN n Multiplicand Register B log 2 n n G (Go) Zero detect C out Parallel adder Control unit 4 Z Q o n Multiplier 0 C Shift register A Shift register Q n n Control signals Product OUT 19

20 ASM Chart (1/2) 1. The multiplicand (top operand) is loaded into register B. 2. The multiplier (bottom operand) is loaded into register Q. 3. Register C A is initialized to 0 when G becomes The partial products are formed in register C A Q. 5. Each multiplier bit, beginning with the LSB, is processed (if bit is 1, use adder to add B to partial product; if bit is 0, do nothing) 6. C A Q is shifted right using the shift register Partial product bits fill vacant locations in Q as multiplier is shifted out If overflow during addition, the outgoing carry is recovered from C during the right shift 7. Steps 5 and 6 are repeated until Counter P = 0 as detected by Zero detect. 1. Counter P is initialized in step 4 to n 1, n = number of bits in multiplier 20

21 ASM Chart (2/2) ASM chart for multiplier: Assumption Initially, the multiplicand is in B & the multiplier is in Q. ( The loading of these two regs is not handled by the multiplier control unit) 21

22 Microoperation in Datapath Datapath for the multiplier: -ops listed in the ASM chart datapath 22

23 Control Part Implementation of a control unit: i. The control signals of the -ops for the datapath ii. The sequencing of the control unit and -ops ASM chart Control unit i. A table that defines the control signals in terms of states and inputs output behavior of C.U. ii. A simplified ASM chart that represents only transitions from state to state next-state behavior of C.U. 23

24 Control Signal Table (1/2) Control Signals for Binary Multiplier Bloc k Dia g ram Mod u l e Mi cr oo pe ra ti on Contr o l Si gn al N a me Contr o l Exp r e ssi on Register A : A 0 I nitia liz e IDLE G A A + B Load MUL0 Q 0 C A Q sr C A Q Shift_dec M UL1 Register B : B IN Load_B LO ADB F lip-f lop C : C 0 C lea r _C IDLE G + MUL1 C C ou t Load Register Q : Q IN Load_Q LO ADQ C A Q sr C A Q Shift_dec Cou n ter P : P n 1 I nitia liz e P P 1 Shift_dec 24

25 Control Signal Table (2/2) Signals are defined on a register basis. LOADQ and LOADB are external signals controlled from the system using the multiplier and will not be considered a part of this design. Note that many of the control signals are reused for different registers. These control signals are the outputs of the control unit. 25

26 Sequencing Part of ASM Next-state behavior State diagram remove -ops, conditional output boxes, & any decision box not affecting the next state IDLE 00 0 G 1 MUL0 01 MUL Z 1 26

27 Hardwired Control Control Design Methods The procedure from Chapter 6 Not suitable for a large amount of input states Procedure specializations that use a single signal to represent each state Sequence Register and Decoder Sequence register with encoded states, e.g., 00, 01, 10, 11. Decoder outputs produce state signals, e.g., 0001, 0010, 0100, One Flip-flop per State Flip-flop outputs as state signals, e. g., 0001, 0010, 0100,

28 Sequence Reg and Decoder Design (1/6) Initially, use sequential circuit design techniques from Chapter 6. First, define: States: IDLE, MUL0, MUL1 Input Signals: G, Z, Q 0 (Q 0 affects outputs, not next state) Output Signals: Initialize, LOAD, Shift_Dec, Clear_C State Transition Diagram (Use sequencing ASM) Output Function Second, find State Assignments (two bits required) We will use two state bits to encode the three state IDLE, MUL0, and MUL1. State M1 M0 IDLE 0 0 MUL0 0 1 MUL1 1 0 Unused

29 Sequence Reg and Decoder Design (2/6) Assuming that state variables M1 and M0 are decoded into states, the next state part of the state table is: Current State Input G Z Next State M1 M0 IDLE IDLE IDLE IDLE MUL MUL MUL MUL Current State M1 M0 Input G Z Next State M1 M0 MUL MUL MUL MUL Unused 0 0 d d Unused 0 1 d d Unused 1 0 d d Unused 1 1 d d 29

30 Sequence Reg and Decoder Design (3/6) 30

31 Sequence Reg and Decoder Design (5/6) Finding the state equations for M1 and M0 is easier due to the decoded states: D M1 = MUL0 D M0 = IDLE G + MUL1 Z Note that since there are five variables, a K-map is harder to use, so we have directly written reduced equations. The output equations using the decoded states: Initialize = IDLE G Load = MUL0 Q 0 Clear_C = IDLE G + MUL1 Shift_dec = MUL1 31

32 Sequence Reg and Decoder Design (5/6) Doing multiple level optimization, extract IDLE G: Initialize = IDLE G D M1 = MUL0 D M0 = Initialize + MUL1 Z Load = MUL0 Q 0 Clear_C = Initialize + MUL1 Shift_dec = MUL1 The resulting circuit using flip-flops, a decoder, and the above equations is given on the next slide. 32

33 Sequence Reg and Decoder Design (6/6) G Initalize D M 0 Initialize Clear_C Z C DECODER A0 A IDLE MUL0 MUL1 Shift_dec M 1 D C Q 0 Load Two one-bit seq regs + One 2-to-4 line decoder 33

34 One Flip-Flop per State This method uses one flip-flop per state and a simple set of transformation rules to implement the circuit. The design starts with the ASM chart, and replaces 1. State boxes with flip-flops, 2. Scalar decision boxes with a demultiplexer with 2 outputs, 3. Vector decision boxes with a (partial) demultiplexer 4. Junctions with an OR gate 5. Conditional outputs with AND gates. 34

35 State Box Transformation Rules Each state box transforms to a D flip-flop Entry point is connected to the input. Exit point is connected to the Q output. Entry STATE Entry STATE D Q Exit Exit 35

36 Scalar Decision Box Transformation Rules Each decision box transforms to a demultiplexer Entry point is an enable" input. The condition is the select" input. Decoded outputs are the exit points. Entry Entry X 0 X 1 Exit 0 Exit 1 Exit 0 Exit 1 36

37 Vector Decision Box Transformation Rules Each Decision box transforms to a demultiplexer Entry point is an enable input. The conditions are the select inputs. Demultiplexer outputs are the exit points. (Binary Vector Values) (Vector of Input Conditions) (Binary Vector Values) 10 X 1 11 X 1, X X 0 0 Entry DEMUX EN D 0 Exit 0 A 1 D 1 Exit 1 A 0 Exit2 D 2 D 3 Exit 3 37

38 Junction Transformation Rules Where two or more entry points join, connect the entry variables to an OR gate The exit is the output of the OR gate. Entry 1 Entry 2 Entry 1 Entry 2 Exit Exit 38

39 Conditional Output Box Rules Entry point is an enable input. The control OUTPUT is the same signal as the exit value. Entry Enable Entry X 1 X OUTPUT Exit 1 Exit 1 OUTPUT 39

40 Multiplier Example: Flip-flop per State Design Logic Diagram D 1 D 0 40

41 Microprogrammed Control Microprogrammed control: a control unit with its binary control values stored as words in memory (control memory) Microinstruction: -instr each word in the control memory, specifies one or more - ops for the system Microprogram: -prog a sequence of -instrs Microprogramming: places some representation for combinations of values of control variables in words of ROM for use by the rest of the control logic via successive read ops. 41

42 Microprogrammed Control Unit Organization The general configuration of a -p control: CM: control memory CAR: control addr reg CDR: control data reg (optional) Next-addr generator 42

43 Microprogrammed Control for Binary Multiplier ASM charts for -p controls: the seq ckts must be Moore-type no conditional output box is permitted in the ASM chart 43

44 Design of a -p Control Unit Determine the bits in the control word for the - instrs. -instr control word format Determine the sizes of the ROM (CM) and the CAR. Determine the structure of the next-addr generator and design the sequence Write the -prog. 44

45 -instr Control Word Format -instr control word format: Control signals to datapath Control outputs Next-address information (Sequencing) 45

46 Next-Address Information Two typical approaches to define the addrs: Method 1: two-addr-per- instr method Include the two addrs in the -instr controlling the decision. Based on the value of the decision variable, one of the two addr values is loaded into the CAR. CAR: a reg w/ parallel load Adv.: permits the arbitrary assignment of addrs to states (no states need to be added for the desired sequencing) Disadv.: requires 2 addrs in each -instr (wide ROM) Method 2: parallel-load counter method Use a counter with parallel load as the CAR. One of the two addrs is obtained from the -instr, but the other is obtained by counting up the CAR. Adv.: requires at most 1 addr per -instr Disadv.: states may have to be added for the desired sequencing (slower system) 46

47 Control Word Format Example (1/3) -instr control word format of the binary multiplier: Control signals: DATAPATH Control outputs: none Sequencing: 2 addr fields NXTADD1 NXTADD0 SEL 47

48 Control Word Format Example (2/3) Control signals: DATAPATH 48

49 Control Word Format Example (3/3) 49

50 Sizes of the ROM and the CAR 50

51 Structure of the Next-Addr Generator CAR NXTADD1 NXTADD0 SEL 51

52 Structure of the Microprogrammed Control Unit 52

53 Microprogram 53

54 Summary Interaction b/t datapaths and control units Programmed vs. Nonprogrammed systems Algorithmic state machine (ASM): a means for representing and specifying control functions Example: Binary multiplier Hardwired control Basic design procedure Sequence reg plus decoder One flip-flop per state Microprogrammed control 54

Register Transfer Level in Verilog: Part II

Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part II Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National