CSE 140 Exam #3 Solution Tajana Simunic Rosing

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1 CSE 140 Exam #3 Solution Tajana Simunic Rosing Winter 2010 Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page. Do not separate the pages. This is a closed-book, closed-notes, no-calculator exam. You may only refer to one 81/2 x 11 page of handwritten notes. Do not look at anyone else s exam. Do not talk to anyone but an exam proctor during the exam. If you have a question, raise your hand and an exam proctor will come to you. You have 80 minutes to finish the exam. When the time is finished, you must stop writing. Write your answers in the space provided. To get the most partial credit, clearly and neatly show all steps of your work points points points points points points Total (100 points)

2 Problem 1 (10 points, 2pts each). Please circle all the answers that apply. a) Which of the following is the correct way to convert a JK flip-flop to a T flip-flop? i. J = T, K = T ii. J = T, K = T iii. J = TQ, K = TQ iv. J = TQ, K = T Q b) Which of the following conditions is/are likely to incur timing errors on a path that starts at flip-flop A and terminates at flip-flop B? i. The path is very short, and the clock skew causes the clock edge of flip-flop A to come slightly later than flip-flop B ii. The path is very long, and the clock skew causes the clock edge of flip-flop A to come slightly earlier than flip-flop B iii. The path is very short, and the clock skew causes the clock edge of flip-flop A to come slightly earlier than flip-flop B iv. The path is very long, and the clock skew causes the clock edge of flip-flop A to come slightly later than flip-flop B c) How many transistors are needed in the minimum CMOS implementation of function A+B(C+D)? i. 6 ii. 8 iii. 10 iv. 12 True or faulse? T F A+A B is the dual of A(A +B) DRAM is larger than SRAM because of the need to implement large capacitors. F R-type MIPS instructions are longer than J-type because R-type has more register operands T is equivalent to

3 Problem 2 (15 points) a) A partial timing diagram of the following circuit is shown below. Draw the waveform of D and Q assuming clock cycle time is 8ns and the following: Delay(AND) = Delay(OR) = 3ns, Delay(NOT) = 3ns, Delay(D FF) = 3ns, Setup(D FF) = 1ns, Hold(D FF) = 1ns. a b c D clk Q clk a b c D Q b) If the clock cycle time is 8ns, is there a problem with the operation of this circuit? If so, fix it without changing the clock cycle time or any of the logic gate/d-ff timing parameters. (Hint: you may change the combinational logic while keeping its functionality the same) Static hazard on D causes Q to capture incorrect signal in the last cycle Fix the static hazard: F = a c + a b + ac + bc

4 Problem 3(15 points) A 4-bit ring counter counts according to the sequence and repeats. A reset input places the counter into state Design this circuit using the following pre-designed components: A 2-to-4 decoder; A pre-designed, positive edge-triggered, 2-bit up-counter that counts as and repeats. In addition to the clock trigger input, this counter has a reset input which can be used to reset it to 00. The counter has outputs q1, q0. A minimum number of AND/OR/NOT gates, if needed.

5 Problem 4 (20 points) A recognizer has a single input X and two outputs (Z1 and Z2). The output Z1 becomes 1 each time the input sequence 101 is observed. Otherwise Z1=0. The output Z2=1 each time input sequence 011 is observed, otherwise Z2=0. For example, for the input X={ }, the outputs are: Z1={ }, and Z2={ }. a. (5 points)draw the Mealy style state diagram of this machine. b. (5 points) Implement the FSM using a shift register and a minimum number of gates.

6 c. Now add to your design a circuit that outputs a 1 each time you detect 13 instances of 3-bit input patterns that are different from both pattern Z1 and Z2. Use a standard counter and a minimum number of gates. (Hint: use Z1 and Z2 as your inputs).

Problem 5 (20 points) Given the state diagram in figure below, implement the state machine using a minimum number of connections on the PLA given below.

7 Problem 5 (20 points) Given the state diagram in figure below, implement the state machine using a minimum number of connections on the PLA given below. Make sure to define all relevant signals/connections. Note that this PLA uses T-flip flops! State encoding is given as: A=00, B=01, C=10, D=11. Show all your work. T 0 =Q 0 I+Q 0 I T 1 =Q 1 Q 0 +I Q 0

8 Problem 6 (20 points) a) Create a high-level state machine that describes the following system behavior. The machine sequentially reads 32 numbers from a 32-word register file and identify the length of the longest sequence of identical values. Example: length of the longest sequence of identical values = 3 start Addr = 32 end Addr = 0 length = 0 Max=0 Reg_n = V[addr] Addr++ Reg_o = Reg_n Reg_n = V[addr] Addr++ Addr < 32 && Reg_o < > Reg_n Addr < 32 && Reg_o = Reg_n Length = 0 Max = length Length <= Max Length > Max Length ++

9 b) Draw the block diagram of how controller connects to the datapath. Show details of the datapath, and label all signals. You can use memory, register, comparator, counter and adder/subtractor in your datapath design. datapath Controller rd rd addr MEM ld_val ld Reg_n ld Reg_o last Addr_inc Rst up Addr counter = equal clr = 32 rst_length length_inc Rst up Length counter ld MAX Rst gte ld_max >

10 This page is intentionally left blank. Use as scratch paper or to provide additional answers.

CSE 140 Exam #3 Tajana Simunic Rosing

CSE 140 Exam #3 Tajana Simunic Rosing Winter 2010 Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page. Do not separate the